include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53
  54 /* Architectures are the sum of the base and extensions.  */
  55 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  56                                                  AARCH64_FEATURE_FP  \
  57                                                  | AARCH64_FEATURE_SIMD)
  58 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  59                                                  AARCH64_FEATURE_FP  \
  60                                                  | AARCH64_FEATURE_SIMD \
  61                                                  | AARCH64_FEATURE_CRC  \
  62                                                  | AARCH64_FEATURE_V8_1 \
  63                                                  | AARCH64_FEATURE_LSE  \
  64                                                  | AARCH64_FEATURE_PAN  \
  65                                                  | AARCH64_FEATURE_LOR  \
  66                                                  | AARCH64_FEATURE_RDMA)
  67 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  68                                                  AARCH64_FEATURE_V8_2   \
  69                                                  | AARCH64_FEATURE_F16  \
  70                                                  | AARCH64_FEATURE_RAS  \
  71                                                  | AARCH64_FEATURE_FP   \
  72                                                  | AARCH64_FEATURE_SIMD \
  73                                                  | AARCH64_FEATURE_CRC  \
  74                                                  | AARCH64_FEATURE_V8_1 \
  75                                                  | AARCH64_FEATURE_LSE  \
  76                                                  | AARCH64_FEATURE_PAN  \
  77                                                  | AARCH64_FEATURE_LOR  \
  78                                                  | AARCH64_FEATURE_RDMA)
  79
  80 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  81 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  82
  83 /* CPU-specific features.  */
  84 typedef unsigned long aarch64_feature_set;
  85
  86 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  87   (((CPU) & (FEAT)) != 0)
  88
  89 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  90   do                                            \
  91     {                                           \
  92       (TARG) = (F1) | (F2);                     \
  93     }                                           \
  94   while (0)
  95
  96 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) &~ (F2);                    \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 104
 105 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
 106   (((OPC) & (FEAT)) != 0)
 107
 108 enum aarch64_operand_class
 109 {
 110   AARCH64_OPND_CLASS_NIL,
 111   AARCH64_OPND_CLASS_INT_REG,
 112   AARCH64_OPND_CLASS_MODIFIED_REG,
 113   AARCH64_OPND_CLASS_FP_REG,
 114   AARCH64_OPND_CLASS_SIMD_REG,
 115   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 116   AARCH64_OPND_CLASS_SISD_REG,
 117   AARCH64_OPND_CLASS_SIMD_REGLIST,
 118   AARCH64_OPND_CLASS_CP_REG,
 119   AARCH64_OPND_CLASS_ADDRESS,
 120   AARCH64_OPND_CLASS_IMMEDIATE,
 121   AARCH64_OPND_CLASS_SYSTEM,
 122   AARCH64_OPND_CLASS_COND,
 123 };
 124
 125 /* Operand code that helps both parsing and coding.
 126    Keep AARCH64_OPERANDS synced.  */
 127
 128 enum aarch64_opnd
 129 {
 130   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 131
 132   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 133   AARCH64_OPND_Rn,      /* Integer register as source.  */
 134   AARCH64_OPND_Rm,      /* Integer register as source.  */
 135   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 136   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 137   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 138   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 139   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 140
 141   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 142   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 143   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 144   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 145   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 146
 147   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 148   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 149   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 150   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 151   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 152   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 153
 154   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 155   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 156   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 157
 158   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 159   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 160   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 161   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 162   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 163   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 164   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 165   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 166   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 167   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 168   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 169                            structure to all lanes.  */
 170   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 171
 172   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 173   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 174
 175   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 176   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 177   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 178   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 179   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 180   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 181   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 182                            (no encoding).  */
 183   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 184   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 185   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 186   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 187   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 188   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 189   AARCH64_OPND_IMM,     /* Immediate.  */
 190   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 191   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 192   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 193   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 194   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 195   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 196   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 197   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 198                            each condition flag.  */
 199
 200   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 201   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 202   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 203   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 204   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 205
 206   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 207   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 208
 209   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 210   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 211   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 212   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 213   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 214
 215   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 216   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 217   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 218   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 219   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 220                                    negative or unaligned and there is
 221                                    no writeback allowed.  This operand code
 222                                    is only used to support the programmer-
 223                                    friendly feature of using LDR/STR as the
 224                                    the mnemonic name for LDUR/STUR instructions
 225                                    wherever there is no ambiguity.  */
 226   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 227   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 228   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 229
 230   AARCH64_OPND_SYSREG,          /* System register operand.  */
 231   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 232   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 233   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 234   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 235   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 236   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 237   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 238   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 239 };
 240
 241 /* Qualifier constrains an operand.  It either specifies a variant of an
 242    operand type or limits values available to an operand type.
 243
 244    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 245
 246 enum aarch64_opnd_qualifier
 247 {
 248   /* Indicating no further qualification on an operand.  */
 249   AARCH64_OPND_QLF_NIL,
 250
 251   /* Qualifying an operand which is a general purpose (integer) register;
 252      indicating the operand data size or a specific register.  */
 253   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 254   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 255   AARCH64_OPND_QLF_WSP, /* WSP.  */
 256   AARCH64_OPND_QLF_SP,  /* SP.  */
 257
 258   /* Qualifying an operand which is a floating-point register, a SIMD
 259      vector element or a SIMD vector element list; indicating operand data
 260      size or the size of each SIMD vector element in the case of a SIMD
 261      vector element list.
 262      These qualifiers are also used to qualify an address operand to
 263      indicate the size of data element a load/store instruction is
 264      accessing.
 265      They are also used for the immediate shift operand in e.g. SSHR.  Such
 266      a use is only for the ease of operand encoding/decoding and qualifier
 267      sequence matching; such a use should not be applied widely; use the value
 268      constraint qualifiers for immediate operands wherever possible.  */
 269   AARCH64_OPND_QLF_S_B,
 270   AARCH64_OPND_QLF_S_H,
 271   AARCH64_OPND_QLF_S_S,
 272   AARCH64_OPND_QLF_S_D,
 273   AARCH64_OPND_QLF_S_Q,
 274
 275   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 276      register list; indicating register shape.
 277      They are also used for the immediate shift operand in e.g. SSHR.  Such
 278      a use is only for the ease of operand encoding/decoding and qualifier
 279      sequence matching; such a use should not be applied widely; use the value
 280      constraint qualifiers for immediate operands wherever possible.  */
 281   AARCH64_OPND_QLF_V_8B,
 282   AARCH64_OPND_QLF_V_16B,
 283   AARCH64_OPND_QLF_V_4H,
 284   AARCH64_OPND_QLF_V_8H,
 285   AARCH64_OPND_QLF_V_2S,
 286   AARCH64_OPND_QLF_V_4S,
 287   AARCH64_OPND_QLF_V_1D,
 288   AARCH64_OPND_QLF_V_2D,
 289   AARCH64_OPND_QLF_V_1Q,
 290
 291   /* Constraint on value.  */
 292   AARCH64_OPND_QLF_imm_0_7,
 293   AARCH64_OPND_QLF_imm_0_15,
 294   AARCH64_OPND_QLF_imm_0_31,
 295   AARCH64_OPND_QLF_imm_0_63,
 296   AARCH64_OPND_QLF_imm_1_32,
 297   AARCH64_OPND_QLF_imm_1_64,
 298
 299   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 300      or shift-ones.  */
 301   AARCH64_OPND_QLF_LSL,
 302   AARCH64_OPND_QLF_MSL,
 303
 304   /* Special qualifier helping retrieve qualifier information during the
 305      decoding time (currently not in use).  */
 306   AARCH64_OPND_QLF_RETRIEVE,
 307 };
 308 \f
 309 /* Instruction class.  */
 310
 311 enum aarch64_insn_class
 312 {
 313   addsub_carry,
 314   addsub_ext,
 315   addsub_imm,
 316   addsub_shift,
 317   asimdall,
 318   asimddiff,
 319   asimdelem,
 320   asimdext,
 321   asimdimm,
 322   asimdins,
 323   asimdmisc,
 324   asimdperm,
 325   asimdsame,
 326   asimdshf,
 327   asimdtbl,
 328   asisddiff,
 329   asisdelem,
 330   asisdlse,
 331   asisdlsep,
 332   asisdlso,
 333   asisdlsop,
 334   asisdmisc,
 335   asisdone,
 336   asisdpair,
 337   asisdsame,
 338   asisdshf,
 339   bitfield,
 340   branch_imm,
 341   branch_reg,
 342   compbranch,
 343   condbranch,
 344   condcmp_imm,
 345   condcmp_reg,
 346   condsel,
 347   cryptoaes,
 348   cryptosha2,
 349   cryptosha3,
 350   dp_1src,
 351   dp_2src,
 352   dp_3src,
 353   exception,
 354   extract,
 355   float2fix,
 356   float2int,
 357   floatccmp,
 358   floatcmp,
 359   floatdp1,
 360   floatdp2,
 361   floatdp3,
 362   floatimm,
 363   floatsel,
 364   ldst_immpost,
 365   ldst_immpre,
 366   ldst_imm9,    /* immpost or immpre */
 367   ldst_pos,
 368   ldst_regoff,
 369   ldst_unpriv,
 370   ldst_unscaled,
 371   ldstexcl,
 372   ldstnapair_offs,
 373   ldstpair_off,
 374   ldstpair_indexed,
 375   loadlit,
 376   log_imm,
 377   log_shift,
 378   lse_atomic,
 379   movewide,
 380   pcreladdr,
 381   ic_system,
 382   testbranch,
 383 };
 384
 385 /* Opcode enumerators.  */
 386
 387 enum aarch64_op
 388 {
 389   OP_NIL,
 390   OP_STRB_POS,
 391   OP_LDRB_POS,
 392   OP_LDRSB_POS,
 393   OP_STRH_POS,
 394   OP_LDRH_POS,
 395   OP_LDRSH_POS,
 396   OP_STR_POS,
 397   OP_LDR_POS,
 398   OP_STRF_POS,
 399   OP_LDRF_POS,
 400   OP_LDRSW_POS,
 401   OP_PRFM_POS,
 402
 403   OP_STURB,
 404   OP_LDURB,
 405   OP_LDURSB,
 406   OP_STURH,
 407   OP_LDURH,
 408   OP_LDURSH,
 409   OP_STUR,
 410   OP_LDUR,
 411   OP_STURV,
 412   OP_LDURV,
 413   OP_LDURSW,
 414   OP_PRFUM,
 415
 416   OP_LDR_LIT,
 417   OP_LDRV_LIT,
 418   OP_LDRSW_LIT,
 419   OP_PRFM_LIT,
 420
 421   OP_ADD,
 422   OP_B,
 423   OP_BL,
 424
 425   OP_MOVN,
 426   OP_MOVZ,
 427   OP_MOVK,
 428
 429   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 430   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 431   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 432
 433   OP_MOV_V,             /* MOV alias for moving vector register.  */
 434
 435   OP_ASR_IMM,
 436   OP_LSR_IMM,
 437   OP_LSL_IMM,
 438
 439   OP_BIC,
 440
 441   OP_UBFX,
 442   OP_BFXIL,
 443   OP_SBFX,
 444   OP_SBFIZ,
 445   OP_BFI,
 446   OP_BFC,               /* ARMv8.2.  */
 447   OP_UBFIZ,
 448   OP_UXTB,
 449   OP_UXTH,
 450   OP_UXTW,
 451
 452   OP_CINC,
 453   OP_CINV,
 454   OP_CNEG,
 455   OP_CSET,
 456   OP_CSETM,
 457
 458   OP_FCVT,
 459   OP_FCVTN,
 460   OP_FCVTN2,
 461   OP_FCVTL,
 462   OP_FCVTL2,
 463   OP_FCVTXN_S,          /* Scalar version.  */
 464
 465   OP_ROR_IMM,
 466
 467   OP_SXTL,
 468   OP_SXTL2,
 469   OP_UXTL,
 470   OP_UXTL2,
 471
 472   OP_TOTAL_NUM,         /* Pseudo.  */
 473 };
 474
 475 /* Maximum number of operands an instruction can have.  */
 476 #define AARCH64_MAX_OPND_NUM 6
 477 /* Maximum number of qualifier sequences an instruction can have.  */
 478 #define AARCH64_MAX_QLF_SEQ_NUM 10
 479 /* Operand qualifier typedef; optimized for the size.  */
 480 typedef unsigned char aarch64_opnd_qualifier_t;
 481 /* Operand qualifier sequence typedef.  */
 482 typedef aarch64_opnd_qualifier_t        \
 483           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 484
 485 /* FIXME: improve the efficiency.  */
 486 static inline bfd_boolean
 487 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 488 {
 489   int i;
 490   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 491     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 492       return FALSE;
 493   return TRUE;
 494 }
 495
 496 /* This structure holds information for a particular opcode.  */
 497
 498 struct aarch64_opcode
 499 {
 500   /* The name of the mnemonic.  */
 501   const char *name;
 502
 503   /* The opcode itself.  Those bits which will be filled in with
 504      operands are zeroes.  */
 505   aarch64_insn opcode;
 506
 507   /* The opcode mask.  This is used by the disassembler.  This is a
 508      mask containing ones indicating those bits which must match the
 509      opcode field, and zeroes indicating those bits which need not
 510      match (and are presumably filled in by operands).  */
 511   aarch64_insn mask;
 512
 513   /* Instruction class.  */
 514   enum aarch64_insn_class iclass;
 515
 516   /* Enumerator identifier.  */
 517   enum aarch64_op op;
 518
 519   /* Which architecture variant provides this instruction.  */
 520   const aarch64_feature_set *avariant;
 521
 522   /* An array of operand codes.  Each code is an index into the
 523      operand table.  They appear in the order which the operands must
 524      appear in assembly code, and are terminated by a zero.  */
 525   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 526
 527   /* A list of operand qualifier code sequence.  Each operand qualifier
 528      code qualifies the corresponding operand code.  Each operand
 529      qualifier sequence specifies a valid opcode variant and related
 530      constraint on operands.  */
 531   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 532
 533   /* Flags providing information about this instruction */
 534   uint32_t flags;
 535 };
 536
 537 typedef struct aarch64_opcode aarch64_opcode;
 538
 539 /* Table describing all the AArch64 opcodes.  */
 540 extern aarch64_opcode aarch64_opcode_table[];
 541
 542 /* Opcode flags.  */
 543 #define F_ALIAS (1 << 0)
 544 #define F_HAS_ALIAS (1 << 1)
 545 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 546    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 547 #define F_P1 (1 << 2)
 548 #define F_P2 (2 << 2)
 549 #define F_P3 (3 << 2)
 550 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 551 #define F_COND (1 << 4)
 552 /* Instruction has the field of 'sf'.  */
 553 #define F_SF (1 << 5)
 554 /* Instruction has the field of 'size:Q'.  */
 555 #define F_SIZEQ (1 << 6)
 556 /* Floating-point instruction has the field of 'type'.  */
 557 #define F_FPTYPE (1 << 7)
 558 /* AdvSIMD scalar instruction has the field of 'size'.  */
 559 #define F_SSIZE (1 << 8)
 560 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 561 #define F_T (1 << 9)
 562 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 563 #define F_GPRSIZE_IN_Q (1 << 10)
 564 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 565 #define F_LDS_SIZE (1 << 11)
 566 /* Optional operand; assume maximum of 1 operand can be optional.  */
 567 #define F_OPD0_OPT (1 << 12)
 568 #define F_OPD1_OPT (2 << 12)
 569 #define F_OPD2_OPT (3 << 12)
 570 #define F_OPD3_OPT (4 << 12)
 571 #define F_OPD4_OPT (5 << 12)
 572 /* Default value for the optional operand when omitted from the assembly.  */
 573 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 574 /* Instruction that is an alias of another instruction needs to be
 575    encoded/decoded by converting it to/from the real form, followed by
 576    the encoding/decoding according to the rules of the real opcode.
 577    This compares to the direct coding using the alias's information.
 578    N.B. this flag requires F_ALIAS to be used together.  */
 579 #define F_CONV (1 << 20)
 580 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 581    friendly pseudo instruction available only in the assembly code (thus will
 582    not show up in the disassembly).  */
 583 #define F_PSEUDO (1 << 21)
 584 /* Instruction has miscellaneous encoding/decoding rules.  */
 585 #define F_MISC (1 << 22)
 586 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 587 #define F_N (1 << 23)
 588 /* Opcode dependent field.  */
 589 #define F_OD(X) (((X) & 0x7) << 24)
 590 /* Instruction has the field of 'sz'.  */
 591 #define F_LSE_SZ (1 << 27)
 592 /* Next bit is 28.  */
 593
 594 static inline bfd_boolean
 595 alias_opcode_p (const aarch64_opcode *opcode)
 596 {
 597   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 598 }
 599
 600 static inline bfd_boolean
 601 opcode_has_alias (const aarch64_opcode *opcode)
 602 {
 603   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 604 }
 605
 606 /* Priority for disassembling preference.  */
 607 static inline int
 608 opcode_priority (const aarch64_opcode *opcode)
 609 {
 610   return (opcode->flags >> 2) & 0x3;
 611 }
 612
 613 static inline bfd_boolean
 614 pseudo_opcode_p (const aarch64_opcode *opcode)
 615 {
 616   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 617 }
 618
 619 static inline bfd_boolean
 620 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 621 {
 622   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 623     ? TRUE : FALSE;
 624 }
 625
 626 static inline aarch64_insn
 627 get_optional_operand_default_value (const aarch64_opcode *opcode)
 628 {
 629   return (opcode->flags >> 15) & 0x1f;
 630 }
 631
 632 static inline unsigned int
 633 get_opcode_dependent_value (const aarch64_opcode *opcode)
 634 {
 635   return (opcode->flags >> 24) & 0x7;
 636 }
 637
 638 static inline bfd_boolean
 639 opcode_has_special_coder (const aarch64_opcode *opcode)
 640 {
 641   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 642           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 643     : FALSE;
 644 }
 645 \f
 646 struct aarch64_name_value_pair
 647 {
 648   const char *  name;
 649   aarch64_insn  value;
 650 };
 651
 652 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 653 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 654 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 655
 656 typedef struct
 657 {
 658   const char *  name;
 659   aarch64_insn  value;
 660   uint32_t      flags;
 661 } aarch64_sys_reg;
 662
 663 extern const aarch64_sys_reg aarch64_sys_regs [];
 664 extern const aarch64_sys_reg aarch64_pstatefields [];
 665 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 666 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 667                                                 const aarch64_sys_reg *);
 668 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 669                                                     const aarch64_sys_reg *);
 670
 671 typedef struct
 672 {
 673   const char *name;
 674   uint32_t value;
 675   uint32_t flags ;
 676 } aarch64_sys_ins_reg;
 677
 678 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 679
 680 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 681 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 682 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 683 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 684
 685 /* Shift/extending operator kinds.
 686    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 687 enum aarch64_modifier_kind
 688 {
 689   AARCH64_MOD_NONE,
 690   AARCH64_MOD_MSL,
 691   AARCH64_MOD_ROR,
 692   AARCH64_MOD_ASR,
 693   AARCH64_MOD_LSR,
 694   AARCH64_MOD_LSL,
 695   AARCH64_MOD_UXTB,
 696   AARCH64_MOD_UXTH,
 697   AARCH64_MOD_UXTW,
 698   AARCH64_MOD_UXTX,
 699   AARCH64_MOD_SXTB,
 700   AARCH64_MOD_SXTH,
 701   AARCH64_MOD_SXTW,
 702   AARCH64_MOD_SXTX,
 703 };
 704
 705 bfd_boolean
 706 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 707
 708 enum aarch64_modifier_kind
 709 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 710 /* Condition.  */
 711
 712 typedef struct
 713 {
 714   /* A list of names with the first one as the disassembly preference;
 715      terminated by NULL if fewer than 3.  */
 716   const char *names[3];
 717   aarch64_insn value;
 718 } aarch64_cond;
 719
 720 extern const aarch64_cond aarch64_conds[16];
 721
 722 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 723 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 724 \f
 725 /* Structure representing an operand.  */
 726
 727 struct aarch64_opnd_info
 728 {
 729   enum aarch64_opnd type;
 730   aarch64_opnd_qualifier_t qualifier;
 731   int idx;
 732
 733   union
 734     {
 735       struct
 736         {
 737           unsigned regno;
 738         } reg;
 739       struct
 740         {
 741           unsigned regno : 5;
 742           unsigned index : 4;
 743         } reglane;
 744       /* e.g. LVn.  */
 745       struct
 746         {
 747           unsigned first_regno : 5;
 748           unsigned num_regs : 3;
 749           /* 1 if it is a list of reg element.  */
 750           unsigned has_index : 1;
 751           /* Lane index; valid only when has_index is 1.  */
 752           unsigned index : 4;
 753         } reglist;
 754       /* e.g. immediate or pc relative address offset.  */
 755       struct
 756         {
 757           int64_t value;
 758           unsigned is_fp : 1;
 759         } imm;
 760       /* e.g. address in STR (register offset).  */
 761       struct
 762         {
 763           unsigned base_regno;
 764           struct
 765             {
 766               union
 767                 {
 768                   int imm;
 769                   unsigned regno;
 770                 };
 771               unsigned is_reg;
 772             } offset;
 773           unsigned pcrel : 1;           /* PC-relative.  */
 774           unsigned writeback : 1;
 775           unsigned preind : 1;          /* Pre-indexed.  */
 776           unsigned postind : 1;         /* Post-indexed.  */
 777         } addr;
 778       const aarch64_cond *cond;
 779       /* The encoding of the system register.  */
 780       aarch64_insn sysreg;
 781       /* The encoding of the PSTATE field.  */
 782       aarch64_insn pstatefield;
 783       const aarch64_sys_ins_reg *sysins_op;
 784       const struct aarch64_name_value_pair *barrier;
 785       const struct aarch64_name_value_pair *prfop;
 786     };
 787
 788   /* Operand shifter; in use when the operand is a register offset address,
 789      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 790   struct
 791     {
 792       enum aarch64_modifier_kind kind;
 793       int amount;
 794       unsigned operator_present: 1;     /* Only valid during encoding.  */
 795       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 796       unsigned amount_present: 1;
 797     } shifter;
 798
 799   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 800                            to be done on it.  In some (but not all) of these
 801                            cases, we need to tell libopcodes to skip the
 802                            constraint checking and the encoding for this
 803                            operand, so that the libopcodes can pick up the
 804                            right opcode before the operand is fixed-up.  This
 805                            flag should only be used during the
 806                            assembling/encoding.  */
 807   unsigned present:1;   /* Whether this operand is present in the assembly
 808                            line; not used during the disassembly.  */
 809 };
 810
 811 typedef struct aarch64_opnd_info aarch64_opnd_info;
 812
 813 /* Structure representing an instruction.
 814
 815    It is used during both the assembling and disassembling.  The assembler
 816    fills an aarch64_inst after a successful parsing and then passes it to the
 817    encoding routine to do the encoding.  During the disassembling, the
 818    disassembler calls the decoding routine to decode a binary instruction; on a
 819    successful return, such a structure will be filled with information of the
 820    instruction; then the disassembler uses the information to print out the
 821    instruction.  */
 822
 823 struct aarch64_inst
 824 {
 825   /* The value of the binary instruction.  */
 826   aarch64_insn value;
 827
 828   /* Corresponding opcode entry.  */
 829   const aarch64_opcode *opcode;
 830
 831   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 832   const aarch64_cond *cond;
 833
 834   /* Operands information.  */
 835   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 836 };
 837
 838 typedef struct aarch64_inst aarch64_inst;
 839 \f
 840 /* Diagnosis related declaration and interface.  */
 841
 842 /* Operand error kind enumerators.
 843
 844    AARCH64_OPDE_RECOVERABLE
 845      Less severe error found during the parsing, very possibly because that
 846      GAS has picked up a wrong instruction template for the parsing.
 847
 848    AARCH64_OPDE_SYNTAX_ERROR
 849      General syntax error; it can be either a user error, or simply because
 850      that GAS is trying a wrong instruction template.
 851
 852    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 853      Definitely a user syntax error.
 854
 855    AARCH64_OPDE_INVALID_VARIANT
 856      No syntax error, but the operands are not a valid combination, e.g.
 857      FMOV D0,S0
 858
 859    AARCH64_OPDE_OUT_OF_RANGE
 860      Error about some immediate value out of a valid range.
 861
 862    AARCH64_OPDE_UNALIGNED
 863      Error about some immediate value not properly aligned (i.e. not being a
 864      multiple times of a certain value).
 865
 866    AARCH64_OPDE_REG_LIST
 867      Error about the register list operand having unexpected number of
 868      registers.
 869
 870    AARCH64_OPDE_OTHER_ERROR
 871      Error of the highest severity and used for any severe issue that does not
 872      fall into any of the above categories.
 873
 874    The enumerators are only interesting to GAS.  They are declared here (in
 875    libopcodes) because that some errors are detected (and then notified to GAS)
 876    by libopcodes (rather than by GAS solely).
 877
 878    The first three errors are only deteced by GAS while the
 879    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 880    only libopcodes has the information about the valid variants of each
 881    instruction.
 882
 883    The enumerators have an increasing severity.  This is helpful when there are
 884    multiple instruction templates available for a given mnemonic name (e.g.
 885    FMOV); this mechanism will help choose the most suitable template from which
 886    the generated diagnostics can most closely describe the issues, if any.  */
 887
 888 enum aarch64_operand_error_kind
 889 {
 890   AARCH64_OPDE_NIL,
 891   AARCH64_OPDE_RECOVERABLE,
 892   AARCH64_OPDE_SYNTAX_ERROR,
 893   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 894   AARCH64_OPDE_INVALID_VARIANT,
 895   AARCH64_OPDE_OUT_OF_RANGE,
 896   AARCH64_OPDE_UNALIGNED,
 897   AARCH64_OPDE_REG_LIST,
 898   AARCH64_OPDE_OTHER_ERROR
 899 };
 900
 901 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 902 struct aarch64_operand_error
 903 {
 904   enum aarch64_operand_error_kind kind;
 905   int index;
 906   const char *error;
 907   int data[3];  /* Some data for extra information.  */
 908 };
 909
 910 typedef struct aarch64_operand_error aarch64_operand_error;
 911
 912 /* Encoding entrypoint.  */
 913
 914 extern int
 915 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 916                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 917                        aarch64_operand_error *);
 918
 919 extern const aarch64_opcode *
 920 aarch64_replace_opcode (struct aarch64_inst *,
 921                         const aarch64_opcode *);
 922
 923 /* Given the opcode enumerator OP, return the pointer to the corresponding
 924    opcode entry.  */
 925
 926 extern const aarch64_opcode *
 927 aarch64_get_opcode (enum aarch64_op);
 928
 929 /* Generate the string representation of an operand.  */
 930 extern void
 931 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 932                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 933
 934 /* Miscellaneous interface.  */
 935
 936 extern int
 937 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 938
 939 extern aarch64_opnd_qualifier_t
 940 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 941                                 const aarch64_opnd_qualifier_t, int);
 942
 943 extern int
 944 aarch64_num_of_operands (const aarch64_opcode *);
 945
 946 extern int
 947 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 948
 949 extern int
 950 aarch64_zero_register_p (const aarch64_opnd_info *);
 951
 952 extern int
 953 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
 954
 955 /* Given an operand qualifier, return the expected data element size
 956    of a qualified operand.  */
 957 extern unsigned char
 958 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 959
 960 extern enum aarch64_operand_class
 961 aarch64_get_operand_class (enum aarch64_opnd);
 962
 963 extern const char *
 964 aarch64_get_operand_name (enum aarch64_opnd);
 965
 966 extern const char *
 967 aarch64_get_operand_desc (enum aarch64_opnd);
 968
 969 #ifdef DEBUG_AARCH64
 970 extern int debug_dump;
 971
 972 extern void
 973 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 974
 975 #define DEBUG_TRACE(M, ...)                                     \
 976   {                                                             \
 977     if (debug_dump)                                             \
 978       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 979   }
 980
 981 #define DEBUG_TRACE_IF(C, M, ...)                               \
 982   {                                                             \
 983     if (debug_dump && (C))                                      \
 984       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 985   }
 986 #else  /* !DEBUG_AARCH64 */
 987 #define DEBUG_TRACE(M, ...) ;
 988 #define DEBUG_TRACE_IF(C, M, ...) ;
 989 #endif /* DEBUG_AARCH64 */
 990
 991 #ifdef __cplusplus
 992 }
 993 #endif
 994
 995 #endif /* OPCODE_AARCH64_H */