1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn
;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
42 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
43 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
44 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
45 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
46 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
47 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
48 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
49 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
51 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
52 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
53 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
54 #define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
56 /* Architectures are the sum of the base and extensions. */
57 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
59 | AARCH64_FEATURE_SIMD)
60 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
62 | AARCH64_FEATURE_SIMD \
63 | AARCH64_FEATURE_CRC \
64 | AARCH64_FEATURE_V8_1 \
65 | AARCH64_FEATURE_LSE \
66 | AARCH64_FEATURE_PAN \
67 | AARCH64_FEATURE_LOR \
68 | AARCH64_FEATURE_RDMA)
69 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
70 AARCH64_FEATURE_V8_2 \
71 | AARCH64_FEATURE_F16 \
72 | AARCH64_FEATURE_RAS \
73 | AARCH64_FEATURE_FP \
74 | AARCH64_FEATURE_SIMD \
75 | AARCH64_FEATURE_CRC \
76 | AARCH64_FEATURE_V8_1 \
77 | AARCH64_FEATURE_LSE \
78 | AARCH64_FEATURE_PAN \
79 | AARCH64_FEATURE_LOR \
80 | AARCH64_FEATURE_RDMA)
82 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
83 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
85 /* CPU-specific features. */
86 typedef unsigned long aarch64_feature_set
;
88 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
89 ((~(CPU) & (FEAT)) == 0)
91 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
92 (((CPU) & (FEAT)) != 0)
94 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
95 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
97 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
100 (TARG) = (F1) | (F2); \
104 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
107 (TARG) = (F1) &~ (F2); \
111 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
113 enum aarch64_operand_class
115 AARCH64_OPND_CLASS_NIL
,
116 AARCH64_OPND_CLASS_INT_REG
,
117 AARCH64_OPND_CLASS_MODIFIED_REG
,
118 AARCH64_OPND_CLASS_FP_REG
,
119 AARCH64_OPND_CLASS_SIMD_REG
,
120 AARCH64_OPND_CLASS_SIMD_ELEMENT
,
121 AARCH64_OPND_CLASS_SISD_REG
,
122 AARCH64_OPND_CLASS_SIMD_REGLIST
,
123 AARCH64_OPND_CLASS_CP_REG
,
124 AARCH64_OPND_CLASS_SVE_REG
,
125 AARCH64_OPND_CLASS_PRED_REG
,
126 AARCH64_OPND_CLASS_ADDRESS
,
127 AARCH64_OPND_CLASS_IMMEDIATE
,
128 AARCH64_OPND_CLASS_SYSTEM
,
129 AARCH64_OPND_CLASS_COND
,
132 /* Operand code that helps both parsing and coding.
133 Keep AARCH64_OPERANDS synced. */
137 AARCH64_OPND_NIL
, /* no operand---MUST BE FIRST!*/
139 AARCH64_OPND_Rd
, /* Integer register as destination. */
140 AARCH64_OPND_Rn
, /* Integer register as source. */
141 AARCH64_OPND_Rm
, /* Integer register as source. */
142 AARCH64_OPND_Rt
, /* Integer register used in ld/st instructions. */
143 AARCH64_OPND_Rt2
, /* Integer register used in ld/st pair instructions. */
144 AARCH64_OPND_Rs
, /* Integer register used in ld/st exclusive. */
145 AARCH64_OPND_Ra
, /* Integer register used in ddp_3src instructions. */
146 AARCH64_OPND_Rt_SYS
, /* Integer register used in system instructions. */
148 AARCH64_OPND_Rd_SP
, /* Integer Rd or SP. */
149 AARCH64_OPND_Rn_SP
, /* Integer Rn or SP. */
150 AARCH64_OPND_PAIRREG
, /* Paired register operand. */
151 AARCH64_OPND_Rm_EXT
, /* Integer Rm extended. */
152 AARCH64_OPND_Rm_SFT
, /* Integer Rm shifted. */
154 AARCH64_OPND_Fd
, /* Floating-point Fd. */
155 AARCH64_OPND_Fn
, /* Floating-point Fn. */
156 AARCH64_OPND_Fm
, /* Floating-point Fm. */
157 AARCH64_OPND_Fa
, /* Floating-point Fa. */
158 AARCH64_OPND_Ft
, /* Floating-point Ft. */
159 AARCH64_OPND_Ft2
, /* Floating-point Ft2. */
161 AARCH64_OPND_Sd
, /* AdvSIMD Scalar Sd. */
162 AARCH64_OPND_Sn
, /* AdvSIMD Scalar Sn. */
163 AARCH64_OPND_Sm
, /* AdvSIMD Scalar Sm. */
165 AARCH64_OPND_Vd
, /* AdvSIMD Vector Vd. */
166 AARCH64_OPND_Vn
, /* AdvSIMD Vector Vn. */
167 AARCH64_OPND_Vm
, /* AdvSIMD Vector Vm. */
168 AARCH64_OPND_VdD1
, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
169 AARCH64_OPND_VnD1
, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
170 AARCH64_OPND_Ed
, /* AdvSIMD Vector Element Vd. */
171 AARCH64_OPND_En
, /* AdvSIMD Vector Element Vn. */
172 AARCH64_OPND_Em
, /* AdvSIMD Vector Element Vm. */
173 AARCH64_OPND_LVn
, /* AdvSIMD Vector register list used in e.g. TBL. */
174 AARCH64_OPND_LVt
, /* AdvSIMD Vector register list used in ld/st. */
175 AARCH64_OPND_LVt_AL
, /* AdvSIMD Vector register list for loading single
176 structure to all lanes. */
177 AARCH64_OPND_LEt
, /* AdvSIMD Vector Element list. */
179 AARCH64_OPND_Cn
, /* Co-processor register in CRn field. */
180 AARCH64_OPND_Cm
, /* Co-processor register in CRm field. */
182 AARCH64_OPND_IDX
, /* AdvSIMD EXT index operand. */
183 AARCH64_OPND_IMM_VLSL
,/* Immediate for shifting vector registers left. */
184 AARCH64_OPND_IMM_VLSR
,/* Immediate for shifting vector registers right. */
185 AARCH64_OPND_SIMD_IMM
,/* AdvSIMD modified immediate without shift. */
186 AARCH64_OPND_SIMD_IMM_SFT
, /* AdvSIMD modified immediate with shift. */
187 AARCH64_OPND_SIMD_FPIMM
,/* AdvSIMD 8-bit fp immediate. */
188 AARCH64_OPND_SHLL_IMM
,/* Immediate shift for AdvSIMD SHLL instruction
190 AARCH64_OPND_IMM0
, /* Immediate for #0. */
191 AARCH64_OPND_FPIMM0
, /* Immediate for #0.0. */
192 AARCH64_OPND_FPIMM
, /* Floating-point Immediate. */
193 AARCH64_OPND_IMMR
, /* Immediate #<immr> in e.g. BFM. */
194 AARCH64_OPND_IMMS
, /* Immediate #<imms> in e.g. BFM. */
195 AARCH64_OPND_WIDTH
, /* Immediate #<width> in e.g. BFI. */
196 AARCH64_OPND_IMM
, /* Immediate. */
197 AARCH64_OPND_UIMM3_OP1
,/* Unsigned 3-bit immediate in the op1 field. */
198 AARCH64_OPND_UIMM3_OP2
,/* Unsigned 3-bit immediate in the op2 field. */
199 AARCH64_OPND_UIMM4
, /* Unsigned 4-bit immediate in the CRm field. */
200 AARCH64_OPND_UIMM7
, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
201 AARCH64_OPND_BIT_NUM
, /* Immediate. */
202 AARCH64_OPND_EXCEPTION
,/* imm16 operand in exception instructions. */
203 AARCH64_OPND_CCMP_IMM
,/* Immediate in conditional compare instructions. */
204 AARCH64_OPND_SIMM5
, /* 5-bit signed immediate in the imm5 field. */
205 AARCH64_OPND_NZCV
, /* Flag bit specifier giving an alternative value for
206 each condition flag. */
208 AARCH64_OPND_LIMM
, /* Logical Immediate. */
209 AARCH64_OPND_AIMM
, /* Arithmetic immediate. */
210 AARCH64_OPND_HALF
, /* #<imm16>{, LSL #<shift>} operand in move wide. */
211 AARCH64_OPND_FBITS
, /* FP #<fbits> operand in e.g. SCVTF */
212 AARCH64_OPND_IMM_MOV
, /* Immediate operand for the MOV alias. */
214 AARCH64_OPND_COND
, /* Standard condition as the last operand. */
215 AARCH64_OPND_COND1
, /* Same as the above, but excluding AL and NV. */
217 AARCH64_OPND_ADDR_ADRP
, /* Memory address for ADRP */
218 AARCH64_OPND_ADDR_PCREL14
, /* 14-bit PC-relative address for e.g. TBZ. */
219 AARCH64_OPND_ADDR_PCREL19
, /* 19-bit PC-relative address for e.g. LDR. */
220 AARCH64_OPND_ADDR_PCREL21
, /* 21-bit PC-relative address for e.g. ADR. */
221 AARCH64_OPND_ADDR_PCREL26
, /* 26-bit PC-relative address for e.g. BL. */
223 AARCH64_OPND_ADDR_SIMPLE
, /* Address of ld/st exclusive. */
224 AARCH64_OPND_ADDR_REGOFF
, /* Address of register offset. */
225 AARCH64_OPND_ADDR_SIMM7
, /* Address of signed 7-bit immediate. */
226 AARCH64_OPND_ADDR_SIMM9
, /* Address of signed 9-bit immediate. */
227 AARCH64_OPND_ADDR_SIMM9_2
, /* Same as the above, but the immediate is
228 negative or unaligned and there is
229 no writeback allowed. This operand code
230 is only used to support the programmer-
231 friendly feature of using LDR/STR as the
232 the mnemonic name for LDUR/STUR instructions
233 wherever there is no ambiguity. */
234 AARCH64_OPND_ADDR_UIMM12
, /* Address of unsigned 12-bit immediate. */
235 AARCH64_OPND_SIMD_ADDR_SIMPLE
,/* Address of ld/st multiple structures. */
236 AARCH64_OPND_SIMD_ADDR_POST
, /* Address of ld/st multiple post-indexed. */
238 AARCH64_OPND_SYSREG
, /* System register operand. */
239 AARCH64_OPND_PSTATEFIELD
, /* PSTATE field name operand. */
240 AARCH64_OPND_SYSREG_AT
, /* System register <at_op> operand. */
241 AARCH64_OPND_SYSREG_DC
, /* System register <dc_op> operand. */
242 AARCH64_OPND_SYSREG_IC
, /* System register <ic_op> operand. */
243 AARCH64_OPND_SYSREG_TLBI
, /* System register <tlbi_op> operand. */
244 AARCH64_OPND_BARRIER
, /* Barrier operand. */
245 AARCH64_OPND_BARRIER_ISB
, /* Barrier operand for ISB. */
246 AARCH64_OPND_PRFOP
, /* Prefetch operation. */
247 AARCH64_OPND_BARRIER_PSB
, /* Barrier operand for PSB. */
249 AARCH64_OPND_SVE_ADDR_RI_S4xVL
, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
250 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
251 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
252 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
253 AARCH64_OPND_SVE_ADDR_RI_S6xVL
, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
254 AARCH64_OPND_SVE_ADDR_RI_S9xVL
, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
255 AARCH64_OPND_SVE_ADDR_RI_U6
, /* SVE [<Xn|SP>, #<uimm6>]. */
256 AARCH64_OPND_SVE_ADDR_RI_U6x2
, /* SVE [<Xn|SP>, #<uimm6>*2]. */
257 AARCH64_OPND_SVE_ADDR_RI_U6x4
, /* SVE [<Xn|SP>, #<uimm6>*4]. */
258 AARCH64_OPND_SVE_ADDR_RI_U6x8
, /* SVE [<Xn|SP>, #<uimm6>*8]. */
259 AARCH64_OPND_SVE_ADDR_RR
, /* SVE [<Xn|SP>, <Xm|XZR>]. */
260 AARCH64_OPND_SVE_ADDR_RR_LSL1
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
261 AARCH64_OPND_SVE_ADDR_RR_LSL2
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
262 AARCH64_OPND_SVE_ADDR_RR_LSL3
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
263 AARCH64_OPND_SVE_ADDR_RX
, /* SVE [<Xn|SP>, <Xm>]. */
264 AARCH64_OPND_SVE_ADDR_RX_LSL1
, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
265 AARCH64_OPND_SVE_ADDR_RX_LSL2
, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
266 AARCH64_OPND_SVE_ADDR_RX_LSL3
, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
267 AARCH64_OPND_SVE_ADDR_RZ
, /* SVE [<Xn|SP>, Zm.D]. */
268 AARCH64_OPND_SVE_ADDR_RZ_LSL1
, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
269 AARCH64_OPND_SVE_ADDR_RZ_LSL2
, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
270 AARCH64_OPND_SVE_ADDR_RZ_LSL3
, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
271 AARCH64_OPND_SVE_ADDR_RZ_XTW_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
272 Bit 14 controls S/U choice. */
273 AARCH64_OPND_SVE_ADDR_RZ_XTW_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
274 Bit 22 controls S/U choice. */
275 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
276 Bit 14 controls S/U choice. */
277 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
278 Bit 22 controls S/U choice. */
279 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
280 Bit 14 controls S/U choice. */
281 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
282 Bit 22 controls S/U choice. */
283 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
284 Bit 14 controls S/U choice. */
285 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
286 Bit 22 controls S/U choice. */
287 AARCH64_OPND_SVE_ADDR_ZI_U5
, /* SVE [Zn.<T>, #<uimm5>]. */
288 AARCH64_OPND_SVE_ADDR_ZI_U5x2
, /* SVE [Zn.<T>, #<uimm5>*2]. */
289 AARCH64_OPND_SVE_ADDR_ZI_U5x4
, /* SVE [Zn.<T>, #<uimm5>*4]. */
290 AARCH64_OPND_SVE_ADDR_ZI_U5x8
, /* SVE [Zn.<T>, #<uimm5>*8]. */
291 AARCH64_OPND_SVE_ADDR_ZZ_LSL
, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
292 AARCH64_OPND_SVE_ADDR_ZZ_SXTW
, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
293 AARCH64_OPND_SVE_ADDR_ZZ_UXTW
, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
294 AARCH64_OPND_SVE_AIMM
, /* SVE unsigned arithmetic immediate. */
295 AARCH64_OPND_SVE_ASIMM
, /* SVE signed arithmetic immediate. */
296 AARCH64_OPND_SVE_FPIMM8
, /* SVE 8-bit floating-point immediate. */
297 AARCH64_OPND_SVE_I1_HALF_ONE
, /* SVE choice between 0.5 and 1.0. */
298 AARCH64_OPND_SVE_I1_HALF_TWO
, /* SVE choice between 0.5 and 2.0. */
299 AARCH64_OPND_SVE_I1_ZERO_ONE
, /* SVE choice between 0.0 and 1.0. */
300 AARCH64_OPND_SVE_INV_LIMM
, /* SVE inverted logical immediate. */
301 AARCH64_OPND_SVE_LIMM
, /* SVE logical immediate. */
302 AARCH64_OPND_SVE_LIMM_MOV
, /* SVE logical immediate for MOV. */
303 AARCH64_OPND_SVE_PATTERN
, /* SVE vector pattern enumeration. */
304 AARCH64_OPND_SVE_PATTERN_SCALED
, /* Likewise, with additional MUL factor. */
305 AARCH64_OPND_SVE_PRFOP
, /* SVE prefetch operation. */
306 AARCH64_OPND_SVE_Pd
, /* SVE p0-p15 in Pd. */
307 AARCH64_OPND_SVE_Pg3
, /* SVE p0-p7 in Pg. */
308 AARCH64_OPND_SVE_Pg4_5
, /* SVE p0-p15 in Pg, bits [8,5]. */
309 AARCH64_OPND_SVE_Pg4_10
, /* SVE p0-p15 in Pg, bits [13,10]. */
310 AARCH64_OPND_SVE_Pg4_16
, /* SVE p0-p15 in Pg, bits [19,16]. */
311 AARCH64_OPND_SVE_Pm
, /* SVE p0-p15 in Pm. */
312 AARCH64_OPND_SVE_Pn
, /* SVE p0-p15 in Pn. */
313 AARCH64_OPND_SVE_Pt
, /* SVE p0-p15 in Pt. */
314 AARCH64_OPND_SVE_Rm
, /* Integer Rm or ZR, alt. SVE position. */
315 AARCH64_OPND_SVE_Rn_SP
, /* Integer Rn or SP, alt. SVE position. */
316 AARCH64_OPND_SVE_SHLIMM_PRED
, /* SVE shift left amount (predicated). */
317 AARCH64_OPND_SVE_SHLIMM_UNPRED
, /* SVE shift left amount (unpredicated). */
318 AARCH64_OPND_SVE_SHRIMM_PRED
, /* SVE shift right amount (predicated). */
319 AARCH64_OPND_SVE_SHRIMM_UNPRED
, /* SVE shift right amount (unpredicated). */
320 AARCH64_OPND_SVE_SIMM5
, /* SVE signed 5-bit immediate. */
321 AARCH64_OPND_SVE_SIMM5B
, /* SVE secondary signed 5-bit immediate. */
322 AARCH64_OPND_SVE_SIMM6
, /* SVE signed 6-bit immediate. */
323 AARCH64_OPND_SVE_SIMM8
, /* SVE signed 8-bit immediate. */
324 AARCH64_OPND_SVE_UIMM3
, /* SVE unsigned 3-bit immediate. */
325 AARCH64_OPND_SVE_UIMM7
, /* SVE unsigned 7-bit immediate. */
326 AARCH64_OPND_SVE_UIMM8
, /* SVE unsigned 8-bit immediate. */
327 AARCH64_OPND_SVE_UIMM8_53
, /* SVE split unsigned 8-bit immediate. */
328 AARCH64_OPND_SVE_VZn
, /* Scalar SIMD&FP register in Zn field. */
329 AARCH64_OPND_SVE_Vd
, /* Scalar SIMD&FP register in Vd. */
330 AARCH64_OPND_SVE_Vm
, /* Scalar SIMD&FP register in Vm. */
331 AARCH64_OPND_SVE_Vn
, /* Scalar SIMD&FP register in Vn. */
332 AARCH64_OPND_SVE_Za_5
, /* SVE vector register in Za, bits [9,5]. */
333 AARCH64_OPND_SVE_Za_16
, /* SVE vector register in Za, bits [20,16]. */
334 AARCH64_OPND_SVE_Zd
, /* SVE vector register in Zd. */
335 AARCH64_OPND_SVE_Zm_5
, /* SVE vector register in Zm, bits [9,5]. */
336 AARCH64_OPND_SVE_Zm_16
, /* SVE vector register in Zm, bits [20,16]. */
337 AARCH64_OPND_SVE_Zn
, /* SVE vector register in Zn. */
338 AARCH64_OPND_SVE_Zn_INDEX
, /* Indexed SVE vector register, for DUP. */
339 AARCH64_OPND_SVE_ZnxN
, /* SVE vector register list in Zn. */
340 AARCH64_OPND_SVE_Zt
, /* SVE vector register in Zt. */
341 AARCH64_OPND_SVE_ZtxN
, /* SVE vector register list in Zt. */
344 /* Qualifier constrains an operand. It either specifies a variant of an
345 operand type or limits values available to an operand type.
347 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
349 enum aarch64_opnd_qualifier
351 /* Indicating no further qualification on an operand. */
352 AARCH64_OPND_QLF_NIL
,
354 /* Qualifying an operand which is a general purpose (integer) register;
355 indicating the operand data size or a specific register. */
356 AARCH64_OPND_QLF_W
, /* Wn, WZR or WSP. */
357 AARCH64_OPND_QLF_X
, /* Xn, XZR or XSP. */
358 AARCH64_OPND_QLF_WSP
, /* WSP. */
359 AARCH64_OPND_QLF_SP
, /* SP. */
361 /* Qualifying an operand which is a floating-point register, a SIMD
362 vector element or a SIMD vector element list; indicating operand data
363 size or the size of each SIMD vector element in the case of a SIMD
365 These qualifiers are also used to qualify an address operand to
366 indicate the size of data element a load/store instruction is
368 They are also used for the immediate shift operand in e.g. SSHR. Such
369 a use is only for the ease of operand encoding/decoding and qualifier
370 sequence matching; such a use should not be applied widely; use the value
371 constraint qualifiers for immediate operands wherever possible. */
372 AARCH64_OPND_QLF_S_B
,
373 AARCH64_OPND_QLF_S_H
,
374 AARCH64_OPND_QLF_S_S
,
375 AARCH64_OPND_QLF_S_D
,
376 AARCH64_OPND_QLF_S_Q
,
378 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
379 register list; indicating register shape.
380 They are also used for the immediate shift operand in e.g. SSHR. Such
381 a use is only for the ease of operand encoding/decoding and qualifier
382 sequence matching; such a use should not be applied widely; use the value
383 constraint qualifiers for immediate operands wherever possible. */
384 AARCH64_OPND_QLF_V_8B
,
385 AARCH64_OPND_QLF_V_16B
,
386 AARCH64_OPND_QLF_V_2H
,
387 AARCH64_OPND_QLF_V_4H
,
388 AARCH64_OPND_QLF_V_8H
,
389 AARCH64_OPND_QLF_V_2S
,
390 AARCH64_OPND_QLF_V_4S
,
391 AARCH64_OPND_QLF_V_1D
,
392 AARCH64_OPND_QLF_V_2D
,
393 AARCH64_OPND_QLF_V_1Q
,
395 AARCH64_OPND_QLF_P_Z
,
396 AARCH64_OPND_QLF_P_M
,
398 /* Constraint on value. */
399 AARCH64_OPND_QLF_imm_0_7
,
400 AARCH64_OPND_QLF_imm_0_15
,
401 AARCH64_OPND_QLF_imm_0_31
,
402 AARCH64_OPND_QLF_imm_0_63
,
403 AARCH64_OPND_QLF_imm_1_32
,
404 AARCH64_OPND_QLF_imm_1_64
,
406 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
408 AARCH64_OPND_QLF_LSL
,
409 AARCH64_OPND_QLF_MSL
,
411 /* Special qualifier helping retrieve qualifier information during the
412 decoding time (currently not in use). */
413 AARCH64_OPND_QLF_RETRIEVE
,
416 /* Instruction class. */
418 enum aarch64_insn_class
473 ldst_imm9
, /* immpost or immpre */
504 /* Opcode enumerators. */
548 OP_MOV_IMM_LOG
, /* MOV alias for moving bitmask immediate. */
549 OP_MOV_IMM_WIDE
, /* MOV alias for moving wide immediate. */
550 OP_MOV_IMM_WIDEN
, /* MOV alias for moving wide immediate (negated). */
552 OP_MOV_V
, /* MOV alias for moving vector register. */
565 OP_BFC
, /* ARMv8.2. */
582 OP_FCVTXN_S
, /* Scalar version. */
603 OP_TOTAL_NUM
, /* Pseudo. */
606 /* Maximum number of operands an instruction can have. */
607 #define AARCH64_MAX_OPND_NUM 6
608 /* Maximum number of qualifier sequences an instruction can have. */
609 #define AARCH64_MAX_QLF_SEQ_NUM 10
610 /* Operand qualifier typedef; optimized for the size. */
611 typedef unsigned char aarch64_opnd_qualifier_t
;
612 /* Operand qualifier sequence typedef. */
613 typedef aarch64_opnd_qualifier_t \
614 aarch64_opnd_qualifier_seq_t
[AARCH64_MAX_OPND_NUM
];
616 /* FIXME: improve the efficiency. */
617 static inline bfd_boolean
618 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t
*qualifiers
)
621 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
622 if (qualifiers
[i
] != AARCH64_OPND_QLF_NIL
)
627 /* This structure holds information for a particular opcode. */
629 struct aarch64_opcode
631 /* The name of the mnemonic. */
634 /* The opcode itself. Those bits which will be filled in with
635 operands are zeroes. */
638 /* The opcode mask. This is used by the disassembler. This is a
639 mask containing ones indicating those bits which must match the
640 opcode field, and zeroes indicating those bits which need not
641 match (and are presumably filled in by operands). */
644 /* Instruction class. */
645 enum aarch64_insn_class iclass
;
647 /* Enumerator identifier. */
650 /* Which architecture variant provides this instruction. */
651 const aarch64_feature_set
*avariant
;
653 /* An array of operand codes. Each code is an index into the
654 operand table. They appear in the order which the operands must
655 appear in assembly code, and are terminated by a zero. */
656 enum aarch64_opnd operands
[AARCH64_MAX_OPND_NUM
];
658 /* A list of operand qualifier code sequence. Each operand qualifier
659 code qualifies the corresponding operand code. Each operand
660 qualifier sequence specifies a valid opcode variant and related
661 constraint on operands. */
662 aarch64_opnd_qualifier_seq_t qualifiers_list
[AARCH64_MAX_QLF_SEQ_NUM
];
664 /* Flags providing information about this instruction */
667 /* If nonzero, this operand and operand 0 are both registers and
668 are required to have the same register number. */
669 unsigned char tied_operand
;
671 /* If non-NULL, a function to verify that a given instruction is valid. */
672 bfd_boolean (* verifier
) (const struct aarch64_opcode
*, const aarch64_insn
);
675 typedef struct aarch64_opcode aarch64_opcode
;
677 /* Table describing all the AArch64 opcodes. */
678 extern aarch64_opcode aarch64_opcode_table
[];
681 #define F_ALIAS (1 << 0)
682 #define F_HAS_ALIAS (1 << 1)
683 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
684 is specified, it is the priority 0 by default, i.e. the lowest priority. */
685 #define F_P1 (1 << 2)
686 #define F_P2 (2 << 2)
687 #define F_P3 (3 << 2)
688 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
689 #define F_COND (1 << 4)
690 /* Instruction has the field of 'sf'. */
691 #define F_SF (1 << 5)
692 /* Instruction has the field of 'size:Q'. */
693 #define F_SIZEQ (1 << 6)
694 /* Floating-point instruction has the field of 'type'. */
695 #define F_FPTYPE (1 << 7)
696 /* AdvSIMD scalar instruction has the field of 'size'. */
697 #define F_SSIZE (1 << 8)
698 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
700 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
701 #define F_GPRSIZE_IN_Q (1 << 10)
702 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
703 #define F_LDS_SIZE (1 << 11)
704 /* Optional operand; assume maximum of 1 operand can be optional. */
705 #define F_OPD0_OPT (1 << 12)
706 #define F_OPD1_OPT (2 << 12)
707 #define F_OPD2_OPT (3 << 12)
708 #define F_OPD3_OPT (4 << 12)
709 #define F_OPD4_OPT (5 << 12)
710 /* Default value for the optional operand when omitted from the assembly. */
711 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
712 /* Instruction that is an alias of another instruction needs to be
713 encoded/decoded by converting it to/from the real form, followed by
714 the encoding/decoding according to the rules of the real opcode.
715 This compares to the direct coding using the alias's information.
716 N.B. this flag requires F_ALIAS to be used together. */
717 #define F_CONV (1 << 20)
718 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
719 friendly pseudo instruction available only in the assembly code (thus will
720 not show up in the disassembly). */
721 #define F_PSEUDO (1 << 21)
722 /* Instruction has miscellaneous encoding/decoding rules. */
723 #define F_MISC (1 << 22)
724 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
725 #define F_N (1 << 23)
726 /* Opcode dependent field. */
727 #define F_OD(X) (((X) & 0x7) << 24)
728 /* Instruction has the field of 'sz'. */
729 #define F_LSE_SZ (1 << 27)
730 /* Require an exact qualifier match, even for NIL qualifiers. */
731 #define F_STRICT (1ULL << 28)
732 /* Next bit is 29. */
734 static inline bfd_boolean
735 alias_opcode_p (const aarch64_opcode
*opcode
)
737 return (opcode
->flags
& F_ALIAS
) ? TRUE
: FALSE
;
740 static inline bfd_boolean
741 opcode_has_alias (const aarch64_opcode
*opcode
)
743 return (opcode
->flags
& F_HAS_ALIAS
) ? TRUE
: FALSE
;
746 /* Priority for disassembling preference. */
748 opcode_priority (const aarch64_opcode
*opcode
)
750 return (opcode
->flags
>> 2) & 0x3;
753 static inline bfd_boolean
754 pseudo_opcode_p (const aarch64_opcode
*opcode
)
756 return (opcode
->flags
& F_PSEUDO
) != 0lu ? TRUE
: FALSE
;
759 static inline bfd_boolean
760 optional_operand_p (const aarch64_opcode
*opcode
, unsigned int idx
)
762 return (((opcode
->flags
>> 12) & 0x7) == idx
+ 1)
766 static inline aarch64_insn
767 get_optional_operand_default_value (const aarch64_opcode
*opcode
)
769 return (opcode
->flags
>> 15) & 0x1f;
772 static inline unsigned int
773 get_opcode_dependent_value (const aarch64_opcode
*opcode
)
775 return (opcode
->flags
>> 24) & 0x7;
778 static inline bfd_boolean
779 opcode_has_special_coder (const aarch64_opcode
*opcode
)
781 return (opcode
->flags
& (F_SF
| F_LSE_SZ
| F_SIZEQ
| F_FPTYPE
| F_SSIZE
| F_T
782 | F_GPRSIZE_IN_Q
| F_LDS_SIZE
| F_MISC
| F_N
| F_COND
)) ? TRUE
786 struct aarch64_name_value_pair
792 extern const struct aarch64_name_value_pair aarch64_operand_modifiers
[];
793 extern const struct aarch64_name_value_pair aarch64_barrier_options
[16];
794 extern const struct aarch64_name_value_pair aarch64_prfops
[32];
795 extern const struct aarch64_name_value_pair aarch64_hint_options
[];
804 extern const aarch64_sys_reg aarch64_sys_regs
[];
805 extern const aarch64_sys_reg aarch64_pstatefields
[];
806 extern bfd_boolean
aarch64_sys_reg_deprecated_p (const aarch64_sys_reg
*);
807 extern bfd_boolean
aarch64_sys_reg_supported_p (const aarch64_feature_set
,
808 const aarch64_sys_reg
*);
809 extern bfd_boolean
aarch64_pstatefield_supported_p (const aarch64_feature_set
,
810 const aarch64_sys_reg
*);
817 } aarch64_sys_ins_reg
;
819 extern bfd_boolean
aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg
*);
821 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set
,
822 const aarch64_sys_ins_reg
*);
824 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic
[];
825 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc
[];
826 extern const aarch64_sys_ins_reg aarch64_sys_regs_at
[];
827 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi
[];
829 /* Shift/extending operator kinds.
830 N.B. order is important; keep aarch64_operand_modifiers synced. */
831 enum aarch64_modifier_kind
852 aarch64_extend_operator_p (enum aarch64_modifier_kind
);
854 enum aarch64_modifier_kind
855 aarch64_get_operand_modifier (const struct aarch64_name_value_pair
*);
860 /* A list of names with the first one as the disassembly preference;
861 terminated by NULL if fewer than 3. */
862 const char *names
[4];
866 extern const aarch64_cond aarch64_conds
[16];
868 const aarch64_cond
* get_cond_from_value (aarch64_insn value
);
869 const aarch64_cond
* get_inverted_cond (const aarch64_cond
*cond
);
871 /* Structure representing an operand. */
873 struct aarch64_opnd_info
875 enum aarch64_opnd type
;
876 aarch64_opnd_qualifier_t qualifier
;
893 unsigned first_regno
: 5;
894 unsigned num_regs
: 3;
895 /* 1 if it is a list of reg element. */
896 unsigned has_index
: 1;
897 /* Lane index; valid only when has_index is 1. */
900 /* e.g. immediate or pc relative address offset. */
906 /* e.g. address in STR (register offset). */
919 unsigned pcrel
: 1; /* PC-relative. */
920 unsigned writeback
: 1;
921 unsigned preind
: 1; /* Pre-indexed. */
922 unsigned postind
: 1; /* Post-indexed. */
924 const aarch64_cond
*cond
;
925 /* The encoding of the system register. */
927 /* The encoding of the PSTATE field. */
928 aarch64_insn pstatefield
;
929 const aarch64_sys_ins_reg
*sysins_op
;
930 const struct aarch64_name_value_pair
*barrier
;
931 const struct aarch64_name_value_pair
*hint_option
;
932 const struct aarch64_name_value_pair
*prfop
;
935 /* Operand shifter; in use when the operand is a register offset address,
936 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
939 enum aarch64_modifier_kind kind
;
940 unsigned operator_present
: 1; /* Only valid during encoding. */
941 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
942 unsigned amount_present
: 1;
946 unsigned skip
:1; /* Operand is not completed if there is a fixup needed
947 to be done on it. In some (but not all) of these
948 cases, we need to tell libopcodes to skip the
949 constraint checking and the encoding for this
950 operand, so that the libopcodes can pick up the
951 right opcode before the operand is fixed-up. This
952 flag should only be used during the
953 assembling/encoding. */
954 unsigned present
:1; /* Whether this operand is present in the assembly
955 line; not used during the disassembly. */
958 typedef struct aarch64_opnd_info aarch64_opnd_info
;
960 /* Structure representing an instruction.
962 It is used during both the assembling and disassembling. The assembler
963 fills an aarch64_inst after a successful parsing and then passes it to the
964 encoding routine to do the encoding. During the disassembling, the
965 disassembler calls the decoding routine to decode a binary instruction; on a
966 successful return, such a structure will be filled with information of the
967 instruction; then the disassembler uses the information to print out the
972 /* The value of the binary instruction. */
975 /* Corresponding opcode entry. */
976 const aarch64_opcode
*opcode
;
978 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
979 const aarch64_cond
*cond
;
981 /* Operands information. */
982 aarch64_opnd_info operands
[AARCH64_MAX_OPND_NUM
];
985 typedef struct aarch64_inst aarch64_inst
;
987 /* Diagnosis related declaration and interface. */
989 /* Operand error kind enumerators.
991 AARCH64_OPDE_RECOVERABLE
992 Less severe error found during the parsing, very possibly because that
993 GAS has picked up a wrong instruction template for the parsing.
995 AARCH64_OPDE_SYNTAX_ERROR
996 General syntax error; it can be either a user error, or simply because
997 that GAS is trying a wrong instruction template.
999 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1000 Definitely a user syntax error.
1002 AARCH64_OPDE_INVALID_VARIANT
1003 No syntax error, but the operands are not a valid combination, e.g.
1006 AARCH64_OPDE_UNTIED_OPERAND
1007 The asm failed to use the same register for a destination operand
1008 and a tied source operand.
1010 AARCH64_OPDE_OUT_OF_RANGE
1011 Error about some immediate value out of a valid range.
1013 AARCH64_OPDE_UNALIGNED
1014 Error about some immediate value not properly aligned (i.e. not being a
1015 multiple times of a certain value).
1017 AARCH64_OPDE_REG_LIST
1018 Error about the register list operand having unexpected number of
1021 AARCH64_OPDE_OTHER_ERROR
1022 Error of the highest severity and used for any severe issue that does not
1023 fall into any of the above categories.
1025 The enumerators are only interesting to GAS. They are declared here (in
1026 libopcodes) because that some errors are detected (and then notified to GAS)
1027 by libopcodes (rather than by GAS solely).
1029 The first three errors are only deteced by GAS while the
1030 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1031 only libopcodes has the information about the valid variants of each
1034 The enumerators have an increasing severity. This is helpful when there are
1035 multiple instruction templates available for a given mnemonic name (e.g.
1036 FMOV); this mechanism will help choose the most suitable template from which
1037 the generated diagnostics can most closely describe the issues, if any. */
1039 enum aarch64_operand_error_kind
1042 AARCH64_OPDE_RECOVERABLE
,
1043 AARCH64_OPDE_SYNTAX_ERROR
,
1044 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
1045 AARCH64_OPDE_INVALID_VARIANT
,
1046 AARCH64_OPDE_UNTIED_OPERAND
,
1047 AARCH64_OPDE_OUT_OF_RANGE
,
1048 AARCH64_OPDE_UNALIGNED
,
1049 AARCH64_OPDE_REG_LIST
,
1050 AARCH64_OPDE_OTHER_ERROR
1053 /* N.B. GAS assumes that this structure work well with shallow copy. */
1054 struct aarch64_operand_error
1056 enum aarch64_operand_error_kind kind
;
1059 int data
[3]; /* Some data for extra information. */
1062 typedef struct aarch64_operand_error aarch64_operand_error
;
1064 /* Encoding entrypoint. */
1067 aarch64_opcode_encode (const aarch64_opcode
*, const aarch64_inst
*,
1068 aarch64_insn
*, aarch64_opnd_qualifier_t
*,
1069 aarch64_operand_error
*);
1071 extern const aarch64_opcode
*
1072 aarch64_replace_opcode (struct aarch64_inst
*,
1073 const aarch64_opcode
*);
1075 /* Given the opcode enumerator OP, return the pointer to the corresponding
1078 extern const aarch64_opcode
*
1079 aarch64_get_opcode (enum aarch64_op
);
1081 /* Generate the string representation of an operand. */
1083 aarch64_print_operand (char *, size_t, bfd_vma
, const aarch64_opcode
*,
1084 const aarch64_opnd_info
*, int, int *, bfd_vma
*);
1086 /* Miscellaneous interface. */
1089 aarch64_operand_index (const enum aarch64_opnd
*, enum aarch64_opnd
);
1091 extern aarch64_opnd_qualifier_t
1092 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t
*, int,
1093 const aarch64_opnd_qualifier_t
, int);
1096 aarch64_num_of_operands (const aarch64_opcode
*);
1099 aarch64_stack_pointer_p (const aarch64_opnd_info
*);
1102 aarch64_zero_register_p (const aarch64_opnd_info
*);
1105 aarch64_decode_insn (aarch64_insn
, aarch64_inst
*, bfd_boolean
);
1107 /* Given an operand qualifier, return the expected data element size
1108 of a qualified operand. */
1109 extern unsigned char
1110 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t
);
1112 extern enum aarch64_operand_class
1113 aarch64_get_operand_class (enum aarch64_opnd
);
1116 aarch64_get_operand_name (enum aarch64_opnd
);
1119 aarch64_get_operand_desc (enum aarch64_opnd
);
1122 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1124 #ifdef DEBUG_AARCH64
1125 extern int debug_dump
;
1128 aarch64_verbose (const char *, ...) __attribute__ ((format (printf
, 1, 2)));
1130 #define DEBUG_TRACE(M, ...) \
1133 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1136 #define DEBUG_TRACE_IF(C, M, ...) \
1138 if (debug_dump && (C)) \
1139 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1141 #else /* !DEBUG_AARCH64 */
1142 #define DEBUG_TRACE(M, ...) ;
1143 #define DEBUG_TRACE_IF(C, M, ...) ;
1144 #endif /* DEBUG_AARCH64 */
1146 extern const char *const aarch64_sve_pattern_array
[32];
1147 extern const char *const aarch64_sve_prfop_array
[16];
1153 #endif /* OPCODE_AARCH64_H */