include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 /* The offset for pc-relative addressing is currently defined to be 0.  */
  31 #define AARCH64_PCREL_OFFSET            0
  32
  33 typedef uint32_t aarch64_insn;
  34
  35 /* The following bitmasks control CPU features.  */
  36 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  37 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  38 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  39 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  40 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  41 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  42 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  43 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  44 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  45
  46 /* Architectures are the sum of the base and extensions.  */
  47 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  48                                                  AARCH64_FEATURE_FP  \
  49                                                  | AARCH64_FEATURE_SIMD)
  50 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  51 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  52
  53 /* CPU-specific features.  */
  54 typedef unsigned long aarch64_feature_set;
  55
  56 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  57   (((CPU) & (FEAT)) != 0)
  58
  59 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  60   do                                            \
  61     {                                           \
  62       (TARG) = (F1) | (F2);                     \
  63     }                                           \
  64   while (0)
  65
  66 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  67   do                                            \
  68     {                                           \
  69       (TARG) = (F1) &~ (F2);                    \
  70     }                                           \
  71   while (0)
  72
  73 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
  74
  75 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
  76   (((OPC) & (FEAT)) != 0)
  77
  78 enum aarch64_operand_class
  79 {
  80   AARCH64_OPND_CLASS_NIL,
  81   AARCH64_OPND_CLASS_INT_REG,
  82   AARCH64_OPND_CLASS_MODIFIED_REG,
  83   AARCH64_OPND_CLASS_FP_REG,
  84   AARCH64_OPND_CLASS_SIMD_REG,
  85   AARCH64_OPND_CLASS_SIMD_ELEMENT,
  86   AARCH64_OPND_CLASS_SISD_REG,
  87   AARCH64_OPND_CLASS_SIMD_REGLIST,
  88   AARCH64_OPND_CLASS_CP_REG,
  89   AARCH64_OPND_CLASS_ADDRESS,
  90   AARCH64_OPND_CLASS_IMMEDIATE,
  91   AARCH64_OPND_CLASS_SYSTEM,
  92   AARCH64_OPND_CLASS_COND,
  93 };
  94
  95 /* Operand code that helps both parsing and coding.
  96    Keep AARCH64_OPERANDS synced.  */
  97
  98 enum aarch64_opnd
  99 {
 100   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 101
 102   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 103   AARCH64_OPND_Rn,      /* Integer register as source.  */
 104   AARCH64_OPND_Rm,      /* Integer register as source.  */
 105   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 106   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 107   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 108   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 109   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 110
 111   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 112   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 113   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 114   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 115   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 116
 117   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 118   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 119   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 120   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 121   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 122   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 123
 124   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 125   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 126   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 127
 128   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 129   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 130   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 131   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 132   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 133   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 134   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 135   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 136   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 137   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 138   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 139                            structure to all lanes.  */
 140   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 141
 142   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 143   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 144
 145   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 146   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 147   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 148   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 149   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 150   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 151   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 152                            (no encoding).  */
 153   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 154   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 155   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 156   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 157   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 158   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 159   AARCH64_OPND_IMM,     /* Immediate.  */
 160   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 161   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 162   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 163   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 164   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 165   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 166   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 167   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 168                            each condition flag.  */
 169
 170   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 171   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 172   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 173   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 174   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 175
 176   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 177   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 178
 179   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 180   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 181   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 182   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 183   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 184
 185   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 186   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 187   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 188   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 189   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 190                                    negative or unaligned and there is
 191                                    no writeback allowed.  This operand code
 192                                    is only used to support the programmer-
 193                                    friendly feature of using LDR/STR as the
 194                                    the mnemonic name for LDUR/STUR instructions
 195                                    wherever there is no ambiguity.  */
 196   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 197   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 198   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 199
 200   AARCH64_OPND_SYSREG,          /* System register operand.  */
 201   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 202   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 203   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 204   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 205   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 206   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 207   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 208   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 209 };
 210
 211 /* Qualifier constrains an operand.  It either specifies a variant of an
 212    operand type or limits values available to an operand type.
 213
 214    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 215
 216 enum aarch64_opnd_qualifier
 217 {
 218   /* Indicating no further qualification on an operand.  */
 219   AARCH64_OPND_QLF_NIL,
 220
 221   /* Qualifying an operand which is a general purpose (integer) register;
 222      indicating the operand data size or a specific register.  */
 223   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 224   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 225   AARCH64_OPND_QLF_WSP, /* WSP.  */
 226   AARCH64_OPND_QLF_SP,  /* SP.  */
 227
 228   /* Qualifying an operand which is a floating-point register, a SIMD
 229      vector element or a SIMD vector element list; indicating operand data
 230      size or the size of each SIMD vector element in the case of a SIMD
 231      vector element list.
 232      These qualifiers are also used to qualify an address operand to
 233      indicate the size of data element a load/store instruction is
 234      accessing.
 235      They are also used for the immediate shift operand in e.g. SSHR.  Such
 236      a use is only for the ease of operand encoding/decoding and qualifier
 237      sequence matching; such a use should not be applied widely; use the value
 238      constraint qualifiers for immediate operands wherever possible.  */
 239   AARCH64_OPND_QLF_S_B,
 240   AARCH64_OPND_QLF_S_H,
 241   AARCH64_OPND_QLF_S_S,
 242   AARCH64_OPND_QLF_S_D,
 243   AARCH64_OPND_QLF_S_Q,
 244
 245   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 246      register list; indicating register shape.
 247      They are also used for the immediate shift operand in e.g. SSHR.  Such
 248      a use is only for the ease of operand encoding/decoding and qualifier
 249      sequence matching; such a use should not be applied widely; use the value
 250      constraint qualifiers for immediate operands wherever possible.  */
 251   AARCH64_OPND_QLF_V_8B,
 252   AARCH64_OPND_QLF_V_16B,
 253   AARCH64_OPND_QLF_V_4H,
 254   AARCH64_OPND_QLF_V_8H,
 255   AARCH64_OPND_QLF_V_2S,
 256   AARCH64_OPND_QLF_V_4S,
 257   AARCH64_OPND_QLF_V_1D,
 258   AARCH64_OPND_QLF_V_2D,
 259   AARCH64_OPND_QLF_V_1Q,
 260
 261   /* Constraint on value.  */
 262   AARCH64_OPND_QLF_imm_0_7,
 263   AARCH64_OPND_QLF_imm_0_15,
 264   AARCH64_OPND_QLF_imm_0_31,
 265   AARCH64_OPND_QLF_imm_0_63,
 266   AARCH64_OPND_QLF_imm_1_32,
 267   AARCH64_OPND_QLF_imm_1_64,
 268
 269   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 270      or shift-ones.  */
 271   AARCH64_OPND_QLF_LSL,
 272   AARCH64_OPND_QLF_MSL,
 273
 274   /* Special qualifier helping retrieve qualifier information during the
 275      decoding time (currently not in use).  */
 276   AARCH64_OPND_QLF_RETRIEVE,
 277 };
 278 \f
 279 /* Instruction class.  */
 280
 281 enum aarch64_insn_class
 282 {
 283   addsub_carry,
 284   addsub_ext,
 285   addsub_imm,
 286   addsub_shift,
 287   asimdall,
 288   asimddiff,
 289   asimdelem,
 290   asimdext,
 291   asimdimm,
 292   asimdins,
 293   asimdmisc,
 294   asimdperm,
 295   asimdsame,
 296   asimdshf,
 297   asimdtbl,
 298   asisddiff,
 299   asisdelem,
 300   asisdlse,
 301   asisdlsep,
 302   asisdlso,
 303   asisdlsop,
 304   asisdmisc,
 305   asisdone,
 306   asisdpair,
 307   asisdsame,
 308   asisdshf,
 309   bitfield,
 310   branch_imm,
 311   branch_reg,
 312   compbranch,
 313   condbranch,
 314   condcmp_imm,
 315   condcmp_reg,
 316   condsel,
 317   cryptoaes,
 318   cryptosha2,
 319   cryptosha3,
 320   dp_1src,
 321   dp_2src,
 322   dp_3src,
 323   exception,
 324   extract,
 325   float2fix,
 326   float2int,
 327   floatccmp,
 328   floatcmp,
 329   floatdp1,
 330   floatdp2,
 331   floatdp3,
 332   floatimm,
 333   floatsel,
 334   ldst_immpost,
 335   ldst_immpre,
 336   ldst_imm9,    /* immpost or immpre */
 337   ldst_pos,
 338   ldst_regoff,
 339   ldst_unpriv,
 340   ldst_unscaled,
 341   ldstexcl,
 342   ldstnapair_offs,
 343   ldstpair_off,
 344   ldstpair_indexed,
 345   loadlit,
 346   log_imm,
 347   log_shift,
 348   lse_atomic,
 349   movewide,
 350   pcreladdr,
 351   ic_system,
 352   testbranch,
 353 };
 354
 355 /* Opcode enumerators.  */
 356
 357 enum aarch64_op
 358 {
 359   OP_NIL,
 360   OP_STRB_POS,
 361   OP_LDRB_POS,
 362   OP_LDRSB_POS,
 363   OP_STRH_POS,
 364   OP_LDRH_POS,
 365   OP_LDRSH_POS,
 366   OP_STR_POS,
 367   OP_LDR_POS,
 368   OP_STRF_POS,
 369   OP_LDRF_POS,
 370   OP_LDRSW_POS,
 371   OP_PRFM_POS,
 372
 373   OP_STURB,
 374   OP_LDURB,
 375   OP_LDURSB,
 376   OP_STURH,
 377   OP_LDURH,
 378   OP_LDURSH,
 379   OP_STUR,
 380   OP_LDUR,
 381   OP_STURV,
 382   OP_LDURV,
 383   OP_LDURSW,
 384   OP_PRFUM,
 385
 386   OP_LDR_LIT,
 387   OP_LDRV_LIT,
 388   OP_LDRSW_LIT,
 389   OP_PRFM_LIT,
 390
 391   OP_ADD,
 392   OP_B,
 393   OP_BL,
 394
 395   OP_MOVN,
 396   OP_MOVZ,
 397   OP_MOVK,
 398
 399   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 400   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 401   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 402
 403   OP_MOV_V,             /* MOV alias for moving vector register.  */
 404
 405   OP_ASR_IMM,
 406   OP_LSR_IMM,
 407   OP_LSL_IMM,
 408
 409   OP_BIC,
 410
 411   OP_UBFX,
 412   OP_BFXIL,
 413   OP_SBFX,
 414   OP_SBFIZ,
 415   OP_BFI,
 416   OP_UBFIZ,
 417   OP_UXTB,
 418   OP_UXTH,
 419   OP_UXTW,
 420
 421   OP_CINC,
 422   OP_CINV,
 423   OP_CNEG,
 424   OP_CSET,
 425   OP_CSETM,
 426
 427   OP_FCVT,
 428   OP_FCVTN,
 429   OP_FCVTN2,
 430   OP_FCVTL,
 431   OP_FCVTL2,
 432   OP_FCVTXN_S,          /* Scalar version.  */
 433
 434   OP_ROR_IMM,
 435
 436   OP_SXTL,
 437   OP_SXTL2,
 438   OP_UXTL,
 439   OP_UXTL2,
 440
 441   OP_TOTAL_NUM,         /* Pseudo.  */
 442 };
 443
 444 /* Maximum number of operands an instruction can have.  */
 445 #define AARCH64_MAX_OPND_NUM 6
 446 /* Maximum number of qualifier sequences an instruction can have.  */
 447 #define AARCH64_MAX_QLF_SEQ_NUM 10
 448 /* Operand qualifier typedef; optimized for the size.  */
 449 typedef unsigned char aarch64_opnd_qualifier_t;
 450 /* Operand qualifier sequence typedef.  */
 451 typedef aarch64_opnd_qualifier_t        \
 452           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 453
 454 /* FIXME: improve the efficiency.  */
 455 static inline bfd_boolean
 456 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 457 {
 458   int i;
 459   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 460     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 461       return FALSE;
 462   return TRUE;
 463 }
 464
 465 /* This structure holds information for a particular opcode.  */
 466
 467 struct aarch64_opcode
 468 {
 469   /* The name of the mnemonic.  */
 470   const char *name;
 471
 472   /* The opcode itself.  Those bits which will be filled in with
 473      operands are zeroes.  */
 474   aarch64_insn opcode;
 475
 476   /* The opcode mask.  This is used by the disassembler.  This is a
 477      mask containing ones indicating those bits which must match the
 478      opcode field, and zeroes indicating those bits which need not
 479      match (and are presumably filled in by operands).  */
 480   aarch64_insn mask;
 481
 482   /* Instruction class.  */
 483   enum aarch64_insn_class iclass;
 484
 485   /* Enumerator identifier.  */
 486   enum aarch64_op op;
 487
 488   /* Which architecture variant provides this instruction.  */
 489   const aarch64_feature_set *avariant;
 490
 491   /* An array of operand codes.  Each code is an index into the
 492      operand table.  They appear in the order which the operands must
 493      appear in assembly code, and are terminated by a zero.  */
 494   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 495
 496   /* A list of operand qualifier code sequence.  Each operand qualifier
 497      code qualifies the corresponding operand code.  Each operand
 498      qualifier sequence specifies a valid opcode variant and related
 499      constraint on operands.  */
 500   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 501
 502   /* Flags providing information about this instruction */
 503   uint32_t flags;
 504 };
 505
 506 typedef struct aarch64_opcode aarch64_opcode;
 507
 508 /* Table describing all the AArch64 opcodes.  */
 509 extern aarch64_opcode aarch64_opcode_table[];
 510
 511 /* Opcode flags.  */
 512 #define F_ALIAS (1 << 0)
 513 #define F_HAS_ALIAS (1 << 1)
 514 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 515    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 516 #define F_P1 (1 << 2)
 517 #define F_P2 (2 << 2)
 518 #define F_P3 (3 << 2)
 519 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 520 #define F_COND (1 << 4)
 521 /* Instruction has the field of 'sf'.  */
 522 #define F_SF (1 << 5)
 523 /* Instruction has the field of 'size:Q'.  */
 524 #define F_SIZEQ (1 << 6)
 525 /* Floating-point instruction has the field of 'type'.  */
 526 #define F_FPTYPE (1 << 7)
 527 /* AdvSIMD scalar instruction has the field of 'size'.  */
 528 #define F_SSIZE (1 << 8)
 529 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 530 #define F_T (1 << 9)
 531 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 532 #define F_GPRSIZE_IN_Q (1 << 10)
 533 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 534 #define F_LDS_SIZE (1 << 11)
 535 /* Optional operand; assume maximum of 1 operand can be optional.  */
 536 #define F_OPD0_OPT (1 << 12)
 537 #define F_OPD1_OPT (2 << 12)
 538 #define F_OPD2_OPT (3 << 12)
 539 #define F_OPD3_OPT (4 << 12)
 540 #define F_OPD4_OPT (5 << 12)
 541 /* Default value for the optional operand when omitted from the assembly.  */
 542 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 543 /* Instruction that is an alias of another instruction needs to be
 544    encoded/decoded by converting it to/from the real form, followed by
 545    the encoding/decoding according to the rules of the real opcode.
 546    This compares to the direct coding using the alias's information.
 547    N.B. this flag requires F_ALIAS to be used together.  */
 548 #define F_CONV (1 << 20)
 549 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 550    friendly pseudo instruction available only in the assembly code (thus will
 551    not show up in the disassembly).  */
 552 #define F_PSEUDO (1 << 21)
 553 /* Instruction has miscellaneous encoding/decoding rules.  */
 554 #define F_MISC (1 << 22)
 555 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 556 #define F_N (1 << 23)
 557 /* Opcode dependent field.  */
 558 #define F_OD(X) (((X) & 0x7) << 24)
 559 /* Instruction has the field of 'sz'.  */
 560 #define F_LSE_SZ (1 << 27)
 561 /* Next bit is 28.  */
 562
 563 static inline bfd_boolean
 564 alias_opcode_p (const aarch64_opcode *opcode)
 565 {
 566   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 567 }
 568
 569 static inline bfd_boolean
 570 opcode_has_alias (const aarch64_opcode *opcode)
 571 {
 572   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 573 }
 574
 575 /* Priority for disassembling preference.  */
 576 static inline int
 577 opcode_priority (const aarch64_opcode *opcode)
 578 {
 579   return (opcode->flags >> 2) & 0x3;
 580 }
 581
 582 static inline bfd_boolean
 583 pseudo_opcode_p (const aarch64_opcode *opcode)
 584 {
 585   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 586 }
 587
 588 static inline bfd_boolean
 589 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 590 {
 591   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 592     ? TRUE : FALSE;
 593 }
 594
 595 static inline aarch64_insn
 596 get_optional_operand_default_value (const aarch64_opcode *opcode)
 597 {
 598   return (opcode->flags >> 15) & 0x1f;
 599 }
 600
 601 static inline unsigned int
 602 get_opcode_dependent_value (const aarch64_opcode *opcode)
 603 {
 604   return (opcode->flags >> 24) & 0x7;
 605 }
 606
 607 static inline bfd_boolean
 608 opcode_has_special_coder (const aarch64_opcode *opcode)
 609 {
 610   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 611           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 612     : FALSE;
 613 }
 614 \f
 615 struct aarch64_name_value_pair
 616 {
 617   const char *  name;
 618   aarch64_insn  value;
 619 };
 620
 621 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 622 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 623 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 624
 625 typedef struct
 626 {
 627   const char *  name;
 628   aarch64_insn  value;
 629   uint32_t      flags;
 630 } aarch64_sys_reg;
 631
 632 extern const aarch64_sys_reg aarch64_sys_regs [];
 633 extern const aarch64_sys_reg aarch64_pstatefields [];
 634 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 635 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 636                                                 const aarch64_sys_reg *);
 637 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 638                                                     const aarch64_sys_reg *);
 639
 640 typedef struct
 641 {
 642   const char *template;
 643   uint32_t value;
 644   int has_xt;
 645 } aarch64_sys_ins_reg;
 646
 647 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 648 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 649 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 650 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 651
 652 /* Shift/extending operator kinds.
 653    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 654 enum aarch64_modifier_kind
 655 {
 656   AARCH64_MOD_NONE,
 657   AARCH64_MOD_MSL,
 658   AARCH64_MOD_ROR,
 659   AARCH64_MOD_ASR,
 660   AARCH64_MOD_LSR,
 661   AARCH64_MOD_LSL,
 662   AARCH64_MOD_UXTB,
 663   AARCH64_MOD_UXTH,
 664   AARCH64_MOD_UXTW,
 665   AARCH64_MOD_UXTX,
 666   AARCH64_MOD_SXTB,
 667   AARCH64_MOD_SXTH,
 668   AARCH64_MOD_SXTW,
 669   AARCH64_MOD_SXTX,
 670 };
 671
 672 bfd_boolean
 673 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 674
 675 enum aarch64_modifier_kind
 676 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 677 /* Condition.  */
 678
 679 typedef struct
 680 {
 681   /* A list of names with the first one as the disassembly preference;
 682      terminated by NULL if fewer than 3.  */
 683   const char *names[3];
 684   aarch64_insn value;
 685 } aarch64_cond;
 686
 687 extern const aarch64_cond aarch64_conds[16];
 688
 689 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 690 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 691 \f
 692 /* Structure representing an operand.  */
 693
 694 struct aarch64_opnd_info
 695 {
 696   enum aarch64_opnd type;
 697   aarch64_opnd_qualifier_t qualifier;
 698   int idx;
 699
 700   union
 701     {
 702       struct
 703         {
 704           unsigned regno;
 705         } reg;
 706       struct
 707         {
 708           unsigned regno : 5;
 709           unsigned index : 4;
 710         } reglane;
 711       /* e.g. LVn.  */
 712       struct
 713         {
 714           unsigned first_regno : 5;
 715           unsigned num_regs : 3;
 716           /* 1 if it is a list of reg element.  */
 717           unsigned has_index : 1;
 718           /* Lane index; valid only when has_index is 1.  */
 719           unsigned index : 4;
 720         } reglist;
 721       /* e.g. immediate or pc relative address offset.  */
 722       struct
 723         {
 724           int64_t value;
 725           unsigned is_fp : 1;
 726         } imm;
 727       /* e.g. address in STR (register offset).  */
 728       struct
 729         {
 730           unsigned base_regno;
 731           struct
 732             {
 733               union
 734                 {
 735                   int imm;
 736                   unsigned regno;
 737                 };
 738               unsigned is_reg;
 739             } offset;
 740           unsigned pcrel : 1;           /* PC-relative.  */
 741           unsigned writeback : 1;
 742           unsigned preind : 1;          /* Pre-indexed.  */
 743           unsigned postind : 1;         /* Post-indexed.  */
 744         } addr;
 745       const aarch64_cond *cond;
 746       /* The encoding of the system register.  */
 747       aarch64_insn sysreg;
 748       /* The encoding of the PSTATE field.  */
 749       aarch64_insn pstatefield;
 750       const aarch64_sys_ins_reg *sysins_op;
 751       const struct aarch64_name_value_pair *barrier;
 752       const struct aarch64_name_value_pair *prfop;
 753     };
 754
 755   /* Operand shifter; in use when the operand is a register offset address,
 756      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 757   struct
 758     {
 759       enum aarch64_modifier_kind kind;
 760       int amount;
 761       unsigned operator_present: 1;     /* Only valid during encoding.  */
 762       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 763       unsigned amount_present: 1;
 764     } shifter;
 765
 766   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 767                            to be done on it.  In some (but not all) of these
 768                            cases, we need to tell libopcodes to skip the
 769                            constraint checking and the encoding for this
 770                            operand, so that the libopcodes can pick up the
 771                            right opcode before the operand is fixed-up.  This
 772                            flag should only be used during the
 773                            assembling/encoding.  */
 774   unsigned present:1;   /* Whether this operand is present in the assembly
 775                            line; not used during the disassembly.  */
 776 };
 777
 778 typedef struct aarch64_opnd_info aarch64_opnd_info;
 779
 780 /* Structure representing an instruction.
 781
 782    It is used during both the assembling and disassembling.  The assembler
 783    fills an aarch64_inst after a successful parsing and then passes it to the
 784    encoding routine to do the encoding.  During the disassembling, the
 785    disassembler calls the decoding routine to decode a binary instruction; on a
 786    successful return, such a structure will be filled with information of the
 787    instruction; then the disassembler uses the information to print out the
 788    instruction.  */
 789
 790 struct aarch64_inst
 791 {
 792   /* The value of the binary instruction.  */
 793   aarch64_insn value;
 794
 795   /* Corresponding opcode entry.  */
 796   const aarch64_opcode *opcode;
 797
 798   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 799   const aarch64_cond *cond;
 800
 801   /* Operands information.  */
 802   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 803 };
 804
 805 typedef struct aarch64_inst aarch64_inst;
 806 \f
 807 /* Diagnosis related declaration and interface.  */
 808
 809 /* Operand error kind enumerators.
 810
 811    AARCH64_OPDE_RECOVERABLE
 812      Less severe error found during the parsing, very possibly because that
 813      GAS has picked up a wrong instruction template for the parsing.
 814
 815    AARCH64_OPDE_SYNTAX_ERROR
 816      General syntax error; it can be either a user error, or simply because
 817      that GAS is trying a wrong instruction template.
 818
 819    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 820      Definitely a user syntax error.
 821
 822    AARCH64_OPDE_INVALID_VARIANT
 823      No syntax error, but the operands are not a valid combination, e.g.
 824      FMOV D0,S0
 825
 826    AARCH64_OPDE_OUT_OF_RANGE
 827      Error about some immediate value out of a valid range.
 828
 829    AARCH64_OPDE_UNALIGNED
 830      Error about some immediate value not properly aligned (i.e. not being a
 831      multiple times of a certain value).
 832
 833    AARCH64_OPDE_REG_LIST
 834      Error about the register list operand having unexpected number of
 835      registers.
 836
 837    AARCH64_OPDE_OTHER_ERROR
 838      Error of the highest severity and used for any severe issue that does not
 839      fall into any of the above categories.
 840
 841    The enumerators are only interesting to GAS.  They are declared here (in
 842    libopcodes) because that some errors are detected (and then notified to GAS)
 843    by libopcodes (rather than by GAS solely).
 844
 845    The first three errors are only deteced by GAS while the
 846    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 847    only libopcodes has the information about the valid variants of each
 848    instruction.
 849
 850    The enumerators have an increasing severity.  This is helpful when there are
 851    multiple instruction templates available for a given mnemonic name (e.g.
 852    FMOV); this mechanism will help choose the most suitable template from which
 853    the generated diagnostics can most closely describe the issues, if any.  */
 854
 855 enum aarch64_operand_error_kind
 856 {
 857   AARCH64_OPDE_NIL,
 858   AARCH64_OPDE_RECOVERABLE,
 859   AARCH64_OPDE_SYNTAX_ERROR,
 860   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 861   AARCH64_OPDE_INVALID_VARIANT,
 862   AARCH64_OPDE_OUT_OF_RANGE,
 863   AARCH64_OPDE_UNALIGNED,
 864   AARCH64_OPDE_REG_LIST,
 865   AARCH64_OPDE_OTHER_ERROR
 866 };
 867
 868 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 869 struct aarch64_operand_error
 870 {
 871   enum aarch64_operand_error_kind kind;
 872   int index;
 873   const char *error;
 874   int data[3];  /* Some data for extra information.  */
 875 };
 876
 877 typedef struct aarch64_operand_error aarch64_operand_error;
 878
 879 /* Encoding entrypoint.  */
 880
 881 extern int
 882 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 883                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 884                        aarch64_operand_error *);
 885
 886 extern const aarch64_opcode *
 887 aarch64_replace_opcode (struct aarch64_inst *,
 888                         const aarch64_opcode *);
 889
 890 /* Given the opcode enumerator OP, return the pointer to the corresponding
 891    opcode entry.  */
 892
 893 extern const aarch64_opcode *
 894 aarch64_get_opcode (enum aarch64_op);
 895
 896 /* Generate the string representation of an operand.  */
 897 extern void
 898 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 899                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 900
 901 /* Miscellaneous interface.  */
 902
 903 extern int
 904 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 905
 906 extern aarch64_opnd_qualifier_t
 907 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 908                                 const aarch64_opnd_qualifier_t, int);
 909
 910 extern int
 911 aarch64_num_of_operands (const aarch64_opcode *);
 912
 913 extern int
 914 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 915
 916 extern
 917 int aarch64_zero_register_p (const aarch64_opnd_info *);
 918
 919 /* Given an operand qualifier, return the expected data element size
 920    of a qualified operand.  */
 921 extern unsigned char
 922 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 923
 924 extern enum aarch64_operand_class
 925 aarch64_get_operand_class (enum aarch64_opnd);
 926
 927 extern const char *
 928 aarch64_get_operand_name (enum aarch64_opnd);
 929
 930 extern const char *
 931 aarch64_get_operand_desc (enum aarch64_opnd);
 932
 933 #ifdef DEBUG_AARCH64
 934 extern int debug_dump;
 935
 936 extern void
 937 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 938
 939 #define DEBUG_TRACE(M, ...)                                     \
 940   {                                                             \
 941     if (debug_dump)                                             \
 942       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 943   }
 944
 945 #define DEBUG_TRACE_IF(C, M, ...)                               \
 946   {                                                             \
 947     if (debug_dump && (C))                                      \
 948       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 949   }
 950 #else  /* !DEBUG_AARCH64 */
 951 #define DEBUG_TRACE(M, ...) ;
 952 #define DEBUG_TRACE_IF(C, M, ...) ;
 953 #endif /* DEBUG_AARCH64 */
 954
 955 #endif /* OPCODE_AARCH64_H */