1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS or GDB; see the file COPYING3. If not, write to
21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
32 #define MAX_INSN_ARGS 16
36 #define MAX_INSN_FLGS 3
39 /* Instruction Class. */
69 /* Instruction Subclass. */
101 /* At most one flag from the set of flags can appear in the
103 F_CLASS_OPTIONAL
= (1 << 0),
105 /* Exactly one from from the set of flags must appear in the
107 F_CLASS_REQUIRED
= (1 << 1),
109 /* The conditional code can be extended over the standard variants
110 via .extCondCode pseudo-op. */
111 F_CLASS_EXTEND
= (1 << 2),
113 /* Condition code flag. */
114 F_CLASS_COND
= (1 << 3)
117 /* The opcode table is an array of struct arc_opcode. */
120 /* The opcode name. */
123 /* The opcode itself. Those bits which will be filled in with
124 operands are zeroes. */
125 unsigned long long opcode
;
127 /* The opcode mask. This is used by the disassembler. This is a
128 mask containing ones indicating those bits which must match the
129 opcode field, and zeroes indicating those bits which need not
130 match (and are presumably filled in by operands). */
131 unsigned long long mask
;
133 /* One bit flags for the opcode. These are primarily used to
134 indicate specific processors and environments support the
135 instructions. The defined values are listed below. */
138 /* The instruction class. This is used by gdb. */
139 insn_class_t insn_class
;
141 /* The instruction subclass. */
142 insn_subclass_t subclass
;
144 /* An array of operand codes. Each code is an index into the
145 operand table. They appear in the order which the operands must
146 appear in assembly code, and are terminated by a zero. */
147 unsigned char operands
[MAX_INSN_ARGS
+ 1];
149 /* An array of flag codes. Each code is an index into the flag
150 table. They appear in the order which the flags must appear in
151 assembly code, and are terminated by a zero. */
152 unsigned char flags
[MAX_INSN_FLGS
+ 1];
155 /* The table itself is sorted by major opcode number, and is otherwise
156 in the order in which the disassembler should consider
158 extern const struct arc_opcode arc_opcodes
[];
160 /* Return length of an instruction represented by OPCODE, in bytes. */
161 extern int arc_opcode_len (const struct arc_opcode
*opcode
);
163 /* CPU Availability. */
164 #define ARC_OPCODE_NONE 0x0000
165 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
166 #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
167 #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
168 #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
171 #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
172 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
173 #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
174 #define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
176 /* CPU extensions. */
177 #define ARC_EA 0x0001
178 #define ARC_CD 0x0001 /* Mutual exclusive with EA. */
179 #define ARC_LLOCK 0x0002
180 #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
181 #define ARC_MPY 0x0004
182 #define ARC_MULT 0x0004
183 #define ARC_NPS400 0x0008
185 /* Floating point support. */
186 #define ARC_DPFP 0x0010
187 #define ARC_SPFP 0x0020
188 #define ARC_FPU 0x0030
189 #define ARC_FPUDA 0x0040
192 #define ARC_SWAP 0x0100
193 #define ARC_NORM 0x0200
194 #define ARC_BSCAN 0x0200
197 #define ARC_UIX 0x1000
198 #define ARC_TSTAMP 0x1000
201 #define ARC_VBFDW 0x1000
202 #define ARC_BARREL 0x1000
203 #define ARC_DSPA 0x1000
206 #define ARC_SHIFT 0x1000
209 #define ARC_INTR 0x1000
210 #define ARC_DIV 0x1000
213 #define ARC_XMAC 0x1000
214 #define ARC_CRC 0x1000
216 /* The operands table is an array of struct arc_operand. */
219 /* The number of bits in the operand. */
222 /* How far the operand is left shifted in the instruction. */
225 /* The default relocation type for this operand. */
226 signed int default_reloc
;
228 /* One bit syntax flags. */
231 /* Insertion function. This is used by the assembler. To insert an
232 operand value into an instruction, check this field.
234 If it is NULL, execute
235 i |= (op & ((1 << o->bits) - 1)) << o->shift;
236 (i is the instruction which we are filling in, o is a pointer to
237 this structure, and op is the opcode value; this assumes twos
238 complement arithmetic).
240 If this field is not NULL, then simply call it with the
241 instruction and the operand value. It will return the new value
242 of the instruction. If the ERRMSG argument is not NULL, then if
243 the operand value is illegal, *ERRMSG will be set to a warning
244 string (the operand will be inserted in any case). If the
245 operand value is legal, *ERRMSG will be unchanged (most operands
246 can accept any value). */
247 unsigned long long (*insert
) (unsigned long long instruction
,
249 const char **errmsg
);
251 /* Extraction function. This is used by the disassembler. To
252 extract this operand type from an instruction, check this field.
254 If it is NULL, compute
255 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
256 if ((o->flags & ARC_OPERAND_SIGNED) != 0
257 && (op & (1 << (o->bits - 1))) != 0)
259 (i is the instruction, o is a pointer to this structure, and op
260 is the result; this assumes twos complement arithmetic).
262 If this field is not NULL, then simply call it with the
263 instruction value. It will return the value of the operand. If
264 the INVALID argument is not NULL, *INVALID will be set to
265 TRUE if this operand type can not actually be extracted from
266 this operand (i.e., the instruction does not match). If the
267 operand is valid, *INVALID will not be changed. */
268 long long int (*extract
) (unsigned long long instruction
,
269 bfd_boolean
*invalid
);
272 /* Elements in the table are retrieved by indexing with values from
273 the operands field of the arc_opcodes table. */
274 extern const struct arc_operand arc_operands
[];
275 extern const unsigned arc_num_operands
;
276 extern const unsigned arc_Toperand
;
277 extern const unsigned arc_NToperand
;
279 /* Values defined for the flags field of a struct arc_operand. */
281 /* This operand does not actually exist in the assembler input. This
282 is used to support extended mnemonics, for which two operands fields
283 are identical. The assembler should call the insert function with
284 any op value. The disassembler should call the extract function,
285 ignore the return value, and check the value placed in the invalid
287 #define ARC_OPERAND_FAKE 0x0001
289 /* This operand names an integer register. */
290 #define ARC_OPERAND_IR 0x0002
292 /* This operand takes signed values. */
293 #define ARC_OPERAND_SIGNED 0x0004
295 /* This operand takes unsigned values. This exists primarily so that
296 a flags value of 0 can be treated as end-of-arguments. */
297 #define ARC_OPERAND_UNSIGNED 0x0008
299 /* This operand takes long immediate values. */
300 #define ARC_OPERAND_LIMM 0x0010
302 /* This operand is identical like the previous one. */
303 #define ARC_OPERAND_DUPLICATE 0x0020
305 /* This operand is PC relative. Used for internal relocs. */
306 #define ARC_OPERAND_PCREL 0x0040
308 /* This operand is truncated. The truncation is done accordingly to
309 operand alignment attribute. */
310 #define ARC_OPERAND_TRUNCATE 0x0080
312 /* This operand is 16bit aligned. */
313 #define ARC_OPERAND_ALIGNED16 0x0100
315 /* This operand is 32bit aligned. */
316 #define ARC_OPERAND_ALIGNED32 0x0200
318 /* This operand can be ignored by matching process if it is not
320 #define ARC_OPERAND_IGNORE 0x0400
322 /* Don't check the range when matching. */
323 #define ARC_OPERAND_NCHK 0x0800
325 /* Mark the braket possition. */
326 #define ARC_OPERAND_BRAKET 0x1000
328 /* Address type operand for NPS400. */
329 #define ARC_OPERAND_ADDRTYPE 0x2000
331 /* Mark the colon position. */
332 #define ARC_OPERAND_COLON 0x4000
334 /* Mask for selecting the type for typecheck purposes. */
335 #define ARC_OPERAND_TYPECHECK_MASK \
337 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
338 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
339 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
341 /* Macro to determine if an operand is a fake operand. */
342 #define ARC_OPERAND_IS_FAKE(op) \
343 ((operand->flags & ARC_OPERAND_FAKE) \
344 && !((operand->flags & ARC_OPERAND_BRAKET) \
345 || (operand->flags & ARC_OPERAND_COLON)))
347 /* The flags structure. */
348 struct arc_flag_operand
356 /* The number of bits in the operand. */
359 /* How far the operand is left shifted in the instruction. */
362 /* Available for disassembler. */
363 unsigned char favail
;
366 /* The flag operands table. */
367 extern const struct arc_flag_operand arc_flag_operands
[];
368 extern const unsigned arc_num_flag_operands
;
370 /* The flag's class structure. */
371 struct arc_flag_class
374 flag_class_t flag_class
;
376 /* List of valid flags (codes). */
380 extern const struct arc_flag_class arc_flag_classes
[];
382 /* Structure for special cases. */
383 struct arc_flag_special
385 /* Name of special case instruction. */
388 /* List of flags applicable for special case instruction. */
392 extern const struct arc_flag_special arc_flag_special_cases
[];
393 extern const unsigned arc_num_flag_special
;
395 /* Relocation equivalence structure. */
396 struct arc_reloc_equiv_tab
398 const char * name
; /* String to lookup. */
399 const char * mnemonic
; /* Extra matching condition. */
400 unsigned flags
[32]; /* Extra matching condition. */
401 signed int oldreloc
; /* Old relocation. */
402 signed int newreloc
; /* New relocation. */
405 extern const struct arc_reloc_equiv_tab arc_reloc_equiv
[];
406 extern const unsigned arc_num_equiv_tab
;
408 /* Structure for operand operations for pseudo/alias instructions. */
409 struct arc_operand_operation
411 /* The index for operand from operand array. */
412 unsigned operand_idx
;
414 /* Defines if it needs the operand inserted by the assembler or
415 whether this operand comes from the pseudo instruction's
417 unsigned char needs_insert
;
419 /* Count we have to add to the operand. Use negative number to
420 subtract from the operand. Also use this number to add to 0 if
421 the operand needs to be inserted (i.e. needs_insert == 1). */
424 /* Index of the operand to swap with. To be done AFTER applying
426 unsigned swap_operand_idx
;
429 /* Structure for pseudo/alias instructions. */
430 struct arc_pseudo_insn
432 /* Mnemonic for pseudo/alias insn. */
433 const char *mnemonic_p
;
435 /* Mnemonic for real instruction. */
436 const char *mnemonic_r
;
438 /* Flag that will have to be added (if any). */
441 /* Amount of operands. */
442 unsigned operand_cnt
;
444 /* Array of operand operations. */
445 struct arc_operand_operation operand
[6];
448 extern const struct arc_pseudo_insn arc_pseudo_insns
[];
449 extern const unsigned arc_num_pseudo_insn
;
451 /* Structure for AUXILIARY registers. */
454 /* Register address. */
457 /* One bit flags for the opcode. These are primarily used to
458 indicate specific processors and environments support the
462 /* AUX register subclass. */
463 insn_subclass_t subclass
;
468 /* Size of the string. */
472 extern const struct arc_aux_reg arc_aux_regs
[];
473 extern const unsigned arc_num_aux_regs
;
475 extern const struct arc_opcode arc_relax_opcodes
[];
476 extern const unsigned arc_num_relax_opcodes
;
478 /* Macro used for generating one class of NPS instructions. */
479 #define NPS_CMEM_HIGH_VALUE 0x57f0
481 /* Macros to help generating regular pattern instructions. */
482 #define FIELDA(word) (word & 0x3F)
483 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
484 #define FIELDC(word) ((word & 0x3F) << 6)
485 #define FIELDF (0x01 << 15)
486 #define FIELDQ (0x1F)
488 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
489 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
490 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
492 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
493 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
494 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
495 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
496 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
497 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
498 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
499 #define INSN3OP_0LL(MOP,SOP) \
500 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
501 #define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
502 #define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
503 #define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
504 #define INSN3OP_0LU(MOP,SOP) \
505 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
506 #define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
507 #define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
508 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
509 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
510 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
511 #define INSN3OP_C0LL(MOP,SOP) \
512 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
513 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
514 #define INSN3OP_C0LU(MOP,SOP) \
515 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
517 #define MASK_32BIT(VAL) (0xffffffff & (VAL))
519 #define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
520 #define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
521 #define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
522 #define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
523 #define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
524 #define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
525 #define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
526 #define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
527 #define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
528 #define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
529 #define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
530 #define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
531 #define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
532 #define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
533 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
534 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
535 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
536 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
537 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
538 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
540 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
541 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
542 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
543 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
544 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
545 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
547 #define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
548 #define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
549 #define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
550 #define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
551 #define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
552 #define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
554 /* Various constants used when defining an extension instruction. */
555 #define ARC_SYNTAX_3OP (1 << 0)
556 #define ARC_SYNTAX_2OP (1 << 1)
557 #define ARC_SYNTAX_1OP (1 << 2)
558 #define ARC_SYNTAX_NOP (1 << 3)
559 #define ARC_SYNTAX_MASK (0x0F)
561 #define ARC_OP1_MUST_BE_IMM (1 << 0)
562 #define ARC_OP1_IMM_IMPLIED (1 << 1)
564 #define ARC_SUFFIX_NONE (1 << 0)
565 #define ARC_SUFFIX_COND (1 << 1)
566 #define ARC_SUFFIX_FLAG (1 << 2)
568 #define ARC_REGISTER_READONLY (1 << 0)
569 #define ARC_REGISTER_WRITEONLY (1 << 1)
570 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
572 /* Constants needed to initialize extension instructions. */
573 extern const unsigned char flags_none
[MAX_INSN_FLGS
+ 1];
574 extern const unsigned char flags_f
[MAX_INSN_FLGS
+ 1];
575 extern const unsigned char flags_cc
[MAX_INSN_FLGS
+ 1];
576 extern const unsigned char flags_ccf
[MAX_INSN_FLGS
+ 1];
578 extern const unsigned char arg_none
[MAX_INSN_ARGS
+ 1];
579 extern const unsigned char arg_32bit_rarbrc
[MAX_INSN_ARGS
+ 1];
580 extern const unsigned char arg_32bit_zarbrc
[MAX_INSN_ARGS
+ 1];
581 extern const unsigned char arg_32bit_rbrbrc
[MAX_INSN_ARGS
+ 1];
582 extern const unsigned char arg_32bit_rarbu6
[MAX_INSN_ARGS
+ 1];
583 extern const unsigned char arg_32bit_zarbu6
[MAX_INSN_ARGS
+ 1];
584 extern const unsigned char arg_32bit_rbrbu6
[MAX_INSN_ARGS
+ 1];
585 extern const unsigned char arg_32bit_rbrbs12
[MAX_INSN_ARGS
+ 1];
586 extern const unsigned char arg_32bit_ralimmrc
[MAX_INSN_ARGS
+ 1];
587 extern const unsigned char arg_32bit_rarblimm
[MAX_INSN_ARGS
+ 1];
588 extern const unsigned char arg_32bit_zalimmrc
[MAX_INSN_ARGS
+ 1];
589 extern const unsigned char arg_32bit_zarblimm
[MAX_INSN_ARGS
+ 1];
591 extern const unsigned char arg_32bit_rbrblimm
[MAX_INSN_ARGS
+ 1];
592 extern const unsigned char arg_32bit_ralimmu6
[MAX_INSN_ARGS
+ 1];
593 extern const unsigned char arg_32bit_zalimmu6
[MAX_INSN_ARGS
+ 1];
595 extern const unsigned char arg_32bit_zalimms12
[MAX_INSN_ARGS
+ 1];
596 extern const unsigned char arg_32bit_ralimmlimm
[MAX_INSN_ARGS
+ 1];
597 extern const unsigned char arg_32bit_zalimmlimm
[MAX_INSN_ARGS
+ 1];
599 extern const unsigned char arg_32bit_rbrc
[MAX_INSN_ARGS
+ 1];
600 extern const unsigned char arg_32bit_zarc
[MAX_INSN_ARGS
+ 1];
601 extern const unsigned char arg_32bit_rbu6
[MAX_INSN_ARGS
+ 1];
602 extern const unsigned char arg_32bit_zau6
[MAX_INSN_ARGS
+ 1];
603 extern const unsigned char arg_32bit_rblimm
[MAX_INSN_ARGS
+ 1];
604 extern const unsigned char arg_32bit_zalimm
[MAX_INSN_ARGS
+ 1];
606 extern const unsigned char arg_32bit_limmrc
[MAX_INSN_ARGS
+ 1];
607 extern const unsigned char arg_32bit_limmu6
[MAX_INSN_ARGS
+ 1];
608 extern const unsigned char arg_32bit_limms12
[MAX_INSN_ARGS
+ 1];
609 extern const unsigned char arg_32bit_limmlimm
[MAX_INSN_ARGS
+ 1];
611 extern const unsigned char arg_32bit_rc
[MAX_INSN_ARGS
+ 1];
612 extern const unsigned char arg_32bit_u6
[MAX_INSN_ARGS
+ 1];
613 extern const unsigned char arg_32bit_limm
[MAX_INSN_ARGS
+ 1];
615 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
616 Instruction Set Reference Manual v2.4 for a description of address types. */
620 /* Addresses in memory. */
622 /* Buffer descriptor. */
623 ARC_NPS400_ADDRTYPE_BD
,
625 /* Job identifier. */
626 ARC_NPS400_ADDRTYPE_JID
,
628 /* Linked Buffer Descriptor. */
629 ARC_NPS400_ADDRTYPE_LBD
,
631 /* Multicast Buffer Descriptor. */
632 ARC_NPS400_ADDRTYPE_MBD
,
634 /* Summarized Address. */
635 ARC_NPS400_ADDRTYPE_SD
,
637 /* SMEM Security Context Local Memory. */
638 ARC_NPS400_ADDRTYPE_SM
,
640 /* Extended Address. */
641 ARC_NPS400_ADDRTYPE_XA
,
643 /* Extended Summarized Address. */
644 ARC_NPS400_ADDRTYPE_XD
,
646 /* CMEM offset addresses. */
648 /* On-demand Counter Descriptor. */
649 ARC_NPS400_ADDRTYPE_CD
,
651 /* CMEM Buffer Descriptor. */
652 ARC_NPS400_ADDRTYPE_CBD
,
654 /* CMEM Job Identifier. */
655 ARC_NPS400_ADDRTYPE_CJID
,
657 /* CMEM Linked Buffer Descriptor. */
658 ARC_NPS400_ADDRTYPE_CLBD
,
661 ARC_NPS400_ADDRTYPE_CM
,
663 /* CMEM Summarized Address. */
664 ARC_NPS400_ADDRTYPE_CSD
,
666 /* CMEM Extended Address. */
667 ARC_NPS400_ADDRTYPE_CXA
,
669 /* CMEM Extended Summarized Address. */
670 ARC_NPS400_ADDRTYPE_CXD
672 } arc_nps_address_type
;
674 #define ARC_NUM_ADDRTYPES 16
680 #endif /* OPCODE_ARC_H */