include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifndef MAX_INSN_ARGS
  28 #define MAX_INSN_ARGS        16
  29 #endif
  30
  31 #ifndef MAX_INSN_FLGS
  32 #define MAX_INSN_FLGS        3
  33 #endif
  34
  35 /* Instruction Class.  */
  36 typedef enum
  37   {
  38     ARITH,
  39     AUXREG,
  40     BRANCH,
  41     CONTROL,
  42     DSP,
  43     FLOAT,
  44     INVALID,
  45     JUMP,
  46     KERNEL,
  47     LOGICAL,
  48     MEMORY,
  49     BITOP,
  50     NET,
  51     ACL,
  52   } insn_class_t;
  53
  54 /* Instruction Subclass.  */
  55 typedef enum
  56   {
  57     NONE,
  58     CVT,
  59     BTSCN,
  60     CD1,
  61     CD2,
  62     COND,
  63     DIV,
  64     DP,
  65     DPA,
  66     DPX,
  67     MPY1E,
  68     MPY6E,
  69     MPY7E,
  70     MPY8E,
  71     MPY9E,
  72     QUARKSE,
  73     SHFT1,
  74     SHFT2,
  75     SWAP,
  76     SP,
  77     SPX
  78   } insn_subclass_t;
  79
  80 /* Flags class.  */
  81 typedef enum
  82   {
  83     F_CLASS_NONE = 0,
  84
  85     /* At most one flag from the set of flags can appear in the
  86        instruction.  */
  87     F_CLASS_OPTIONAL = (1 << 0),
  88
  89     /* Exactly one from from the set of flags must appear in the
  90        instruction.  */
  91     F_CLASS_REQUIRED = (1 << 1),
  92
  93     /* The conditional code can be extended over the standard variants
  94        via .extCondCode pseudo-op.  */
  95     F_CLASS_EXTEND = (1 << 2),
  96
  97     /* Condition code flag.  */
  98     F_CLASS_COND = (1 << 3)
  99   } flag_class_t;
 100
 101 /* The opcode table is an array of struct arc_opcode.  */
 102 struct arc_opcode
 103 {
 104   /* The opcode name.  */
 105   const char *name;
 106
 107   /* The opcode itself.  Those bits which will be filled in with
 108      operands are zeroes.  */
 109   unsigned opcode;
 110
 111   /* The opcode mask.  This is used by the disassembler.  This is a
 112      mask containing ones indicating those bits which must match the
 113      opcode field, and zeroes indicating those bits which need not
 114      match (and are presumably filled in by operands).  */
 115   unsigned mask;
 116
 117   /* One bit flags for the opcode.  These are primarily used to
 118      indicate specific processors and environments support the
 119      instructions.  The defined values are listed below.  */
 120   unsigned cpu;
 121
 122   /* The instruction class.  This is used by gdb.  */
 123   insn_class_t insn_class;
 124
 125   /* The instruction subclass.  */
 126   insn_subclass_t subclass;
 127
 128   /* An array of operand codes.  Each code is an index into the
 129      operand table.  They appear in the order which the operands must
 130      appear in assembly code, and are terminated by a zero.  */
 131   unsigned char operands[MAX_INSN_ARGS + 1];
 132
 133   /* An array of flag codes.  Each code is an index into the flag
 134      table.  They appear in the order which the flags must appear in
 135      assembly code, and are terminated by a zero.  */
 136   unsigned char flags[MAX_INSN_FLGS + 1];
 137 };
 138
 139 /* Structure used to describe 48 and 64 bit instructions.  */
 140 struct arc_long_opcode
 141 {
 142   /* The base instruction is either 16 or 32 bits, and is described like a
 143      normal instruction.  */
 144   struct arc_opcode base_opcode;
 145
 146   /* The template value for the 32-bit LIMM extension.  Used by the
 147      assembler and disassembler in the same way as the 'opcode' field of
 148      'struct arc_opcode'.  */
 149   unsigned limm_template;
 150
 151   /* The mask value for the 32-bit LIMM extension.  Used by the
 152      disassembler just like the 'mask' field in 'struct arc_opcode'.  */
 153   unsigned limm_mask;
 154
 155   /* Array of operand codes similar to the 'operands' array in 'struct
 156      arc_opcode'.  These operands are used to fill in the LIMM value.  */
 157   unsigned char operands[MAX_INSN_ARGS + 1];
 158 };
 159
 160 extern const struct arc_long_opcode arc_long_opcodes[];
 161 extern const unsigned arc_num_long_opcodes;
 162
 163 /* The table itself is sorted by major opcode number, and is otherwise
 164    in the order in which the disassembler should consider
 165    instructions.  */
 166 extern const struct arc_opcode arc_opcodes[];
 167
 168 /* CPU Availability.  */
 169 #define ARC_OPCODE_NONE     0x0000
 170 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 171 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 172 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 173 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 174 #define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */
 175
 176 /* CPU combi.  */
 177 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 178                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 179 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 180
 181 /* CPU extensions.  */
 182 #define ARC_EA       0x0001
 183 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 184 #define ARC_LLOCK    0x0002
 185 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 186 #define ARC_MPY      0x0004
 187 #define ARC_MULT     0x0004
 188
 189 /* Floating point support.  */
 190 #define ARC_DPFP     0x0010
 191 #define ARC_SPFP     0x0020
 192 #define ARC_FPU      0x0030
 193 #define ARC_FPUDA    0x0040
 194
 195 /* NORM & SWAP.  */
 196 #define ARC_SWAP     0x0100
 197 #define ARC_NORM     0x0200
 198 #define ARC_BSCAN    0x0200
 199
 200 /* A7 specific.  */
 201 #define ARC_UIX      0x1000
 202 #define ARC_TSTAMP   0x1000
 203
 204 /* A6 specific.  */
 205 #define ARC_VBFDW    0x1000
 206 #define ARC_BARREL   0x1000
 207 #define ARC_DSPA     0x1000
 208
 209 /* EM specific.  */
 210 #define ARC_SHIFT    0x1000
 211
 212 /* V2 specific.  */
 213 #define ARC_INTR     0x1000
 214 #define ARC_DIV      0x1000
 215
 216 /* V1 specific.  */
 217 #define ARC_XMAC     0x1000
 218 #define ARC_CRC      0x1000
 219
 220 /* A macro to check for short instructions.  */
 221 #define ARC_SHORT(mask)                         \
 222   (((mask) & 0xFFFF0000) ? 0 : 1)
 223
 224 /* The operands table is an array of struct arc_operand.  */
 225 struct arc_operand
 226 {
 227   /* The number of bits in the operand.  */
 228   unsigned int bits;
 229
 230   /* How far the operand is left shifted in the instruction.  */
 231   unsigned int shift;
 232
 233   /* The default relocation type for this operand.  */
 234   signed int default_reloc;
 235
 236   /* One bit syntax flags.  */
 237   unsigned int flags;
 238
 239   /* Insertion function.  This is used by the assembler.  To insert an
 240      operand value into an instruction, check this field.
 241
 242      If it is NULL, execute
 243          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 244      (i is the instruction which we are filling in, o is a pointer to
 245      this structure, and op is the opcode value; this assumes twos
 246      complement arithmetic).
 247
 248      If this field is not NULL, then simply call it with the
 249      instruction and the operand value.  It will return the new value
 250      of the instruction.  If the ERRMSG argument is not NULL, then if
 251      the operand value is illegal, *ERRMSG will be set to a warning
 252      string (the operand will be inserted in any case).  If the
 253      operand value is legal, *ERRMSG will be unchanged (most operands
 254      can accept any value).  */
 255   unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
 256
 257   /* Extraction function.  This is used by the disassembler.  To
 258      extract this operand type from an instruction, check this field.
 259
 260      If it is NULL, compute
 261          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 262          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 263              && (op & (1 << (o->bits - 1))) != 0)
 264            op -= 1 << o->bits;
 265      (i is the instruction, o is a pointer to this structure, and op
 266      is the result; this assumes twos complement arithmetic).
 267
 268      If this field is not NULL, then simply call it with the
 269      instruction value.  It will return the value of the operand.  If
 270      the INVALID argument is not NULL, *INVALID will be set to
 271      TRUE if this operand type can not actually be extracted from
 272      this operand (i.e., the instruction does not match).  If the
 273      operand is valid, *INVALID will not be changed.  */
 274   int (*extract) (unsigned instruction, bfd_boolean *invalid);
 275 };
 276
 277 /* Elements in the table are retrieved by indexing with values from
 278    the operands field of the arc_opcodes table.  */
 279 extern const struct arc_operand arc_operands[];
 280 extern const unsigned arc_num_operands;
 281 extern const unsigned arc_Toperand;
 282 extern const unsigned arc_NToperand;
 283
 284 /* Values defined for the flags field of a struct arc_operand.  */
 285
 286 /* This operand does not actually exist in the assembler input.  This
 287    is used to support extended mnemonics, for which two operands fields
 288    are identical.  The assembler should call the insert function with
 289    any op value.  The disassembler should call the extract function,
 290    ignore the return value, and check the value placed in the invalid
 291    argument.  */
 292 #define ARC_OPERAND_FAKE        0x0001
 293
 294 /* This operand names an integer register.  */
 295 #define ARC_OPERAND_IR          0x0002
 296
 297 /* This operand takes signed values.  */
 298 #define ARC_OPERAND_SIGNED      0x0004
 299
 300 /* This operand takes unsigned values.  This exists primarily so that
 301    a flags value of 0 can be treated as end-of-arguments.  */
 302 #define ARC_OPERAND_UNSIGNED    0x0008
 303
 304 /* This operand takes long immediate values.  */
 305 #define ARC_OPERAND_LIMM        0x0010
 306
 307 /* This operand is identical like the previous one.  */
 308 #define ARC_OPERAND_DUPLICATE   0x0020
 309
 310 /* This operand is PC relative.  Used for internal relocs.  */
 311 #define ARC_OPERAND_PCREL       0x0040
 312
 313 /* This operand is truncated.  The truncation is done accordingly to
 314    operand alignment attribute.  */
 315 #define ARC_OPERAND_TRUNCATE    0x0080
 316
 317 /* This operand is 16bit aligned.  */
 318 #define ARC_OPERAND_ALIGNED16   0x0100
 319
 320 /* This operand is 32bit aligned.  */
 321 #define ARC_OPERAND_ALIGNED32   0x0200
 322
 323 /* This operand can be ignored by matching process if it is not
 324    present.  */
 325 #define ARC_OPERAND_IGNORE      0x0400
 326
 327 /* Don't check the range when matching.  */
 328 #define ARC_OPERAND_NCHK        0x0800
 329
 330 /* Mark the braket possition.  */
 331 #define ARC_OPERAND_BRAKET      0x1000
 332
 333 /* Mask for selecting the type for typecheck purposes.  */
 334 #define ARC_OPERAND_TYPECHECK_MASK              \
 335   (ARC_OPERAND_IR |                             \
 336    ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED |      \
 337    ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
 338
 339 /* The flags structure.  */
 340 struct arc_flag_operand
 341 {
 342   /* The flag name.  */
 343   const char *name;
 344
 345   /* The flag code.  */
 346   unsigned code;
 347
 348   /* The number of bits in the operand.  */
 349   unsigned int bits;
 350
 351   /* How far the operand is left shifted in the instruction.  */
 352   unsigned int shift;
 353
 354   /* Available for disassembler.  */
 355   unsigned char favail;
 356 };
 357
 358 /* The flag operands table.  */
 359 extern const struct arc_flag_operand arc_flag_operands[];
 360 extern const unsigned arc_num_flag_operands;
 361
 362 /* The flag's class structure.  */
 363 struct arc_flag_class
 364 {
 365   /* Flag class.  */
 366   flag_class_t flag_class;
 367
 368   /* List of valid flags (codes).  */
 369   unsigned flags[256];
 370 };
 371
 372 extern const struct arc_flag_class arc_flag_classes[];
 373
 374 /* Structure for special cases.  */
 375 struct arc_flag_special
 376 {
 377   /* Name of special case instruction.  */
 378   const char *name;
 379
 380   /* List of flags applicable for special case instruction.  */
 381   unsigned flags[32];
 382 };
 383
 384 extern const struct arc_flag_special arc_flag_special_cases[];
 385 extern const unsigned arc_num_flag_special;
 386
 387 /* Relocation equivalence structure.  */
 388 struct arc_reloc_equiv_tab
 389 {
 390   const char * name;       /* String to lookup.  */
 391   const char * mnemonic;   /* Extra matching condition.  */
 392   unsigned     flags[32];  /* Extra matching condition.  */
 393   signed int   oldreloc;   /* Old relocation.  */
 394   signed int   newreloc;   /* New relocation.  */
 395 };
 396
 397 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 398 extern const unsigned arc_num_equiv_tab;
 399
 400 /* Structure for operand operations for pseudo/alias instructions.  */
 401 struct arc_operand_operation
 402 {
 403   /* The index for operand from operand array.  */
 404   unsigned operand_idx;
 405
 406   /* Defines if it needs the operand inserted by the assembler or
 407      whether this operand comes from the pseudo instruction's
 408      operands.  */
 409   unsigned char needs_insert;
 410
 411   /* Count we have to add to the operand.  Use negative number to
 412      subtract from the operand.  Also use this number to add to 0 if
 413      the operand needs to be inserted (i.e. needs_insert == 1).  */
 414   int count;
 415
 416   /* Index of the operand to swap with.  To be done AFTER applying
 417      inc_count.  */
 418   unsigned swap_operand_idx;
 419 };
 420
 421 /* Structure for pseudo/alias instructions.  */
 422 struct arc_pseudo_insn
 423 {
 424   /* Mnemonic for pseudo/alias insn.  */
 425   const char *mnemonic_p;
 426
 427   /* Mnemonic for real instruction.  */
 428   const char *mnemonic_r;
 429
 430   /* Flag that will have to be added (if any).  */
 431   const char *flag_r;
 432
 433   /* Amount of operands.  */
 434   unsigned operand_cnt;
 435
 436   /* Array of operand operations.  */
 437   struct arc_operand_operation operand[6];
 438 };
 439
 440 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 441 extern const unsigned arc_num_pseudo_insn;
 442
 443 /* Structure for AUXILIARY registers.  */
 444 struct arc_aux_reg
 445 {
 446   /* Register address.  */
 447   int address;
 448
 449   /* One bit flags for the opcode.  These are primarily used to
 450      indicate specific processors and environments support the
 451      instructions.  */
 452   unsigned cpu;
 453
 454   /* AUX register subclass.  */
 455   insn_subclass_t subclass;
 456
 457   /* Register name.  */
 458   const char *name;
 459
 460   /* Size of the string.  */
 461   size_t length;
 462 };
 463
 464 extern const struct arc_aux_reg arc_aux_regs[];
 465 extern const unsigned arc_num_aux_regs;
 466
 467 extern const struct arc_opcode arc_relax_opcodes[];
 468 extern const unsigned arc_num_relax_opcodes;
 469
 470 /* Macro used for generating one class of NPS instructions.  */
 471 #define NPS_CMEM_HIGH_VALUE 0x57f0
 472
 473 /* Macros to help generating regular pattern instructions.  */
 474 #define FIELDA(word) (word & 0x3F)
 475 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 476 #define FIELDC(word) ((word & 0x3F) << 6)
 477 #define FIELDF       (0x01 << 15)
 478 #define FIELDQ       (0x1F)
 479
 480 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 481 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 482 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 483
 484 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 485 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 486 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 487 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 488 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 489 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 490 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 491 #define INSN3OP_0LL(MOP,SOP)                                    \
 492   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 493 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 494 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 495 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 496 #define INSN3OP_0LU(MOP,SOP)                                    \
 497   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 498 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 499 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 500 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 501 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 502 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 503 #define INSN3OP_C0LL(MOP,SOP)                                   \
 504   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 505 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 506 #define INSN3OP_C0LU(MOP,SOP)                                   \
 507   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 508
 509 #define MINSN3OP_ABC  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 510 #define MINSN3OP_ALC  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 511 #define MINSN3OP_ABL  (~(FIELDF | FIELDA (63) | FIELDB (63)))
 512 #define MINSN3OP_ALL  (~(FIELDF | FIELDA (63)))
 513 #define MINSN3OP_0BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 514 #define MINSN3OP_0LC  (~(FIELDF | FIELDC (63)))
 515 #define MINSN3OP_0BL  (~(FIELDF | FIELDB (63)))
 516 #define MINSN3OP_0LL  (~(FIELDF))
 517 #define MINSN3OP_ABU  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 518 #define MINSN3OP_ALU  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 519 #define MINSN3OP_0BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 520 #define MINSN3OP_0LU  (~(FIELDF | FIELDC (63)))
 521 #define MINSN3OP_BBS  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 522 #define MINSN3OP_0LS  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 523 #define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 524 #define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
 525 #define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
 526 #define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
 527 #define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 528 #define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
 529
 530 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 531 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 532 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 533 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 534 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 535 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 536
 537 #define MINSN2OP_BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 538 #define MINSN2OP_BL  (~(FIELDF | FIELDB (63)))
 539 #define MINSN2OP_0C  (~(FIELDF | FIELDC (63)))
 540 #define MINSN2OP_0L  (~(FIELDF))
 541 #define MINSN2OP_BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 542 #define MINSN2OP_0U  (~(FIELDF | FIELDC (63)))
 543
 544 /* Various constants used when defining an extension instruction.  */
 545 #define ARC_SYNTAX_3OP          (1 << 0)
 546 #define ARC_SYNTAX_2OP          (1 << 1)
 547 #define ARC_SYNTAX_1OP          (1 << 2)
 548 #define ARC_SYNTAX_NOP          (1 << 3)
 549 #define ARC_SYNTAX_MASK         (0x0F)
 550
 551 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 552 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 553
 554 #define ARC_SUFFIX_NONE         (1 << 0)
 555 #define ARC_SUFFIX_COND         (1 << 1)
 556 #define ARC_SUFFIX_FLAG         (1 << 2)
 557
 558 #define ARC_REGISTER_READONLY    (1 << 0)
 559 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 560 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 561
 562 /* Constants needed to initialize extension instructions.  */
 563 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 564 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 565 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 566 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 567
 568 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 569 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 570 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 571 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 572 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 573 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 574 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 575 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 576 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 577 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 578 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 579 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 580
 581 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 582 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 583 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 584
 585 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 586 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 587 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 588
 589 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 590 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 591 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 592 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 593 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 594 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 595
 596 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 597 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 598 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 599 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 600
 601 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 602 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 604
 605 #endif /* OPCODE_ARC_H */