1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS or GDB; see the file COPYING3. If not, write to
21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
32 #define MAX_INSN_ARGS 16
36 #define MAX_INSN_FLGS 3
39 /* Instruction Class. */
63 /* Instruction Subclass. */
95 /* At most one flag from the set of flags can appear in the
97 F_CLASS_OPTIONAL
= (1 << 0),
99 /* Exactly one from from the set of flags must appear in the
101 F_CLASS_REQUIRED
= (1 << 1),
103 /* The conditional code can be extended over the standard variants
104 via .extCondCode pseudo-op. */
105 F_CLASS_EXTEND
= (1 << 2),
107 /* Condition code flag. */
108 F_CLASS_COND
= (1 << 3)
111 /* The opcode table is an array of struct arc_opcode. */
114 /* The opcode name. */
117 /* The opcode itself. Those bits which will be filled in with
118 operands are zeroes. */
121 /* The opcode mask. This is used by the disassembler. This is a
122 mask containing ones indicating those bits which must match the
123 opcode field, and zeroes indicating those bits which need not
124 match (and are presumably filled in by operands). */
127 /* One bit flags for the opcode. These are primarily used to
128 indicate specific processors and environments support the
129 instructions. The defined values are listed below. */
132 /* The instruction class. This is used by gdb. */
133 insn_class_t insn_class
;
135 /* The instruction subclass. */
136 insn_subclass_t subclass
;
138 /* An array of operand codes. Each code is an index into the
139 operand table. They appear in the order which the operands must
140 appear in assembly code, and are terminated by a zero. */
141 unsigned char operands
[MAX_INSN_ARGS
+ 1];
143 /* An array of flag codes. Each code is an index into the flag
144 table. They appear in the order which the flags must appear in
145 assembly code, and are terminated by a zero. */
146 unsigned char flags
[MAX_INSN_FLGS
+ 1];
149 /* Structure used to describe 48 and 64 bit instructions. */
150 struct arc_long_opcode
152 /* The base instruction is either 16 or 32 bits, and is described like a
153 normal instruction. */
154 struct arc_opcode base_opcode
;
156 /* The template value for the 32-bit LIMM extension. Used by the
157 assembler and disassembler in the same way as the 'opcode' field of
158 'struct arc_opcode'. */
159 unsigned limm_template
;
161 /* The mask value for the 32-bit LIMM extension. Used by the
162 disassembler just like the 'mask' field in 'struct arc_opcode'. */
165 /* Array of operand codes similar to the 'operands' array in 'struct
166 arc_opcode'. These operands are used to fill in the LIMM value. */
167 unsigned char operands
[MAX_INSN_ARGS
+ 1];
170 extern const struct arc_long_opcode arc_long_opcodes
[];
171 extern const unsigned arc_num_long_opcodes
;
173 /* The table itself is sorted by major opcode number, and is otherwise
174 in the order in which the disassembler should consider
176 extern const struct arc_opcode arc_opcodes
[];
178 /* CPU Availability. */
179 #define ARC_OPCODE_NONE 0x0000
180 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
181 #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
182 #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
183 #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
186 #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
187 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
188 #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
190 /* CPU extensions. */
191 #define ARC_EA 0x0001
192 #define ARC_CD 0x0001 /* Mutual exclusive with EA. */
193 #define ARC_LLOCK 0x0002
194 #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
195 #define ARC_MPY 0x0004
196 #define ARC_MULT 0x0004
197 #define ARC_NPS400 0x0008
199 /* Floating point support. */
200 #define ARC_DPFP 0x0010
201 #define ARC_SPFP 0x0020
202 #define ARC_FPU 0x0030
203 #define ARC_FPUDA 0x0040
206 #define ARC_SWAP 0x0100
207 #define ARC_NORM 0x0200
208 #define ARC_BSCAN 0x0200
211 #define ARC_UIX 0x1000
212 #define ARC_TSTAMP 0x1000
215 #define ARC_VBFDW 0x1000
216 #define ARC_BARREL 0x1000
217 #define ARC_DSPA 0x1000
220 #define ARC_SHIFT 0x1000
223 #define ARC_INTR 0x1000
224 #define ARC_DIV 0x1000
227 #define ARC_XMAC 0x1000
228 #define ARC_CRC 0x1000
230 /* A macro to check for short instructions. */
231 #define ARC_SHORT(mask) \
232 (((mask) & 0xFFFF0000) ? 0 : 1)
234 /* The operands table is an array of struct arc_operand. */
237 /* The number of bits in the operand. */
240 /* How far the operand is left shifted in the instruction. */
243 /* The default relocation type for this operand. */
244 signed int default_reloc
;
246 /* One bit syntax flags. */
249 /* Insertion function. This is used by the assembler. To insert an
250 operand value into an instruction, check this field.
252 If it is NULL, execute
253 i |= (op & ((1 << o->bits) - 1)) << o->shift;
254 (i is the instruction which we are filling in, o is a pointer to
255 this structure, and op is the opcode value; this assumes twos
256 complement arithmetic).
258 If this field is not NULL, then simply call it with the
259 instruction and the operand value. It will return the new value
260 of the instruction. If the ERRMSG argument is not NULL, then if
261 the operand value is illegal, *ERRMSG will be set to a warning
262 string (the operand will be inserted in any case). If the
263 operand value is legal, *ERRMSG will be unchanged (most operands
264 can accept any value). */
265 unsigned (*insert
) (unsigned instruction
, int op
, const char **errmsg
);
267 /* Extraction function. This is used by the disassembler. To
268 extract this operand type from an instruction, check this field.
270 If it is NULL, compute
271 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
272 if ((o->flags & ARC_OPERAND_SIGNED) != 0
273 && (op & (1 << (o->bits - 1))) != 0)
275 (i is the instruction, o is a pointer to this structure, and op
276 is the result; this assumes twos complement arithmetic).
278 If this field is not NULL, then simply call it with the
279 instruction value. It will return the value of the operand. If
280 the INVALID argument is not NULL, *INVALID will be set to
281 TRUE if this operand type can not actually be extracted from
282 this operand (i.e., the instruction does not match). If the
283 operand is valid, *INVALID will not be changed. */
284 int (*extract
) (unsigned instruction
, bfd_boolean
*invalid
);
287 /* Elements in the table are retrieved by indexing with values from
288 the operands field of the arc_opcodes table. */
289 extern const struct arc_operand arc_operands
[];
290 extern const unsigned arc_num_operands
;
291 extern const unsigned arc_Toperand
;
292 extern const unsigned arc_NToperand
;
294 /* Values defined for the flags field of a struct arc_operand. */
296 /* This operand does not actually exist in the assembler input. This
297 is used to support extended mnemonics, for which two operands fields
298 are identical. The assembler should call the insert function with
299 any op value. The disassembler should call the extract function,
300 ignore the return value, and check the value placed in the invalid
302 #define ARC_OPERAND_FAKE 0x0001
304 /* This operand names an integer register. */
305 #define ARC_OPERAND_IR 0x0002
307 /* This operand takes signed values. */
308 #define ARC_OPERAND_SIGNED 0x0004
310 /* This operand takes unsigned values. This exists primarily so that
311 a flags value of 0 can be treated as end-of-arguments. */
312 #define ARC_OPERAND_UNSIGNED 0x0008
314 /* This operand takes long immediate values. */
315 #define ARC_OPERAND_LIMM 0x0010
317 /* This operand is identical like the previous one. */
318 #define ARC_OPERAND_DUPLICATE 0x0020
320 /* This operand is PC relative. Used for internal relocs. */
321 #define ARC_OPERAND_PCREL 0x0040
323 /* This operand is truncated. The truncation is done accordingly to
324 operand alignment attribute. */
325 #define ARC_OPERAND_TRUNCATE 0x0080
327 /* This operand is 16bit aligned. */
328 #define ARC_OPERAND_ALIGNED16 0x0100
330 /* This operand is 32bit aligned. */
331 #define ARC_OPERAND_ALIGNED32 0x0200
333 /* This operand can be ignored by matching process if it is not
335 #define ARC_OPERAND_IGNORE 0x0400
337 /* Don't check the range when matching. */
338 #define ARC_OPERAND_NCHK 0x0800
340 /* Mark the braket possition. */
341 #define ARC_OPERAND_BRAKET 0x1000
343 /* Address type operand for NPS400. */
344 #define ARC_OPERAND_ADDRTYPE 0x2000
346 /* Mark the colon position. */
347 #define ARC_OPERAND_COLON 0x4000
349 /* Mask for selecting the type for typecheck purposes. */
350 #define ARC_OPERAND_TYPECHECK_MASK \
352 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
353 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
354 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
356 /* Macro to determine if an operand is a fake operand. */
357 #define ARC_OPERAND_IS_FAKE(op) \
358 ((operand->flags & ARC_OPERAND_FAKE) \
359 && !((operand->flags & ARC_OPERAND_BRAKET) \
360 || (operand->flags & ARC_OPERAND_COLON)))
362 /* The flags structure. */
363 struct arc_flag_operand
371 /* The number of bits in the operand. */
374 /* How far the operand is left shifted in the instruction. */
377 /* Available for disassembler. */
378 unsigned char favail
;
381 /* The flag operands table. */
382 extern const struct arc_flag_operand arc_flag_operands
[];
383 extern const unsigned arc_num_flag_operands
;
385 /* The flag's class structure. */
386 struct arc_flag_class
389 flag_class_t flag_class
;
391 /* List of valid flags (codes). */
395 extern const struct arc_flag_class arc_flag_classes
[];
397 /* Structure for special cases. */
398 struct arc_flag_special
400 /* Name of special case instruction. */
403 /* List of flags applicable for special case instruction. */
407 extern const struct arc_flag_special arc_flag_special_cases
[];
408 extern const unsigned arc_num_flag_special
;
410 /* Relocation equivalence structure. */
411 struct arc_reloc_equiv_tab
413 const char * name
; /* String to lookup. */
414 const char * mnemonic
; /* Extra matching condition. */
415 unsigned flags
[32]; /* Extra matching condition. */
416 signed int oldreloc
; /* Old relocation. */
417 signed int newreloc
; /* New relocation. */
420 extern const struct arc_reloc_equiv_tab arc_reloc_equiv
[];
421 extern const unsigned arc_num_equiv_tab
;
423 /* Structure for operand operations for pseudo/alias instructions. */
424 struct arc_operand_operation
426 /* The index for operand from operand array. */
427 unsigned operand_idx
;
429 /* Defines if it needs the operand inserted by the assembler or
430 whether this operand comes from the pseudo instruction's
432 unsigned char needs_insert
;
434 /* Count we have to add to the operand. Use negative number to
435 subtract from the operand. Also use this number to add to 0 if
436 the operand needs to be inserted (i.e. needs_insert == 1). */
439 /* Index of the operand to swap with. To be done AFTER applying
441 unsigned swap_operand_idx
;
444 /* Structure for pseudo/alias instructions. */
445 struct arc_pseudo_insn
447 /* Mnemonic for pseudo/alias insn. */
448 const char *mnemonic_p
;
450 /* Mnemonic for real instruction. */
451 const char *mnemonic_r
;
453 /* Flag that will have to be added (if any). */
456 /* Amount of operands. */
457 unsigned operand_cnt
;
459 /* Array of operand operations. */
460 struct arc_operand_operation operand
[6];
463 extern const struct arc_pseudo_insn arc_pseudo_insns
[];
464 extern const unsigned arc_num_pseudo_insn
;
466 /* Structure for AUXILIARY registers. */
469 /* Register address. */
472 /* One bit flags for the opcode. These are primarily used to
473 indicate specific processors and environments support the
477 /* AUX register subclass. */
478 insn_subclass_t subclass
;
483 /* Size of the string. */
487 extern const struct arc_aux_reg arc_aux_regs
[];
488 extern const unsigned arc_num_aux_regs
;
490 extern const struct arc_opcode arc_relax_opcodes
[];
491 extern const unsigned arc_num_relax_opcodes
;
493 /* Macro used for generating one class of NPS instructions. */
494 #define NPS_CMEM_HIGH_VALUE 0x57f0
496 /* Macros to help generating regular pattern instructions. */
497 #define FIELDA(word) (word & 0x3F)
498 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
499 #define FIELDC(word) ((word & 0x3F) << 6)
500 #define FIELDF (0x01 << 15)
501 #define FIELDQ (0x1F)
503 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
504 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
505 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
507 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
508 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
509 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
510 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
511 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
512 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
513 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
514 #define INSN3OP_0LL(MOP,SOP) \
515 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
516 #define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
517 #define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
518 #define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
519 #define INSN3OP_0LU(MOP,SOP) \
520 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
521 #define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
522 #define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
523 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
524 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
525 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
526 #define INSN3OP_C0LL(MOP,SOP) \
527 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
528 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
529 #define INSN3OP_C0LU(MOP,SOP) \
530 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
532 #define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
533 #define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
534 #define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
535 #define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
536 #define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
537 #define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
538 #define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
539 #define MINSN3OP_0LL (~(FIELDF))
540 #define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
541 #define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
542 #define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
543 #define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
544 #define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
545 #define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
546 #define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
547 #define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
548 #define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
549 #define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
550 #define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
551 #define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
553 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
554 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
555 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
556 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
557 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
558 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
560 #define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
561 #define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
562 #define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
563 #define MINSN2OP_0L (~(FIELDF))
564 #define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
565 #define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
567 /* Various constants used when defining an extension instruction. */
568 #define ARC_SYNTAX_3OP (1 << 0)
569 #define ARC_SYNTAX_2OP (1 << 1)
570 #define ARC_SYNTAX_1OP (1 << 2)
571 #define ARC_SYNTAX_NOP (1 << 3)
572 #define ARC_SYNTAX_MASK (0x0F)
574 #define ARC_OP1_MUST_BE_IMM (1 << 0)
575 #define ARC_OP1_IMM_IMPLIED (1 << 1)
577 #define ARC_SUFFIX_NONE (1 << 0)
578 #define ARC_SUFFIX_COND (1 << 1)
579 #define ARC_SUFFIX_FLAG (1 << 2)
581 #define ARC_REGISTER_READONLY (1 << 0)
582 #define ARC_REGISTER_WRITEONLY (1 << 1)
583 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
585 /* Constants needed to initialize extension instructions. */
586 extern const unsigned char flags_none
[MAX_INSN_FLGS
+ 1];
587 extern const unsigned char flags_f
[MAX_INSN_FLGS
+ 1];
588 extern const unsigned char flags_cc
[MAX_INSN_FLGS
+ 1];
589 extern const unsigned char flags_ccf
[MAX_INSN_FLGS
+ 1];
591 extern const unsigned char arg_none
[MAX_INSN_ARGS
+ 1];
592 extern const unsigned char arg_32bit_rarbrc
[MAX_INSN_ARGS
+ 1];
593 extern const unsigned char arg_32bit_zarbrc
[MAX_INSN_ARGS
+ 1];
594 extern const unsigned char arg_32bit_rbrbrc
[MAX_INSN_ARGS
+ 1];
595 extern const unsigned char arg_32bit_rarbu6
[MAX_INSN_ARGS
+ 1];
596 extern const unsigned char arg_32bit_zarbu6
[MAX_INSN_ARGS
+ 1];
597 extern const unsigned char arg_32bit_rbrbu6
[MAX_INSN_ARGS
+ 1];
598 extern const unsigned char arg_32bit_rbrbs12
[MAX_INSN_ARGS
+ 1];
599 extern const unsigned char arg_32bit_ralimmrc
[MAX_INSN_ARGS
+ 1];
600 extern const unsigned char arg_32bit_rarblimm
[MAX_INSN_ARGS
+ 1];
601 extern const unsigned char arg_32bit_zalimmrc
[MAX_INSN_ARGS
+ 1];
602 extern const unsigned char arg_32bit_zarblimm
[MAX_INSN_ARGS
+ 1];
604 extern const unsigned char arg_32bit_rbrblimm
[MAX_INSN_ARGS
+ 1];
605 extern const unsigned char arg_32bit_ralimmu6
[MAX_INSN_ARGS
+ 1];
606 extern const unsigned char arg_32bit_zalimmu6
[MAX_INSN_ARGS
+ 1];
608 extern const unsigned char arg_32bit_zalimms12
[MAX_INSN_ARGS
+ 1];
609 extern const unsigned char arg_32bit_ralimmlimm
[MAX_INSN_ARGS
+ 1];
610 extern const unsigned char arg_32bit_zalimmlimm
[MAX_INSN_ARGS
+ 1];
612 extern const unsigned char arg_32bit_rbrc
[MAX_INSN_ARGS
+ 1];
613 extern const unsigned char arg_32bit_zarc
[MAX_INSN_ARGS
+ 1];
614 extern const unsigned char arg_32bit_rbu6
[MAX_INSN_ARGS
+ 1];
615 extern const unsigned char arg_32bit_zau6
[MAX_INSN_ARGS
+ 1];
616 extern const unsigned char arg_32bit_rblimm
[MAX_INSN_ARGS
+ 1];
617 extern const unsigned char arg_32bit_zalimm
[MAX_INSN_ARGS
+ 1];
619 extern const unsigned char arg_32bit_limmrc
[MAX_INSN_ARGS
+ 1];
620 extern const unsigned char arg_32bit_limmu6
[MAX_INSN_ARGS
+ 1];
621 extern const unsigned char arg_32bit_limms12
[MAX_INSN_ARGS
+ 1];
622 extern const unsigned char arg_32bit_limmlimm
[MAX_INSN_ARGS
+ 1];
624 extern const unsigned char arg_32bit_rc
[MAX_INSN_ARGS
+ 1];
625 extern const unsigned char arg_32bit_u6
[MAX_INSN_ARGS
+ 1];
626 extern const unsigned char arg_32bit_limm
[MAX_INSN_ARGS
+ 1];
628 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
629 Instruction Set Reference Manual v2.4 for a description of address types. */
633 /* Addresses in memory. */
635 /* Buffer descriptor. */
636 ARC_NPS400_ADDRTYPE_BD
,
638 /* Job identifier. */
639 ARC_NPS400_ADDRTYPE_JID
,
641 /* Linked Buffer Descriptor. */
642 ARC_NPS400_ADDRTYPE_LBD
,
644 /* Multicast Buffer Descriptor. */
645 ARC_NPS400_ADDRTYPE_MBD
,
647 /* Summarized Address. */
648 ARC_NPS400_ADDRTYPE_SD
,
650 /* SMEM Security Context Local Memory. */
651 ARC_NPS400_ADDRTYPE_SM
,
653 /* Extended Address. */
654 ARC_NPS400_ADDRTYPE_XA
,
656 /* Extended Summarized Address. */
657 ARC_NPS400_ADDRTYPE_XD
,
659 /* CMEM offset addresses. */
661 /* On-demand Counter Descriptor. */
662 ARC_NPS400_ADDRTYPE_CD
,
664 /* CMEM Buffer Descriptor. */
665 ARC_NPS400_ADDRTYPE_CBD
,
667 /* CMEM Job Identifier. */
668 ARC_NPS400_ADDRTYPE_CJID
,
670 /* CMEM Linked Buffer Descriptor. */
671 ARC_NPS400_ADDRTYPE_CLBD
,
674 ARC_NPS400_ADDRTYPE_CM
,
676 /* CMEM Summarized Address. */
677 ARC_NPS400_ADDRTYPE_CSD
,
679 /* CMEM Extended Address. */
680 ARC_NPS400_ADDRTYPE_CXA
,
682 /* CMEM Extended Summarized Address. */
683 ARC_NPS400_ADDRTYPE_CXD
685 } arc_nps_address_type
;
687 #define ARC_NUM_ADDRTYPES 16
693 #endif /* OPCODE_ARC_H */