include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifndef MAX_INSN_ARGS
  28 #define MAX_INSN_ARGS        16
  29 #endif
  30
  31 #ifndef MAX_INSN_FLGS
  32 #define MAX_INSN_FLGS        3
  33 #endif
  34
  35 /* Instruction Class.  */
  36 typedef enum
  37   {
  38     ARITH,
  39     AUXREG,
  40     BRANCH,
  41     CONTROL,
  42     DSP,
  43     FLOAT,
  44     INVALID,
  45     JUMP,
  46     KERNEL,
  47     LOGICAL,
  48     MEMORY,
  49     BITOP,
  50     NET,
  51     ACL,
  52     DPI,
  53   } insn_class_t;
  54
  55 /* Instruction Subclass.  */
  56 typedef enum
  57   {
  58     NONE,
  59     CVT,
  60     BTSCN,
  61     CD1,
  62     CD2,
  63     COND,
  64     DIV,
  65     DP,
  66     DPA,
  67     DPX,
  68     MPY1E,
  69     MPY6E,
  70     MPY7E,
  71     MPY8E,
  72     MPY9E,
  73     QUARKSE,
  74     SHFT1,
  75     SHFT2,
  76     SWAP,
  77     SP,
  78     SPX
  79   } insn_subclass_t;
  80
  81 /* Flags class.  */
  82 typedef enum
  83   {
  84     F_CLASS_NONE = 0,
  85
  86     /* At most one flag from the set of flags can appear in the
  87        instruction.  */
  88     F_CLASS_OPTIONAL = (1 << 0),
  89
  90     /* Exactly one from from the set of flags must appear in the
  91        instruction.  */
  92     F_CLASS_REQUIRED = (1 << 1),
  93
  94     /* The conditional code can be extended over the standard variants
  95        via .extCondCode pseudo-op.  */
  96     F_CLASS_EXTEND = (1 << 2),
  97
  98     /* Condition code flag.  */
  99     F_CLASS_COND = (1 << 3)
 100   } flag_class_t;
 101
 102 /* The opcode table is an array of struct arc_opcode.  */
 103 struct arc_opcode
 104 {
 105   /* The opcode name.  */
 106   const char *name;
 107
 108   /* The opcode itself.  Those bits which will be filled in with
 109      operands are zeroes.  */
 110   unsigned opcode;
 111
 112   /* The opcode mask.  This is used by the disassembler.  This is a
 113      mask containing ones indicating those bits which must match the
 114      opcode field, and zeroes indicating those bits which need not
 115      match (and are presumably filled in by operands).  */
 116   unsigned mask;
 117
 118   /* One bit flags for the opcode.  These are primarily used to
 119      indicate specific processors and environments support the
 120      instructions.  The defined values are listed below.  */
 121   unsigned cpu;
 122
 123   /* The instruction class.  This is used by gdb.  */
 124   insn_class_t insn_class;
 125
 126   /* The instruction subclass.  */
 127   insn_subclass_t subclass;
 128
 129   /* An array of operand codes.  Each code is an index into the
 130      operand table.  They appear in the order which the operands must
 131      appear in assembly code, and are terminated by a zero.  */
 132   unsigned char operands[MAX_INSN_ARGS + 1];
 133
 134   /* An array of flag codes.  Each code is an index into the flag
 135      table.  They appear in the order which the flags must appear in
 136      assembly code, and are terminated by a zero.  */
 137   unsigned char flags[MAX_INSN_FLGS + 1];
 138 };
 139
 140 /* Structure used to describe 48 and 64 bit instructions.  */
 141 struct arc_long_opcode
 142 {
 143   /* The base instruction is either 16 or 32 bits, and is described like a
 144      normal instruction.  */
 145   struct arc_opcode base_opcode;
 146
 147   /* The template value for the 32-bit LIMM extension.  Used by the
 148      assembler and disassembler in the same way as the 'opcode' field of
 149      'struct arc_opcode'.  */
 150   unsigned limm_template;
 151
 152   /* The mask value for the 32-bit LIMM extension.  Used by the
 153      disassembler just like the 'mask' field in 'struct arc_opcode'.  */
 154   unsigned limm_mask;
 155
 156   /* Array of operand codes similar to the 'operands' array in 'struct
 157      arc_opcode'.  These operands are used to fill in the LIMM value.  */
 158   unsigned char operands[MAX_INSN_ARGS + 1];
 159 };
 160
 161 extern const struct arc_long_opcode arc_long_opcodes[];
 162 extern const unsigned arc_num_long_opcodes;
 163
 164 /* The table itself is sorted by major opcode number, and is otherwise
 165    in the order in which the disassembler should consider
 166    instructions.  */
 167 extern const struct arc_opcode arc_opcodes[];
 168
 169 /* CPU Availability.  */
 170 #define ARC_OPCODE_NONE     0x0000
 171 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 172 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 173 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 174 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 175 #define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */
 176
 177 /* CPU combi.  */
 178 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 179                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 180 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 181
 182 /* CPU extensions.  */
 183 #define ARC_EA       0x0001
 184 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 185 #define ARC_LLOCK    0x0002
 186 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 187 #define ARC_MPY      0x0004
 188 #define ARC_MULT     0x0004
 189
 190 /* Floating point support.  */
 191 #define ARC_DPFP     0x0010
 192 #define ARC_SPFP     0x0020
 193 #define ARC_FPU      0x0030
 194 #define ARC_FPUDA    0x0040
 195
 196 /* NORM & SWAP.  */
 197 #define ARC_SWAP     0x0100
 198 #define ARC_NORM     0x0200
 199 #define ARC_BSCAN    0x0200
 200
 201 /* A7 specific.  */
 202 #define ARC_UIX      0x1000
 203 #define ARC_TSTAMP   0x1000
 204
 205 /* A6 specific.  */
 206 #define ARC_VBFDW    0x1000
 207 #define ARC_BARREL   0x1000
 208 #define ARC_DSPA     0x1000
 209
 210 /* EM specific.  */
 211 #define ARC_SHIFT    0x1000
 212
 213 /* V2 specific.  */
 214 #define ARC_INTR     0x1000
 215 #define ARC_DIV      0x1000
 216
 217 /* V1 specific.  */
 218 #define ARC_XMAC     0x1000
 219 #define ARC_CRC      0x1000
 220
 221 /* A macro to check for short instructions.  */
 222 #define ARC_SHORT(mask)                         \
 223   (((mask) & 0xFFFF0000) ? 0 : 1)
 224
 225 /* The operands table is an array of struct arc_operand.  */
 226 struct arc_operand
 227 {
 228   /* The number of bits in the operand.  */
 229   unsigned int bits;
 230
 231   /* How far the operand is left shifted in the instruction.  */
 232   unsigned int shift;
 233
 234   /* The default relocation type for this operand.  */
 235   signed int default_reloc;
 236
 237   /* One bit syntax flags.  */
 238   unsigned int flags;
 239
 240   /* Insertion function.  This is used by the assembler.  To insert an
 241      operand value into an instruction, check this field.
 242
 243      If it is NULL, execute
 244          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 245      (i is the instruction which we are filling in, o is a pointer to
 246      this structure, and op is the opcode value; this assumes twos
 247      complement arithmetic).
 248
 249      If this field is not NULL, then simply call it with the
 250      instruction and the operand value.  It will return the new value
 251      of the instruction.  If the ERRMSG argument is not NULL, then if
 252      the operand value is illegal, *ERRMSG will be set to a warning
 253      string (the operand will be inserted in any case).  If the
 254      operand value is legal, *ERRMSG will be unchanged (most operands
 255      can accept any value).  */
 256   unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
 257
 258   /* Extraction function.  This is used by the disassembler.  To
 259      extract this operand type from an instruction, check this field.
 260
 261      If it is NULL, compute
 262          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 263          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 264              && (op & (1 << (o->bits - 1))) != 0)
 265            op -= 1 << o->bits;
 266      (i is the instruction, o is a pointer to this structure, and op
 267      is the result; this assumes twos complement arithmetic).
 268
 269      If this field is not NULL, then simply call it with the
 270      instruction value.  It will return the value of the operand.  If
 271      the INVALID argument is not NULL, *INVALID will be set to
 272      TRUE if this operand type can not actually be extracted from
 273      this operand (i.e., the instruction does not match).  If the
 274      operand is valid, *INVALID will not be changed.  */
 275   int (*extract) (unsigned instruction, bfd_boolean *invalid);
 276 };
 277
 278 /* Elements in the table are retrieved by indexing with values from
 279    the operands field of the arc_opcodes table.  */
 280 extern const struct arc_operand arc_operands[];
 281 extern const unsigned arc_num_operands;
 282 extern const unsigned arc_Toperand;
 283 extern const unsigned arc_NToperand;
 284
 285 /* Values defined for the flags field of a struct arc_operand.  */
 286
 287 /* This operand does not actually exist in the assembler input.  This
 288    is used to support extended mnemonics, for which two operands fields
 289    are identical.  The assembler should call the insert function with
 290    any op value.  The disassembler should call the extract function,
 291    ignore the return value, and check the value placed in the invalid
 292    argument.  */
 293 #define ARC_OPERAND_FAKE        0x0001
 294
 295 /* This operand names an integer register.  */
 296 #define ARC_OPERAND_IR          0x0002
 297
 298 /* This operand takes signed values.  */
 299 #define ARC_OPERAND_SIGNED      0x0004
 300
 301 /* This operand takes unsigned values.  This exists primarily so that
 302    a flags value of 0 can be treated as end-of-arguments.  */
 303 #define ARC_OPERAND_UNSIGNED    0x0008
 304
 305 /* This operand takes long immediate values.  */
 306 #define ARC_OPERAND_LIMM        0x0010
 307
 308 /* This operand is identical like the previous one.  */
 309 #define ARC_OPERAND_DUPLICATE   0x0020
 310
 311 /* This operand is PC relative.  Used for internal relocs.  */
 312 #define ARC_OPERAND_PCREL       0x0040
 313
 314 /* This operand is truncated.  The truncation is done accordingly to
 315    operand alignment attribute.  */
 316 #define ARC_OPERAND_TRUNCATE    0x0080
 317
 318 /* This operand is 16bit aligned.  */
 319 #define ARC_OPERAND_ALIGNED16   0x0100
 320
 321 /* This operand is 32bit aligned.  */
 322 #define ARC_OPERAND_ALIGNED32   0x0200
 323
 324 /* This operand can be ignored by matching process if it is not
 325    present.  */
 326 #define ARC_OPERAND_IGNORE      0x0400
 327
 328 /* Don't check the range when matching.  */
 329 #define ARC_OPERAND_NCHK        0x0800
 330
 331 /* Mark the braket possition.  */
 332 #define ARC_OPERAND_BRAKET      0x1000
 333
 334 /* Mask for selecting the type for typecheck purposes.  */
 335 #define ARC_OPERAND_TYPECHECK_MASK              \
 336   (ARC_OPERAND_IR |                             \
 337    ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED |      \
 338    ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
 339
 340 /* The flags structure.  */
 341 struct arc_flag_operand
 342 {
 343   /* The flag name.  */
 344   const char *name;
 345
 346   /* The flag code.  */
 347   unsigned code;
 348
 349   /* The number of bits in the operand.  */
 350   unsigned int bits;
 351
 352   /* How far the operand is left shifted in the instruction.  */
 353   unsigned int shift;
 354
 355   /* Available for disassembler.  */
 356   unsigned char favail;
 357 };
 358
 359 /* The flag operands table.  */
 360 extern const struct arc_flag_operand arc_flag_operands[];
 361 extern const unsigned arc_num_flag_operands;
 362
 363 /* The flag's class structure.  */
 364 struct arc_flag_class
 365 {
 366   /* Flag class.  */
 367   flag_class_t flag_class;
 368
 369   /* List of valid flags (codes).  */
 370   unsigned flags[256];
 371 };
 372
 373 extern const struct arc_flag_class arc_flag_classes[];
 374
 375 /* Structure for special cases.  */
 376 struct arc_flag_special
 377 {
 378   /* Name of special case instruction.  */
 379   const char *name;
 380
 381   /* List of flags applicable for special case instruction.  */
 382   unsigned flags[32];
 383 };
 384
 385 extern const struct arc_flag_special arc_flag_special_cases[];
 386 extern const unsigned arc_num_flag_special;
 387
 388 /* Relocation equivalence structure.  */
 389 struct arc_reloc_equiv_tab
 390 {
 391   const char * name;       /* String to lookup.  */
 392   const char * mnemonic;   /* Extra matching condition.  */
 393   unsigned     flags[32];  /* Extra matching condition.  */
 394   signed int   oldreloc;   /* Old relocation.  */
 395   signed int   newreloc;   /* New relocation.  */
 396 };
 397
 398 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 399 extern const unsigned arc_num_equiv_tab;
 400
 401 /* Structure for operand operations for pseudo/alias instructions.  */
 402 struct arc_operand_operation
 403 {
 404   /* The index for operand from operand array.  */
 405   unsigned operand_idx;
 406
 407   /* Defines if it needs the operand inserted by the assembler or
 408      whether this operand comes from the pseudo instruction's
 409      operands.  */
 410   unsigned char needs_insert;
 411
 412   /* Count we have to add to the operand.  Use negative number to
 413      subtract from the operand.  Also use this number to add to 0 if
 414      the operand needs to be inserted (i.e. needs_insert == 1).  */
 415   int count;
 416
 417   /* Index of the operand to swap with.  To be done AFTER applying
 418      inc_count.  */
 419   unsigned swap_operand_idx;
 420 };
 421
 422 /* Structure for pseudo/alias instructions.  */
 423 struct arc_pseudo_insn
 424 {
 425   /* Mnemonic for pseudo/alias insn.  */
 426   const char *mnemonic_p;
 427
 428   /* Mnemonic for real instruction.  */
 429   const char *mnemonic_r;
 430
 431   /* Flag that will have to be added (if any).  */
 432   const char *flag_r;
 433
 434   /* Amount of operands.  */
 435   unsigned operand_cnt;
 436
 437   /* Array of operand operations.  */
 438   struct arc_operand_operation operand[6];
 439 };
 440
 441 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 442 extern const unsigned arc_num_pseudo_insn;
 443
 444 /* Structure for AUXILIARY registers.  */
 445 struct arc_aux_reg
 446 {
 447   /* Register address.  */
 448   int address;
 449
 450   /* One bit flags for the opcode.  These are primarily used to
 451      indicate specific processors and environments support the
 452      instructions.  */
 453   unsigned cpu;
 454
 455   /* AUX register subclass.  */
 456   insn_subclass_t subclass;
 457
 458   /* Register name.  */
 459   const char *name;
 460
 461   /* Size of the string.  */
 462   size_t length;
 463 };
 464
 465 extern const struct arc_aux_reg arc_aux_regs[];
 466 extern const unsigned arc_num_aux_regs;
 467
 468 extern const struct arc_opcode arc_relax_opcodes[];
 469 extern const unsigned arc_num_relax_opcodes;
 470
 471 /* Macro used for generating one class of NPS instructions.  */
 472 #define NPS_CMEM_HIGH_VALUE 0x57f0
 473
 474 /* Macros to help generating regular pattern instructions.  */
 475 #define FIELDA(word) (word & 0x3F)
 476 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 477 #define FIELDC(word) ((word & 0x3F) << 6)
 478 #define FIELDF       (0x01 << 15)
 479 #define FIELDQ       (0x1F)
 480
 481 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 482 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 483 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 484
 485 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 486 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 487 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 488 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 489 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 490 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 491 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 492 #define INSN3OP_0LL(MOP,SOP)                                    \
 493   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 494 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 495 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 496 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 497 #define INSN3OP_0LU(MOP,SOP)                                    \
 498   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 499 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 500 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 501 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 502 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 503 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 504 #define INSN3OP_C0LL(MOP,SOP)                                   \
 505   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 506 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 507 #define INSN3OP_C0LU(MOP,SOP)                                   \
 508   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 509
 510 #define MINSN3OP_ABC  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 511 #define MINSN3OP_ALC  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 512 #define MINSN3OP_ABL  (~(FIELDF | FIELDA (63) | FIELDB (63)))
 513 #define MINSN3OP_ALL  (~(FIELDF | FIELDA (63)))
 514 #define MINSN3OP_0BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 515 #define MINSN3OP_0LC  (~(FIELDF | FIELDC (63)))
 516 #define MINSN3OP_0BL  (~(FIELDF | FIELDB (63)))
 517 #define MINSN3OP_0LL  (~(FIELDF))
 518 #define MINSN3OP_ABU  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 519 #define MINSN3OP_ALU  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 520 #define MINSN3OP_0BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 521 #define MINSN3OP_0LU  (~(FIELDF | FIELDC (63)))
 522 #define MINSN3OP_BBS  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 523 #define MINSN3OP_0LS  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 524 #define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 525 #define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
 526 #define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
 527 #define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
 528 #define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 529 #define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
 530
 531 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 532 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 533 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 534 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 535 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 536 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 537
 538 #define MINSN2OP_BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 539 #define MINSN2OP_BL  (~(FIELDF | FIELDB (63)))
 540 #define MINSN2OP_0C  (~(FIELDF | FIELDC (63)))
 541 #define MINSN2OP_0L  (~(FIELDF))
 542 #define MINSN2OP_BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 543 #define MINSN2OP_0U  (~(FIELDF | FIELDC (63)))
 544
 545 /* Various constants used when defining an extension instruction.  */
 546 #define ARC_SYNTAX_3OP          (1 << 0)
 547 #define ARC_SYNTAX_2OP          (1 << 1)
 548 #define ARC_SYNTAX_1OP          (1 << 2)
 549 #define ARC_SYNTAX_NOP          (1 << 3)
 550 #define ARC_SYNTAX_MASK         (0x0F)
 551
 552 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 553 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 554
 555 #define ARC_SUFFIX_NONE         (1 << 0)
 556 #define ARC_SUFFIX_COND         (1 << 1)
 557 #define ARC_SUFFIX_FLAG         (1 << 2)
 558
 559 #define ARC_REGISTER_READONLY    (1 << 0)
 560 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 561 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 562
 563 /* Constants needed to initialize extension instructions.  */
 564 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 565 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 566 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 567 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 568
 569 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 570 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 571 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 572 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 573 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 574 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 575 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 576 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 577 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 578 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 579 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 580 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 581
 582 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 583 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 584 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 585
 586 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 587 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 588 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 589
 590 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 591 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 592 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 593 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 594 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 595 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 596
 597 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 598 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 599 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 600 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 601
 602 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 604 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 605
 606 #endif /* OPCODE_ARC_H */