include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #ifndef MAX_INSN_ARGS
  32 #define MAX_INSN_ARGS        16
  33 #endif
  34
  35 #ifndef MAX_INSN_FLGS
  36 #define MAX_INSN_FLGS        3
  37 #endif
  38
  39 /* Instruction Class.  */
  40 typedef enum
  41 {
  42   ACL,
  43   ARITH,
  44   AUXREG,
  45   BITOP,
  46   BITSTREAM,
  47   BMU,
  48   BRANCH,
  49   CONTROL,
  50   DPI,
  51   DSP,
  52   FLOAT,
  53   INVALID,
  54   JUMP,
  55   KERNEL,
  56   LOGICAL,
  57   MEMORY,
  58   NET,
  59   PMU,
  60   XY
  61 } insn_class_t;
  62
  63 /* Instruction Subclass.  */
  64 typedef enum
  65 {
  66   NONE,
  67   CVT,
  68   BTSCN,
  69   CD1,
  70   CD2,
  71   COND,
  72   DIV,
  73   DP,
  74   DPA,
  75   DPX,
  76   MPY1E,
  77   MPY6E,
  78   MPY7E,
  79   MPY8E,
  80   MPY9E,
  81   NPS400,
  82   QUARKSE,
  83   SHFT1,
  84   SHFT2,
  85   SWAP,
  86   SP,
  87   SPX
  88 } insn_subclass_t;
  89
  90 /* Flags class.  */
  91 typedef enum
  92 {
  93   F_CLASS_NONE = 0,
  94
  95   /* At most one flag from the set of flags can appear in the
  96      instruction.  */
  97   F_CLASS_OPTIONAL = (1 << 0),
  98
  99   /* Exactly one from from the set of flags must appear in the
 100      instruction.  */
 101   F_CLASS_REQUIRED = (1 << 1),
 102
 103   /* The conditional code can be extended over the standard variants
 104      via .extCondCode pseudo-op.  */
 105   F_CLASS_EXTEND = (1 << 2),
 106
 107   /* Condition code flag.  */
 108   F_CLASS_COND = (1 << 3)
 109 } flag_class_t;
 110
 111 /* The opcode table is an array of struct arc_opcode.  */
 112 struct arc_opcode
 113 {
 114   /* The opcode name.  */
 115   const char *name;
 116
 117   /* The opcode itself.  Those bits which will be filled in with
 118      operands are zeroes.  */
 119   unsigned opcode;
 120
 121   /* The opcode mask.  This is used by the disassembler.  This is a
 122      mask containing ones indicating those bits which must match the
 123      opcode field, and zeroes indicating those bits which need not
 124      match (and are presumably filled in by operands).  */
 125   unsigned mask;
 126
 127   /* One bit flags for the opcode.  These are primarily used to
 128      indicate specific processors and environments support the
 129      instructions.  The defined values are listed below.  */
 130   unsigned cpu;
 131
 132   /* The instruction class.  This is used by gdb.  */
 133   insn_class_t insn_class;
 134
 135   /* The instruction subclass.  */
 136   insn_subclass_t subclass;
 137
 138   /* An array of operand codes.  Each code is an index into the
 139      operand table.  They appear in the order which the operands must
 140      appear in assembly code, and are terminated by a zero.  */
 141   unsigned char operands[MAX_INSN_ARGS + 1];
 142
 143   /* An array of flag codes.  Each code is an index into the flag
 144      table.  They appear in the order which the flags must appear in
 145      assembly code, and are terminated by a zero.  */
 146   unsigned char flags[MAX_INSN_FLGS + 1];
 147 };
 148
 149 /* Structure used to describe 48 and 64 bit instructions.  */
 150 struct arc_long_opcode
 151 {
 152   /* The base instruction is either 16 or 32 bits, and is described like a
 153      normal instruction.  */
 154   struct arc_opcode base_opcode;
 155
 156   /* The template value for the 32-bit LIMM extension.  Used by the
 157      assembler and disassembler in the same way as the 'opcode' field of
 158      'struct arc_opcode'.  */
 159   unsigned limm_template;
 160
 161   /* The mask value for the 32-bit LIMM extension.  Used by the
 162      disassembler just like the 'mask' field in 'struct arc_opcode'.  */
 163   unsigned limm_mask;
 164
 165   /* Array of operand codes similar to the 'operands' array in 'struct
 166      arc_opcode'.  These operands are used to fill in the LIMM value.  */
 167   unsigned char operands[MAX_INSN_ARGS + 1];
 168 };
 169
 170 extern const struct arc_long_opcode arc_long_opcodes[];
 171 extern const unsigned arc_num_long_opcodes;
 172
 173 /* The table itself is sorted by major opcode number, and is otherwise
 174    in the order in which the disassembler should consider
 175    instructions.  */
 176 extern const struct arc_opcode arc_opcodes[];
 177
 178 /* CPU Availability.  */
 179 #define ARC_OPCODE_NONE     0x0000
 180 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 181 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 182 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 183 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 184
 185 /* CPU combi.  */
 186 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 187                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 188 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 189 #define ARC_OPCODE_ARCV2   (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 190
 191 /* CPU extensions.  */
 192 #define ARC_EA       0x0001
 193 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 194 #define ARC_LLOCK    0x0002
 195 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 196 #define ARC_MPY      0x0004
 197 #define ARC_MULT     0x0004
 198 #define ARC_NPS400   0x0008
 199
 200 /* Floating point support.  */
 201 #define ARC_DPFP     0x0010
 202 #define ARC_SPFP     0x0020
 203 #define ARC_FPU      0x0030
 204 #define ARC_FPUDA    0x0040
 205
 206 /* NORM & SWAP.  */
 207 #define ARC_SWAP     0x0100
 208 #define ARC_NORM     0x0200
 209 #define ARC_BSCAN    0x0200
 210
 211 /* A7 specific.  */
 212 #define ARC_UIX      0x1000
 213 #define ARC_TSTAMP   0x1000
 214
 215 /* A6 specific.  */
 216 #define ARC_VBFDW    0x1000
 217 #define ARC_BARREL   0x1000
 218 #define ARC_DSPA     0x1000
 219
 220 /* EM specific.  */
 221 #define ARC_SHIFT    0x1000
 222
 223 /* V2 specific.  */
 224 #define ARC_INTR     0x1000
 225 #define ARC_DIV      0x1000
 226
 227 /* V1 specific.  */
 228 #define ARC_XMAC     0x1000
 229 #define ARC_CRC      0x1000
 230
 231 /* A macro to check for short instructions.  */
 232 #define ARC_SHORT(mask)                         \
 233   (((mask) & 0xFFFF0000) ? 0 : 1)
 234
 235 /* The operands table is an array of struct arc_operand.  */
 236 struct arc_operand
 237 {
 238   /* The number of bits in the operand.  */
 239   unsigned int bits;
 240
 241   /* How far the operand is left shifted in the instruction.  */
 242   unsigned int shift;
 243
 244   /* The default relocation type for this operand.  */
 245   signed int default_reloc;
 246
 247   /* One bit syntax flags.  */
 248   unsigned int flags;
 249
 250   /* Insertion function.  This is used by the assembler.  To insert an
 251      operand value into an instruction, check this field.
 252
 253      If it is NULL, execute
 254          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 255      (i is the instruction which we are filling in, o is a pointer to
 256      this structure, and op is the opcode value; this assumes twos
 257      complement arithmetic).
 258
 259      If this field is not NULL, then simply call it with the
 260      instruction and the operand value.  It will return the new value
 261      of the instruction.  If the ERRMSG argument is not NULL, then if
 262      the operand value is illegal, *ERRMSG will be set to a warning
 263      string (the operand will be inserted in any case).  If the
 264      operand value is legal, *ERRMSG will be unchanged (most operands
 265      can accept any value).  */
 266   unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
 267
 268   /* Extraction function.  This is used by the disassembler.  To
 269      extract this operand type from an instruction, check this field.
 270
 271      If it is NULL, compute
 272          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 273          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 274              && (op & (1 << (o->bits - 1))) != 0)
 275            op -= 1 << o->bits;
 276      (i is the instruction, o is a pointer to this structure, and op
 277      is the result; this assumes twos complement arithmetic).
 278
 279      If this field is not NULL, then simply call it with the
 280      instruction value.  It will return the value of the operand.  If
 281      the INVALID argument is not NULL, *INVALID will be set to
 282      TRUE if this operand type can not actually be extracted from
 283      this operand (i.e., the instruction does not match).  If the
 284      operand is valid, *INVALID will not be changed.  */
 285   int (*extract) (unsigned instruction, bfd_boolean *invalid);
 286 };
 287
 288 /* Elements in the table are retrieved by indexing with values from
 289    the operands field of the arc_opcodes table.  */
 290 extern const struct arc_operand arc_operands[];
 291 extern const unsigned arc_num_operands;
 292 extern const unsigned arc_Toperand;
 293 extern const unsigned arc_NToperand;
 294
 295 /* Values defined for the flags field of a struct arc_operand.  */
 296
 297 /* This operand does not actually exist in the assembler input.  This
 298    is used to support extended mnemonics, for which two operands fields
 299    are identical.  The assembler should call the insert function with
 300    any op value.  The disassembler should call the extract function,
 301    ignore the return value, and check the value placed in the invalid
 302    argument.  */
 303 #define ARC_OPERAND_FAKE        0x0001
 304
 305 /* This operand names an integer register.  */
 306 #define ARC_OPERAND_IR          0x0002
 307
 308 /* This operand takes signed values.  */
 309 #define ARC_OPERAND_SIGNED      0x0004
 310
 311 /* This operand takes unsigned values.  This exists primarily so that
 312    a flags value of 0 can be treated as end-of-arguments.  */
 313 #define ARC_OPERAND_UNSIGNED    0x0008
 314
 315 /* This operand takes long immediate values.  */
 316 #define ARC_OPERAND_LIMM        0x0010
 317
 318 /* This operand is identical like the previous one.  */
 319 #define ARC_OPERAND_DUPLICATE   0x0020
 320
 321 /* This operand is PC relative.  Used for internal relocs.  */
 322 #define ARC_OPERAND_PCREL       0x0040
 323
 324 /* This operand is truncated.  The truncation is done accordingly to
 325    operand alignment attribute.  */
 326 #define ARC_OPERAND_TRUNCATE    0x0080
 327
 328 /* This operand is 16bit aligned.  */
 329 #define ARC_OPERAND_ALIGNED16   0x0100
 330
 331 /* This operand is 32bit aligned.  */
 332 #define ARC_OPERAND_ALIGNED32   0x0200
 333
 334 /* This operand can be ignored by matching process if it is not
 335    present.  */
 336 #define ARC_OPERAND_IGNORE      0x0400
 337
 338 /* Don't check the range when matching.  */
 339 #define ARC_OPERAND_NCHK        0x0800
 340
 341 /* Mark the braket possition.  */
 342 #define ARC_OPERAND_BRAKET      0x1000
 343
 344 /* Address type operand for NPS400.  */
 345 #define ARC_OPERAND_ADDRTYPE    0x2000
 346
 347 /* Mark the colon position.  */
 348 #define ARC_OPERAND_COLON       0x4000
 349
 350 /* Mask for selecting the type for typecheck purposes.  */
 351 #define ARC_OPERAND_TYPECHECK_MASK               \
 352   (ARC_OPERAND_IR                                \
 353    | ARC_OPERAND_LIMM     | ARC_OPERAND_SIGNED   \
 354    | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET   \
 355    | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
 356
 357 /* Macro to determine if an operand is a fake operand.  */
 358 #define ARC_OPERAND_IS_FAKE(op)                     \
 359   ((operand->flags & ARC_OPERAND_FAKE)              \
 360    && !((operand->flags & ARC_OPERAND_BRAKET)       \
 361         || (operand->flags & ARC_OPERAND_COLON)))
 362
 363 /* The flags structure.  */
 364 struct arc_flag_operand
 365 {
 366   /* The flag name.  */
 367   const char *name;
 368
 369   /* The flag code.  */
 370   unsigned code;
 371
 372   /* The number of bits in the operand.  */
 373   unsigned int bits;
 374
 375   /* How far the operand is left shifted in the instruction.  */
 376   unsigned int shift;
 377
 378   /* Available for disassembler.  */
 379   unsigned char favail;
 380 };
 381
 382 /* The flag operands table.  */
 383 extern const struct arc_flag_operand arc_flag_operands[];
 384 extern const unsigned arc_num_flag_operands;
 385
 386 /* The flag's class structure.  */
 387 struct arc_flag_class
 388 {
 389   /* Flag class.  */
 390   flag_class_t flag_class;
 391
 392   /* List of valid flags (codes).  */
 393   unsigned flags[256];
 394 };
 395
 396 extern const struct arc_flag_class arc_flag_classes[];
 397
 398 /* Structure for special cases.  */
 399 struct arc_flag_special
 400 {
 401   /* Name of special case instruction.  */
 402   const char *name;
 403
 404   /* List of flags applicable for special case instruction.  */
 405   unsigned flags[32];
 406 };
 407
 408 extern const struct arc_flag_special arc_flag_special_cases[];
 409 extern const unsigned arc_num_flag_special;
 410
 411 /* Relocation equivalence structure.  */
 412 struct arc_reloc_equiv_tab
 413 {
 414   const char * name;       /* String to lookup.  */
 415   const char * mnemonic;   /* Extra matching condition.  */
 416   unsigned     flags[32];  /* Extra matching condition.  */
 417   signed int   oldreloc;   /* Old relocation.  */
 418   signed int   newreloc;   /* New relocation.  */
 419 };
 420
 421 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 422 extern const unsigned arc_num_equiv_tab;
 423
 424 /* Structure for operand operations for pseudo/alias instructions.  */
 425 struct arc_operand_operation
 426 {
 427   /* The index for operand from operand array.  */
 428   unsigned operand_idx;
 429
 430   /* Defines if it needs the operand inserted by the assembler or
 431      whether this operand comes from the pseudo instruction's
 432      operands.  */
 433   unsigned char needs_insert;
 434
 435   /* Count we have to add to the operand.  Use negative number to
 436      subtract from the operand.  Also use this number to add to 0 if
 437      the operand needs to be inserted (i.e. needs_insert == 1).  */
 438   int count;
 439
 440   /* Index of the operand to swap with.  To be done AFTER applying
 441      inc_count.  */
 442   unsigned swap_operand_idx;
 443 };
 444
 445 /* Structure for pseudo/alias instructions.  */
 446 struct arc_pseudo_insn
 447 {
 448   /* Mnemonic for pseudo/alias insn.  */
 449   const char *mnemonic_p;
 450
 451   /* Mnemonic for real instruction.  */
 452   const char *mnemonic_r;
 453
 454   /* Flag that will have to be added (if any).  */
 455   const char *flag_r;
 456
 457   /* Amount of operands.  */
 458   unsigned operand_cnt;
 459
 460   /* Array of operand operations.  */
 461   struct arc_operand_operation operand[6];
 462 };
 463
 464 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 465 extern const unsigned arc_num_pseudo_insn;
 466
 467 /* Structure for AUXILIARY registers.  */
 468 struct arc_aux_reg
 469 {
 470   /* Register address.  */
 471   int address;
 472
 473   /* One bit flags for the opcode.  These are primarily used to
 474      indicate specific processors and environments support the
 475      instructions.  */
 476   unsigned cpu;
 477
 478   /* AUX register subclass.  */
 479   insn_subclass_t subclass;
 480
 481   /* Register name.  */
 482   const char *name;
 483
 484   /* Size of the string.  */
 485   size_t length;
 486 };
 487
 488 extern const struct arc_aux_reg arc_aux_regs[];
 489 extern const unsigned arc_num_aux_regs;
 490
 491 extern const struct arc_opcode arc_relax_opcodes[];
 492 extern const unsigned arc_num_relax_opcodes;
 493
 494 /* Macro used for generating one class of NPS instructions.  */
 495 #define NPS_CMEM_HIGH_VALUE 0x57f0
 496
 497 /* Macros to help generating regular pattern instructions.  */
 498 #define FIELDA(word) (word & 0x3F)
 499 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 500 #define FIELDC(word) ((word & 0x3F) << 6)
 501 #define FIELDF       (0x01 << 15)
 502 #define FIELDQ       (0x1F)
 503
 504 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 505 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 506 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 507
 508 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 509 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 510 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 511 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 512 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 513 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 514 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 515 #define INSN3OP_0LL(MOP,SOP)                                    \
 516   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 517 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 518 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 519 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 520 #define INSN3OP_0LU(MOP,SOP)                                    \
 521   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 522 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 523 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 524 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 525 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 526 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 527 #define INSN3OP_C0LL(MOP,SOP)                                   \
 528   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 529 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 530 #define INSN3OP_C0LU(MOP,SOP)                                   \
 531   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 532
 533 #define MINSN3OP_ABC  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 534 #define MINSN3OP_ALC  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 535 #define MINSN3OP_ABL  (~(FIELDF | FIELDA (63) | FIELDB (63)))
 536 #define MINSN3OP_ALL  (~(FIELDF | FIELDA (63)))
 537 #define MINSN3OP_0BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 538 #define MINSN3OP_0LC  (~(FIELDF | FIELDC (63)))
 539 #define MINSN3OP_0BL  (~(FIELDF | FIELDB (63)))
 540 #define MINSN3OP_0LL  (~(FIELDF))
 541 #define MINSN3OP_ABU  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 542 #define MINSN3OP_ALU  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 543 #define MINSN3OP_0BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 544 #define MINSN3OP_0LU  (~(FIELDF | FIELDC (63)))
 545 #define MINSN3OP_BBS  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 546 #define MINSN3OP_0LS  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 547 #define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 548 #define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
 549 #define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
 550 #define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
 551 #define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 552 #define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
 553
 554 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 555 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 556 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 557 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 558 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 559 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 560
 561 #define MINSN2OP_BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 562 #define MINSN2OP_BL  (~(FIELDF | FIELDB (63)))
 563 #define MINSN2OP_0C  (~(FIELDF | FIELDC (63)))
 564 #define MINSN2OP_0L  (~(FIELDF))
 565 #define MINSN2OP_BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 566 #define MINSN2OP_0U  (~(FIELDF | FIELDC (63)))
 567
 568 /* Various constants used when defining an extension instruction.  */
 569 #define ARC_SYNTAX_3OP          (1 << 0)
 570 #define ARC_SYNTAX_2OP          (1 << 1)
 571 #define ARC_SYNTAX_1OP          (1 << 2)
 572 #define ARC_SYNTAX_NOP          (1 << 3)
 573 #define ARC_SYNTAX_MASK         (0x0F)
 574
 575 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 576 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 577
 578 #define ARC_SUFFIX_NONE         (1 << 0)
 579 #define ARC_SUFFIX_COND         (1 << 1)
 580 #define ARC_SUFFIX_FLAG         (1 << 2)
 581
 582 #define ARC_REGISTER_READONLY    (1 << 0)
 583 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 584 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 585
 586 /* Constants needed to initialize extension instructions.  */
 587 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 588 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 589 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 590 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 591
 592 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 593 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 594 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 595 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 596 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 597 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 598 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 599 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 600 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 601 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 602 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 604
 605 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 606 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 607 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 608
 609 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 610 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 611 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 612
 613 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 614 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 615 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 616 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 617 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 618 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 619
 620 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 621 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 622 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 623 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 624
 625 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 626 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 627 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 628
 629 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
 630    Instruction Set Reference Manual v2.4 for a description of address types.  */
 631
 632 typedef enum
 633 {
 634   /* Addresses in memory.  */
 635
 636   /* Buffer descriptor.  */
 637   ARC_NPS400_ADDRTYPE_BD,
 638
 639   /* Job identifier.  */
 640   ARC_NPS400_ADDRTYPE_JID,
 641
 642   /* Linked Buffer Descriptor.  */
 643   ARC_NPS400_ADDRTYPE_LBD,
 644
 645   /* Multicast Buffer Descriptor.  */
 646   ARC_NPS400_ADDRTYPE_MBD,
 647
 648   /* Summarized Address.  */
 649   ARC_NPS400_ADDRTYPE_SD,
 650
 651   /* SMEM Security Context Local Memory.  */
 652   ARC_NPS400_ADDRTYPE_SM,
 653
 654   /* Extended Address.  */
 655   ARC_NPS400_ADDRTYPE_XA,
 656
 657   /* Extended Summarized Address.  */
 658   ARC_NPS400_ADDRTYPE_XD,
 659
 660   /* CMEM offset addresses.  */
 661
 662   /* On-demand Counter Descriptor.  */
 663   ARC_NPS400_ADDRTYPE_CD,
 664
 665   /* CMEM Buffer Descriptor.  */
 666   ARC_NPS400_ADDRTYPE_CBD,
 667
 668   /* CMEM Job Identifier.  */
 669   ARC_NPS400_ADDRTYPE_CJID,
 670
 671   /* CMEM Linked Buffer Descriptor.  */
 672   ARC_NPS400_ADDRTYPE_CLBD,
 673
 674   /* CMEM Offset.  */
 675   ARC_NPS400_ADDRTYPE_CM,
 676
 677   /* CMEM Summarized Address.  */
 678   ARC_NPS400_ADDRTYPE_CSD,
 679
 680   /* CMEM Extended Address.  */
 681   ARC_NPS400_ADDRTYPE_CXA,
 682
 683   /* CMEM Extended Summarized Address.  */
 684   ARC_NPS400_ADDRTYPE_CXD
 685
 686 } arc_nps_address_type;
 687
 688 #define ARC_NUM_ADDRTYPES 16
 689
 690 #ifdef __cplusplus
 691 }
 692 #endif
 693
 694 #endif /* OPCODE_ARC_H */