1 /* ARM assembler/disassembler support.
2 Copyright 2004 Free Software Foundation, Inc.
4 This file is part of GDB and GAS.
6 GDB and GAS are free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
8 published by the Free Software Foundation; either version 1, or (at
9 your option) any later version.
11 GDB and GAS are distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GDB or GAS; see the file COPYING. If not, write to the
18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* The following bitmasks control CPU extensions: */
22 #define ARM_EXT_V1 0x00000001 /* All processors (core set). */
23 #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
24 #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
25 #define ARM_EXT_V3 0x00000008 /* MSR MRS. */
26 #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
27 #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
28 #define ARM_EXT_V4T 0x00000040 /* Thumb. */
29 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
30 #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
31 #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
32 #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
33 #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
34 #define ARM_EXT_V6 0x00001000 /* ARM V6. */
35 #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
36 #define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
37 #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
38 #define ARM_EXT_DIV 0x00010000 /* Integer division. */
39 /* The 'M' in Arm V7M stands for Microcontroller.
40 On earlier architecture variants it stands for Multiply. */
41 #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
42 #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
43 #define ARM_EXT_V7 0x00080000 /* Arm V7. */
44 #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
45 #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
46 #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
47 #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
48 #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
49 #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
51 /* Co-processor space extensions. */
52 #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
53 #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
54 #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
55 #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
57 #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
58 #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
59 #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
60 #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
61 #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
62 #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
63 #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
64 #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
65 #define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */
66 #define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */
67 #define FPU_VFP_EXT_D32 0x00400000 /* Registers D16-D31. */
68 #define FPU_NEON_FP16 0x00200000 /* Half-precision extensions. */
70 /* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
71 defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
72 ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
73 three more to cover cores prior to ARM6. Finally, there are cores which
74 implement further extensions in the co-processor space. */
75 #define ARM_AEXT_V1 ARM_EXT_V1
76 #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2)
77 #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S)
78 #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3)
79 #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M)
80 #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4)
81 #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4)
82 #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T)
83 #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T)
84 #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5)
85 #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5)
86 #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
87 #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
88 #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP)
89 #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E)
90 #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
91 #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
92 #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
93 #define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z)
94 #define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
95 #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
96 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR)
97 #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
98 #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z)
99 #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
100 #define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
101 #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
102 #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
103 #define ARM_AEXT_NOTM \
104 (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM)
105 #define ARM_AEXT_V6M \
106 ((ARM_AEXT_V6K | ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) \
108 #define ARM_AEXT_V7M \
109 ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
111 #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
113 /* Processors with specific extensions in the co-processor space. */
114 #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
115 #define ARM_ARCH_IWMMXT \
116 ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
117 #define ARM_ARCH_IWMMXT2 \
118 ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)
120 #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
121 #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
122 #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
123 #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3)
124 #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
125 #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
126 | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
127 #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
130 #define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
132 #define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
133 #define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
135 #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
136 #define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
137 #define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
138 #define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
139 #define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
140 #define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
141 #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
142 ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
143 #define FPU_ARCH_NEON_FP16 \
144 ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_NEON_FP16)
145 #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
147 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
149 #define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
151 #define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
152 #define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
153 #define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
154 #define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
155 #define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
156 #define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
157 #define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
158 #define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
159 #define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
160 #define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
161 #define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
162 #define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
163 #define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
164 #define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
165 #define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
166 #define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
167 #define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
168 #define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
169 #define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
170 #define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
171 #define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
172 #define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
173 #define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
174 #define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
175 #define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
176 #define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
177 #define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
178 #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
179 #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
181 /* Some useful combinations: */
182 #define ARM_ARCH_NONE ARM_FEATURE (0, 0)
183 #define FPU_NONE ARM_FEATURE (0, 0)
184 #define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
185 #define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
186 #define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
188 /* There are too many feature bits to fit in a single word, so use a
189 structure. For simplicity we put all core features in one word and
190 everything else in the other. */
194 unsigned long coproc
;
197 #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
198 (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
200 #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
202 (TARG).core = (F1).core | (F2).core; \
203 (TARG).coproc = (F1).coproc | (F2).coproc; \
206 #define ARM_CLEAR_FEATURE(TARG,F1,F2) \
208 (TARG).core = (F1).core &~ (F2).core; \
209 (TARG).coproc = (F1).coproc &~ (F2).coproc; \
212 #define ARM_FEATURE(core, coproc) {(core), (coproc)}
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