1 /* bfin.h -- Header file for ADI Blackfin opcode table
2 Copyright 2005 Free Software Foundation, Inc.
4 This file is part of GDB, GAS, and the GNU binutils.
6 GDB, GAS, and the GNU binutils are free software; you can redistribute
7 them and/or modify them under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either version
9 1, or (at your option) any later version.
11 GDB, GAS, and the GNU binutils are distributed in the hope that they
12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 the GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20 /* Common to all DSP32 instructions. */
21 #define BIT_MULTI_INS 0x0800
23 /* This just sets the multi instruction bit of a DSP32 instruction. */
24 #define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS;
27 /* DSP instructions (32 bit) */
30 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
31 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
32 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
33 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
75 #define DSP32Mac_opcode 0xc0000000
76 #define DSP32Mac_src1_bits 0
77 #define DSP32Mac_src1_mask 0x7
78 #define DSP32Mac_src0_bits 3
79 #define DSP32Mac_src0_mask 0x7
80 #define DSP32Mac_dst_bits 6
81 #define DSP32Mac_dst_mask 0x7
82 #define DSP32Mac_h10_bits 9
83 #define DSP32Mac_h10_mask 0x1
84 #define DSP32Mac_h00_bits 10
85 #define DSP32Mac_h00_mask 0x1
86 #define DSP32Mac_op0_bits 11
87 #define DSP32Mac_op0_mask 0x3
88 #define DSP32Mac_w0_bits 13
89 #define DSP32Mac_w0_mask 0x1
90 #define DSP32Mac_h11_bits 14
91 #define DSP32Mac_h11_mask 0x1
92 #define DSP32Mac_h01_bits 15
93 #define DSP32Mac_h01_mask 0x1
94 #define DSP32Mac_op1_bits 16
95 #define DSP32Mac_op1_mask 0x3
96 #define DSP32Mac_w1_bits 18
97 #define DSP32Mac_w1_mask 0x1
98 #define DSP32Mac_p_bits 19
99 #define DSP32Mac_p_mask 0x1
100 #define DSP32Mac_MM_bits 20
101 #define DSP32Mac_MM_mask 0x1
102 #define DSP32Mac_mmod_bits 21
103 #define DSP32Mac_mmod_mask 0xf
104 #define DSP32Mac_code2_bits 25
105 #define DSP32Mac_code2_mask 0x3
106 #define DSP32Mac_M_bits 27
107 #define DSP32Mac_M_mask 0x1
108 #define DSP32Mac_code_bits 28
109 #define DSP32Mac_code_mask 0xf
111 #define init_DSP32Mac \
114 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
115 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
116 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
117 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
118 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
119 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
120 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
121 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
122 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
123 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
124 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
125 DSP32Mac_p_bits, DSP32Mac_p_mask, \
126 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
127 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
128 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
129 DSP32Mac_M_bits, DSP32Mac_M_mask, \
130 DSP32Mac_code_bits, DSP32Mac_code_mask \
134 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
135 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
136 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
137 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
140 typedef DSP32Mac DSP32Mult
;
141 #define DSP32Mult_opcode 0xc2000000
143 #define init_DSP32Mult \
146 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
147 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
148 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
149 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
150 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
151 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
152 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
153 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
154 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
155 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
156 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
157 DSP32Mac_p_bits, DSP32Mac_p_mask, \
158 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
159 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
160 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
161 DSP32Mac_M_bits, DSP32Mac_M_mask, \
162 DSP32Mac_code_bits, DSP32Mac_code_mask \
166 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
167 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
168 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
169 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
174 unsigned long opcode
;
203 #define DSP32Alu_opcode 0xc4000000
204 #define DSP32Alu_src1_bits 0
205 #define DSP32Alu_src1_mask 0x7
206 #define DSP32Alu_src0_bits 3
207 #define DSP32Alu_src0_mask 0x7
208 #define DSP32Alu_dst1_bits 6
209 #define DSP32Alu_dst1_mask 0x7
210 #define DSP32Alu_dst0_bits 9
211 #define DSP32Alu_dst0_mask 0x7
212 #define DSP32Alu_x_bits 12
213 #define DSP32Alu_x_mask 0x1
214 #define DSP32Alu_s_bits 13
215 #define DSP32Alu_s_mask 0x1
216 #define DSP32Alu_aop_bits 14
217 #define DSP32Alu_aop_mask 0x3
218 #define DSP32Alu_aopcde_bits 16
219 #define DSP32Alu_aopcde_mask 0x1f
220 #define DSP32Alu_HL_bits 21
221 #define DSP32Alu_HL_mask 0x1
222 #define DSP32Alu_dontcare_bits 22
223 #define DSP32Alu_dontcare_mask 0x7
224 #define DSP32Alu_code2_bits 25
225 #define DSP32Alu_code2_mask 0x3
226 #define DSP32Alu_M_bits 27
227 #define DSP32Alu_M_mask 0x1
228 #define DSP32Alu_code_bits 28
229 #define DSP32Alu_code_mask 0xf
231 #define init_DSP32Alu \
234 DSP32Alu_src1_bits, DSP32Alu_src1_mask, \
235 DSP32Alu_src0_bits, DSP32Alu_src0_mask, \
236 DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \
237 DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \
238 DSP32Alu_x_bits, DSP32Alu_x_mask, \
239 DSP32Alu_s_bits, DSP32Alu_s_mask, \
240 DSP32Alu_aop_bits, DSP32Alu_aop_mask, \
241 DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \
242 DSP32Alu_HL_bits, DSP32Alu_HL_mask, \
243 DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \
244 DSP32Alu_code2_bits, DSP32Alu_code2_mask, \
245 DSP32Alu_M_bits, DSP32Alu_M_mask, \
246 DSP32Alu_code_bits, DSP32Alu_code_mask \
250 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
251 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
252 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
253 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
258 unsigned long opcode
;
283 #define DSP32Shift_opcode 0xc6000000
284 #define DSP32Shift_src1_bits 0
285 #define DSP32Shift_src1_mask 0x7
286 #define DSP32Shift_src0_bits 3
287 #define DSP32Shift_src0_mask 0x7
288 #define DSP32Shift_dst1_bits 6
289 #define DSP32Shift_dst1_mask 0x7
290 #define DSP32Shift_dst0_bits 9
291 #define DSP32Shift_dst0_mask 0x7
292 #define DSP32Shift_HLs_bits 12
293 #define DSP32Shift_HLs_mask 0x3
294 #define DSP32Shift_sop_bits 14
295 #define DSP32Shift_sop_mask 0x3
296 #define DSP32Shift_sopcde_bits 16
297 #define DSP32Shift_sopcde_mask 0x1f
298 #define DSP32Shift_dontcare_bits 21
299 #define DSP32Shift_dontcare_mask 0x3
300 #define DSP32Shift_code2_bits 23
301 #define DSP32Shift_code2_mask 0xf
302 #define DSP32Shift_M_bits 27
303 #define DSP32Shift_M_mask 0x1
304 #define DSP32Shift_code_bits 28
305 #define DSP32Shift_code_mask 0xf
307 #define init_DSP32Shift \
310 DSP32Shift_src1_bits, DSP32Shift_src1_mask, \
311 DSP32Shift_src0_bits, DSP32Shift_src0_mask, \
312 DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \
313 DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \
314 DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \
315 DSP32Shift_sop_bits, DSP32Shift_sop_mask, \
316 DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \
317 DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \
318 DSP32Shift_code2_bits, DSP32Shift_code2_mask, \
319 DSP32Shift_M_bits, DSP32Shift_M_mask, \
320 DSP32Shift_code_bits, DSP32Shift_code_mask \
324 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
325 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
326 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
327 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
332 unsigned long opcode
;
355 #define DSP32ShiftImm_opcode 0xc6800000
356 #define DSP32ShiftImm_src1_bits 0
357 #define DSP32ShiftImm_src1_mask 0x7
358 #define DSP32ShiftImm_immag_bits 3
359 #define DSP32ShiftImm_immag_mask 0x3f
360 #define DSP32ShiftImm_dst0_bits 9
361 #define DSP32ShiftImm_dst0_mask 0x7
362 #define DSP32ShiftImm_HLs_bits 12
363 #define DSP32ShiftImm_HLs_mask 0x3
364 #define DSP32ShiftImm_sop_bits 14
365 #define DSP32ShiftImm_sop_mask 0x3
366 #define DSP32ShiftImm_sopcde_bits 16
367 #define DSP32ShiftImm_sopcde_mask 0x1f
368 #define DSP32ShiftImm_dontcare_bits 21
369 #define DSP32ShiftImm_dontcare_mask 0x3
370 #define DSP32ShiftImm_code2_bits 23
371 #define DSP32ShiftImm_code2_mask 0xf
372 #define DSP32ShiftImm_M_bits 27
373 #define DSP32ShiftImm_M_mask 0x1
374 #define DSP32ShiftImm_code_bits 28
375 #define DSP32ShiftImm_code_mask 0xf
377 #define init_DSP32ShiftImm \
379 DSP32ShiftImm_opcode, \
380 DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \
381 DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \
382 DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \
383 DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \
384 DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \
385 DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \
386 DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \
387 DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \
388 DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \
389 DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \
395 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
396 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
397 |.offset........................................................|
398 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
403 unsigned long opcode
;
420 #define LDSTidxI_opcode 0xe4000000
421 #define LDSTidxI_offset_bits 0
422 #define LDSTidxI_offset_mask 0xffff
423 #define LDSTidxI_reg_bits 16
424 #define LDSTidxI_reg_mask 0x7
425 #define LDSTidxI_ptr_bits 19
426 #define LDSTidxI_ptr_mask 0x7
427 #define LDSTidxI_sz_bits 22
428 #define LDSTidxI_sz_mask 0x3
429 #define LDSTidxI_Z_bits 24
430 #define LDSTidxI_Z_mask 0x1
431 #define LDSTidxI_W_bits 25
432 #define LDSTidxI_W_mask 0x1
433 #define LDSTidxI_code_bits 26
434 #define LDSTidxI_code_mask 0x3f
436 #define init_LDSTidxI \
439 LDSTidxI_offset_bits, LDSTidxI_offset_mask, \
440 LDSTidxI_reg_bits, LDSTidxI_reg_mask, \
441 LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \
442 LDSTidxI_sz_bits, LDSTidxI_sz_mask, \
443 LDSTidxI_Z_bits, LDSTidxI_Z_mask, \
444 LDSTidxI_W_bits, LDSTidxI_W_mask, \
445 LDSTidxI_code_bits, LDSTidxI_code_mask \
450 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
451 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
452 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
457 unsigned short opcode
;
474 #define LDST_opcode 0x9000
475 #define LDST_reg_bits 0
476 #define LDST_reg_mask 0x7
477 #define LDST_ptr_bits 3
478 #define LDST_ptr_mask 0x7
479 #define LDST_Z_bits 6
480 #define LDST_Z_mask 0x1
481 #define LDST_aop_bits 7
482 #define LDST_aop_mask 0x3
483 #define LDST_W_bits 9
484 #define LDST_W_mask 0x1
485 #define LDST_sz_bits 10
486 #define LDST_sz_mask 0x3
487 #define LDST_code_bits 12
488 #define LDST_code_mask 0xf
493 LDST_reg_bits, LDST_reg_mask, \
494 LDST_ptr_bits, LDST_ptr_mask, \
495 LDST_Z_bits, LDST_Z_mask, \
496 LDST_aop_bits, LDST_aop_mask, \
497 LDST_W_bits, LDST_W_mask, \
498 LDST_sz_bits, LDST_sz_mask, \
499 LDST_code_bits, LDST_code_mask \
503 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
504 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
505 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
510 unsigned short opcode
;
525 #define LDSTii_opcode 0xa000
526 #define LDSTii_reg_bit 0
527 #define LDSTii_reg_mask 0x7
528 #define LDSTii_ptr_bit 3
529 #define LDSTii_ptr_mask 0x7
530 #define LDSTii_offset_bit 6
531 #define LDSTii_offset_mask 0xf
532 #define LDSTii_op_bit 10
533 #define LDSTii_op_mask 0x3
534 #define LDSTii_W_bit 12
535 #define LDSTii_W_mask 0x1
536 #define LDSTii_code_bit 13
537 #define LDSTii_code_mask 0x7
539 #define init_LDSTii \
542 LDSTii_reg_bit, LDSTii_reg_mask, \
543 LDSTii_ptr_bit, LDSTii_ptr_mask, \
544 LDSTii_offset_bit, LDSTii_offset_mask, \
545 LDSTii_op_bit, LDSTii_op_mask, \
546 LDSTii_W_bit, LDSTii_W_mask, \
547 LDSTii_code_bit, LDSTii_code_mask \
552 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
553 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
554 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
559 unsigned short opcode
;
570 #define LDSTiiFP_opcode 0xb800
571 #define LDSTiiFP_reg_bits 0
572 #define LDSTiiFP_reg_mask 0xf
573 #define LDSTiiFP_offset_bits 4
574 #define LDSTiiFP_offset_mask 0x1f
575 #define LDSTiiFP_W_bits 9
576 #define LDSTiiFP_W_mask 0x1
577 #define LDSTiiFP_code_bits 10
578 #define LDSTiiFP_code_mask 0x3f
580 #define init_LDSTiiFP \
583 LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \
584 LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \
585 LDSTiiFP_W_bits, LDSTiiFP_W_mask, \
586 LDSTiiFP_code_bits, LDSTiiFP_code_mask \
590 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
591 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
592 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
597 unsigned short opcode
;
612 #define DspLDST_opcode 0x9c00
613 #define DspLDST_reg_bits 0
614 #define DspLDST_reg_mask 0x7
615 #define DspLDST_i_bits 3
616 #define DspLDST_i_mask 0x3
617 #define DspLDST_m_bits 5
618 #define DspLDST_m_mask 0x3
619 #define DspLDST_aop_bits 7
620 #define DspLDST_aop_mask 0x3
621 #define DspLDST_W_bits 9
622 #define DspLDST_W_mask 0x1
623 #define DspLDST_code_bits 10
624 #define DspLDST_code_mask 0x3f
626 #define init_DspLDST \
629 DspLDST_reg_bits, DspLDST_reg_mask, \
630 DspLDST_i_bits, DspLDST_i_mask, \
631 DspLDST_m_bits, DspLDST_m_mask, \
632 DspLDST_aop_bits, DspLDST_aop_mask, \
633 DspLDST_W_bits, DspLDST_W_mask, \
634 DspLDST_code_bits, DspLDST_code_mask \
639 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
640 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
641 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
646 unsigned short opcode
;
661 #define LDSTpmod_opcode 0x8000
662 #define LDSTpmod_ptr_bits 0
663 #define LDSTpmod_ptr_mask 0x7
664 #define LDSTpmod_idx_bits 3
665 #define LDSTpmod_idx_mask 0x7
666 #define LDSTpmod_reg_bits 6
667 #define LDSTpmod_reg_mask 0x7
668 #define LDSTpmod_aop_bits 9
669 #define LDSTpmod_aop_mask 0x3
670 #define LDSTpmod_W_bits 11
671 #define LDSTpmod_W_mask 0x1
672 #define LDSTpmod_code_bits 12
673 #define LDSTpmod_code_mask 0xf
675 #define init_LDSTpmod \
678 LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \
679 LDSTpmod_idx_bits, LDSTpmod_idx_mask, \
680 LDSTpmod_reg_bits, LDSTpmod_reg_mask, \
681 LDSTpmod_aop_bits, LDSTpmod_aop_mask, \
682 LDSTpmod_W_bits, LDSTpmod_W_mask, \
683 LDSTpmod_code_bits, LDSTpmod_code_mask \
688 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
689 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
690 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
695 unsigned short opcode
;
706 #define LOGI2op_opcode 0x4800
707 #define LOGI2op_dst_bits 0
708 #define LOGI2op_dst_mask 0x7
709 #define LOGI2op_src_bits 3
710 #define LOGI2op_src_mask 0x1f
711 #define LOGI2op_opc_bits 8
712 #define LOGI2op_opc_mask 0x7
713 #define LOGI2op_code_bits 11
714 #define LOGI2op_code_mask 0x1f
716 #define init_LOGI2op \
719 LOGI2op_dst_bits, LOGI2op_dst_mask, \
720 LOGI2op_src_bits, LOGI2op_src_mask, \
721 LOGI2op_opc_bits, LOGI2op_opc_mask, \
722 LOGI2op_code_bits, LOGI2op_code_mask \
727 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
728 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
729 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
734 unsigned short opcode
;
745 #define ALU2op_opcode 0x4000
746 #define ALU2op_dst_bits 0
747 #define ALU2op_dst_mask 0x7
748 #define ALU2op_src_bits 3
749 #define ALU2op_src_mask 0x7
750 #define ALU2op_opc_bits 6
751 #define ALU2op_opc_mask 0xf
752 #define ALU2op_code_bits 10
753 #define ALU2op_code_mask 0x3f
755 #define init_ALU2op \
758 ALU2op_dst_bits, ALU2op_dst_mask, \
759 ALU2op_src_bits, ALU2op_src_mask, \
760 ALU2op_opc_bits, ALU2op_opc_mask, \
761 ALU2op_code_bits, ALU2op_code_mask \
766 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
767 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
768 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
773 unsigned short opcode
;
784 #define BRCC_opcode 0x1000
785 #define BRCC_offset_bits 0
786 #define BRCC_offset_mask 0x3ff
787 #define BRCC_B_bits 10
788 #define BRCC_B_mask 0x1
789 #define BRCC_T_bits 11
790 #define BRCC_T_mask 0x1
791 #define BRCC_code_bits 12
792 #define BRCC_code_mask 0xf
797 BRCC_offset_bits, BRCC_offset_mask, \
798 BRCC_B_bits, BRCC_B_mask, \
799 BRCC_T_bits, BRCC_T_mask, \
800 BRCC_code_bits, BRCC_code_mask \
805 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
806 | 0 | 0 | 1 | 0 |.offset........................................|
807 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
812 unsigned short opcode
;
819 #define UJump_opcode 0x2000
820 #define UJump_offset_bits 0
821 #define UJump_offset_mask 0xfff
822 #define UJump_code_bits 12
823 #define UJump_code_mask 0xf
828 UJump_offset_bits, UJump_offset_mask, \
829 UJump_code_bits, UJump_code_mask \
834 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
835 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
836 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
841 unsigned short opcode
;
850 #define ProgCtrl_opcode 0x0000
851 #define ProgCtrl_poprnd_bits 0
852 #define ProgCtrl_poprnd_mask 0xf
853 #define ProgCtrl_prgfunc_bits 4
854 #define ProgCtrl_prgfunc_mask 0xf
855 #define ProgCtrl_code_bits 8
856 #define ProgCtrl_code_mask 0xff
858 #define init_ProgCtrl \
861 ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \
862 ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \
863 ProgCtrl_code_bits, ProgCtrl_code_mask \
867 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
868 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
869 |.lsw...........................................................|
870 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
876 unsigned long opcode
;
885 #define CALLa_opcode 0xe2000000
886 #define CALLa_addr_bits 0
887 #define CALLa_addr_mask 0xffffff
888 #define CALLa_S_bits 24
889 #define CALLa_S_mask 0x1
890 #define CALLa_code_bits 25
891 #define CALLa_code_mask 0x7f
896 CALLa_addr_bits, CALLa_addr_mask, \
897 CALLa_S_bits, CALLa_S_mask, \
898 CALLa_code_bits, CALLa_code_mask \
903 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
904 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
905 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
910 unsigned short opcode
;
921 #define PseudoDbg_opcode 0xf800
922 #define PseudoDbg_reg_bits 0
923 #define PseudoDbg_reg_mask 0x7
924 #define PseudoDbg_grp_bits 3
925 #define PseudoDbg_grp_mask 0x7
926 #define PseudoDbg_fn_bits 6
927 #define PseudoDbg_fn_mask 0x3
928 #define PseudoDbg_code_bits 8
929 #define PseudoDbg_code_mask 0xff
931 #define init_PseudoDbg \
934 PseudoDbg_reg_bits, PseudoDbg_reg_mask, \
935 PseudoDbg_grp_bits, PseudoDbg_grp_mask, \
936 PseudoDbg_fn_bits, PseudoDbg_fn_mask, \
937 PseudoDbg_code_bits, PseudoDbg_code_mask \
941 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
942 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
943 |.expected......................................................|
944 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
949 unsigned long opcode
;
964 #define PseudoDbg_Assert_opcode 0xf0000000
965 #define PseudoDbg_Assert_expected_bits 0
966 #define PseudoDbg_Assert_expected_mask 0xffff
967 #define PseudoDbg_Assert_regtest_bits 16
968 #define PseudoDbg_Assert_regtest_mask 0x7
969 #define PseudoDbg_Assert_grp_bits 19
970 #define PseudoDbg_Assert_grp_mask 0x7
971 #define PseudoDbg_Assert_dbgop_bits 22
972 #define PseudoDbg_Assert_dbgop_mask 0x3
973 #define PseudoDbg_Assert_dontcare_bits 24
974 #define PseudoDbg_Assert_dontcare_mask 0x7
975 #define PseudoDbg_Assert_code_bits 27
976 #define PseudoDbg_Assert_code_mask 0x1f
978 #define init_PseudoDbg_Assert \
980 PseudoDbg_Assert_opcode, \
981 PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
982 PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
983 PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
984 PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
985 PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
986 PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
990 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
991 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
992 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
997 unsigned short opcode
;
1008 #define CaCTRL_opcode 0x0240
1009 #define CaCTRL_reg_bits 0
1010 #define CaCTRL_reg_mask 0x7
1011 #define CaCTRL_op_bits 3
1012 #define CaCTRL_op_mask 0x3
1013 #define CaCTRL_a_bits 5
1014 #define CaCTRL_a_mask 0x1
1015 #define CaCTRL_code_bits 6
1016 #define CaCTRL_code_mask 0x3fff
1018 #define init_CaCTRL \
1021 CaCTRL_reg_bits, CaCTRL_reg_mask, \
1022 CaCTRL_op_bits, CaCTRL_op_mask, \
1023 CaCTRL_a_bits, CaCTRL_a_mask, \
1024 CaCTRL_code_bits, CaCTRL_code_mask \
1028 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1029 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
1030 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1035 unsigned short opcode
;
1050 #define PushPopMultiple_opcode 0x0400
1051 #define PushPopMultiple_pr_bits 0
1052 #define PushPopMultiple_pr_mask 0x7
1053 #define PushPopMultiple_dr_bits 3
1054 #define PushPopMultiple_dr_mask 0x7
1055 #define PushPopMultiple_W_bits 6
1056 #define PushPopMultiple_W_mask 0x1
1057 #define PushPopMultiple_p_bits 7
1058 #define PushPopMultiple_p_mask 0x1
1059 #define PushPopMultiple_d_bits 8
1060 #define PushPopMultiple_d_mask 0x1
1061 #define PushPopMultiple_code_bits 8
1062 #define PushPopMultiple_code_mask 0x1
1064 #define init_PushPopMultiple \
1066 PushPopMultiple_opcode, \
1067 PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \
1068 PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \
1069 PushPopMultiple_W_bits, PushPopMultiple_W_mask, \
1070 PushPopMultiple_p_bits, PushPopMultiple_p_mask, \
1071 PushPopMultiple_d_bits, PushPopMultiple_d_mask, \
1072 PushPopMultiple_code_bits, PushPopMultiple_code_mask \
1076 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1077 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
1078 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1083 unsigned short opcode
;
1094 #define PushPopReg_opcode 0x0100
1095 #define PushPopReg_reg_bits 0
1096 #define PushPopReg_reg_mask 0x7
1097 #define PushPopReg_grp_bits 3
1098 #define PushPopReg_grp_mask 0x7
1099 #define PushPopReg_W_bits 6
1100 #define PushPopReg_W_mask 0x1
1101 #define PushPopReg_code_bits 7
1102 #define PushPopReg_code_mask 0x1ff
1104 #define init_PushPopReg \
1106 PushPopReg_opcode, \
1107 PushPopReg_reg_bits, PushPopReg_reg_mask, \
1108 PushPopReg_grp_bits, PushPopReg_grp_mask, \
1109 PushPopReg_W_bits, PushPopReg_W_mask, \
1110 PushPopReg_code_bits, PushPopReg_code_mask, \
1114 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1115 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
1116 |.framesize.....................................................|
1117 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1122 unsigned long opcode
;
1131 #define Linkage_opcode 0xe8000000
1132 #define Linkage_framesize_bits 0
1133 #define Linkage_framesize_mask 0xffff
1134 #define Linkage_R_bits 16
1135 #define Linkage_R_mask 0x1
1136 #define Linkage_code_bits 17
1137 #define Linkage_code_mask 0x7fff
1139 #define init_Linkage \
1142 Linkage_framesize_bits, Linkage_framesize_mask, \
1143 Linkage_R_bits, Linkage_R_mask, \
1144 Linkage_code_bits, Linkage_code_mask \
1148 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1149 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
1150 |.reg...........| - | - |.eoffset...............................|
1151 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1156 unsigned long opcode
;
1173 #define LoopSetup_opcode 0xe0800000
1174 #define LoopSetup_eoffset_bits 0
1175 #define LoopSetup_eoffset_mask 0x3ff
1176 #define LoopSetup_dontcare_bits 10
1177 #define LoopSetup_dontcare_mask 0x3
1178 #define LoopSetup_reg_bits 12
1179 #define LoopSetup_reg_mask 0xf
1180 #define LoopSetup_soffset_bits 16
1181 #define LoopSetup_soffset_mask 0xf
1182 #define LoopSetup_c_bits 20
1183 #define LoopSetup_c_mask 0x1
1184 #define LoopSetup_rop_bits 21
1185 #define LoopSetup_rop_mask 0x3
1186 #define LoopSetup_code_bits 23
1187 #define LoopSetup_code_mask 0x1ff
1189 #define init_LoopSetup \
1192 LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \
1193 LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \
1194 LoopSetup_reg_bits, LoopSetup_reg_mask, \
1195 LoopSetup_soffset_bits, LoopSetup_soffset_mask, \
1196 LoopSetup_c_bits, LoopSetup_c_mask, \
1197 LoopSetup_rop_bits, LoopSetup_rop_mask, \
1198 LoopSetup_code_bits, LoopSetup_code_mask \
1202 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1203 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
1204 |.hword.........................................................|
1205 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1210 unsigned long opcode
;
1227 #define LDIMMhalf_opcode 0xe1000000
1228 #define LDIMMhalf_hword_bits 0
1229 #define LDIMMhalf_hword_mask 0xffff
1230 #define LDIMMhalf_reg_bits 16
1231 #define LDIMMhalf_reg_mask 0x7
1232 #define LDIMMhalf_grp_bits 19
1233 #define LDIMMhalf_grp_mask 0x3
1234 #define LDIMMhalf_S_bits 21
1235 #define LDIMMhalf_S_mask 0x1
1236 #define LDIMMhalf_H_bits 22
1237 #define LDIMMhalf_H_mask 0x1
1238 #define LDIMMhalf_Z_bits 23
1239 #define LDIMMhalf_Z_mask 0x1
1240 #define LDIMMhalf_code_bits 24
1241 #define LDIMMhalf_code_mask 0xff
1243 #define init_LDIMMhalf \
1246 LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \
1247 LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \
1248 LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \
1249 LDIMMhalf_S_bits, LDIMMhalf_S_mask, \
1250 LDIMMhalf_H_bits, LDIMMhalf_H_mask, \
1251 LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \
1252 LDIMMhalf_code_bits, LDIMMhalf_code_mask \
1257 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1258 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1259 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1264 unsigned short opcode
;
1273 #define CC2dreg_opcode 0x0200
1274 #define CC2dreg_reg_bits 0
1275 #define CC2dreg_reg_mask 0x7
1276 #define CC2dreg_op_bits 3
1277 #define CC2dreg_op_mask 0x3
1278 #define CC2dreg_code_bits 5
1279 #define CC2dreg_code_mask 0x7fff
1281 #define init_CC2dreg \
1284 CC2dreg_reg_bits, CC2dreg_reg_mask, \
1285 CC2dreg_op_bits, CC2dreg_op_mask, \
1286 CC2dreg_code_bits, CC2dreg_code_mask \
1291 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1292 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1293 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1298 unsigned short opcode
;
1309 #define PTR2op_opcode 0x4400
1310 #define PTR2op_dst_bits 0
1311 #define PTR2op_dst_mask 0x7
1312 #define PTR2op_src_bits 3
1313 #define PTR2op_src_mask 0x7
1314 #define PTR2op_opc_bits 6
1315 #define PTR2op_opc_mask 0x7
1316 #define PTR2op_code_bits 9
1317 #define PTR2op_code_mask 0x7f
1319 #define init_PTR2op \
1322 PTR2op_dst_bits, PTR2op_dst_mask, \
1323 PTR2op_src_bits, PTR2op_src_mask, \
1324 PTR2op_opc_bits, PTR2op_opc_mask, \
1325 PTR2op_code_bits, PTR2op_code_mask \
1330 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1331 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1332 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1337 unsigned short opcode
;
1350 #define COMP3op_opcode 0x5000
1351 #define COMP3op_src0_bits 0
1352 #define COMP3op_src0_mask 0x7
1353 #define COMP3op_src1_bits 3
1354 #define COMP3op_src1_mask 0x7
1355 #define COMP3op_dst_bits 6
1356 #define COMP3op_dst_mask 0x7
1357 #define COMP3op_opc_bits 9
1358 #define COMP3op_opc_mask 0x7
1359 #define COMP3op_code_bits 12
1360 #define COMP3op_code_mask 0xf
1362 #define init_COMP3op \
1365 COMP3op_src0_bits, COMP3op_src0_mask, \
1366 COMP3op_src1_bits, COMP3op_src1_mask, \
1367 COMP3op_dst_bits, COMP3op_dst_mask, \
1368 COMP3op_opc_bits, COMP3op_opc_mask, \
1369 COMP3op_code_bits, COMP3op_code_mask \
1373 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1374 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1375 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1380 unsigned short opcode
;
1395 #define CCmv_opcode 0x0600
1396 #define CCmv_src_bits 0
1397 #define CCmv_src_mask 0x7
1398 #define CCmv_dst_bits 3
1399 #define CCmv_dst_mask 0x7
1400 #define CCmv_s_bits 6
1401 #define CCmv_s_mask 0x1
1402 #define CCmv_d_bits 7
1403 #define CCmv_d_mask 0x1
1404 #define CCmv_T_bits 8
1405 #define CCmv_T_mask 0x1
1406 #define CCmv_code_bits 9
1407 #define CCmv_code_mask 0x7f
1412 CCmv_src_bits, CCmv_src_mask, \
1413 CCmv_dst_bits, CCmv_dst_mask, \
1414 CCmv_s_bits, CCmv_s_mask, \
1415 CCmv_d_bits, CCmv_d_mask, \
1416 CCmv_T_bits, CCmv_T_mask, \
1417 CCmv_code_bits, CCmv_code_mask \
1422 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1423 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1424 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1429 unsigned short opcode
;
1444 #define CCflag_opcode 0x0800
1445 #define CCflag_x_bits 0
1446 #define CCflag_x_mask 0x7
1447 #define CCflag_y_bits 3
1448 #define CCflag_y_mask 0x7
1449 #define CCflag_G_bits 6
1450 #define CCflag_G_mask 0x1
1451 #define CCflag_opc_bits 7
1452 #define CCflag_opc_mask 0x7
1453 #define CCflag_I_bits 10
1454 #define CCflag_I_mask 0x1
1455 #define CCflag_code_bits 11
1456 #define CCflag_code_mask 0x1f
1458 #define init_CCflag \
1461 CCflag_x_bits, CCflag_x_mask, \
1462 CCflag_y_bits, CCflag_y_mask, \
1463 CCflag_G_bits, CCflag_G_mask, \
1464 CCflag_opc_bits, CCflag_opc_mask, \
1465 CCflag_I_bits, CCflag_I_mask, \
1466 CCflag_code_bits, CCflag_code_mask, \
1471 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1472 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1473 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1478 unsigned short opcode
;
1489 #define CC2stat_opcode 0x0300
1490 #define CC2stat_cbit_bits 0
1491 #define CC2stat_cbit_mask 0x1f
1492 #define CC2stat_op_bits 5
1493 #define CC2stat_op_mask 0x3
1494 #define CC2stat_D_bits 7
1495 #define CC2stat_D_mask 0x1
1496 #define CC2stat_code_bits 8
1497 #define CC2stat_code_mask 0xff
1499 #define init_CC2stat \
1502 CC2stat_cbit_bits, CC2stat_cbit_mask, \
1503 CC2stat_op_bits, CC2stat_op_mask, \
1504 CC2stat_D_bits, CC2stat_D_mask, \
1505 CC2stat_code_bits, CC2stat_code_mask \
1510 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1511 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1512 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1517 unsigned short opcode
;
1530 #define RegMv_opcode 0x3000
1531 #define RegMv_src_bits 0
1532 #define RegMv_src_mask 0x7
1533 #define RegMv_dst_bits 3
1534 #define RegMv_dst_mask 0x7
1535 #define RegMv_gs_bits 6
1536 #define RegMv_gs_mask 0x7
1537 #define RegMv_gd_bits 9
1538 #define RegMv_gd_mask 0x7
1539 #define RegMv_code_bits 12
1540 #define RegMv_code_mask 0xf
1542 #define init_RegMv \
1545 RegMv_src_bits, RegMv_src_mask, \
1546 RegMv_dst_bits, RegMv_dst_mask, \
1547 RegMv_gs_bits, RegMv_gs_mask, \
1548 RegMv_gd_bits, RegMv_gd_mask, \
1549 RegMv_code_bits, RegMv_code_mask \
1554 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1555 | 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
1556 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1561 unsigned short opcode
;
1572 #define COMPI2opD_opcode 0x6000
1573 #define COMPI2opD_dst_bits 0
1574 #define COMPI2opD_dst_mask 0x7
1575 #define COMPI2opD_src_bits 3
1576 #define COMPI2opD_src_mask 0x7f
1577 #define COMPI2opD_op_bits 10
1578 #define COMPI2opD_op_mask 0x1
1579 #define COMPI2opD_code_bits 11
1580 #define COMPI2opD_code_mask 0x1f
1582 #define init_COMPI2opD \
1585 COMPI2opD_dst_bits, COMPI2opD_dst_mask, \
1586 COMPI2opD_src_bits, COMPI2opD_src_mask, \
1587 COMPI2opD_op_bits, COMPI2opD_op_mask, \
1588 COMPI2opD_code_bits, COMPI2opD_code_mask \
1592 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1593 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1594 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1597 typedef COMPI2opD COMPI2opP
;
1599 #define COMPI2opP_opcode 0x6800
1600 #define COMPI2opP_dst_bits 0
1601 #define COMPI2opP_dst_mask 0x7
1602 #define COMPI2opP_src_bits 3
1603 #define COMPI2opP_src_mask 0x7f
1604 #define COMPI2opP_op_bits 10
1605 #define COMPI2opP_op_mask 0x1
1606 #define COMPI2opP_code_bits 11
1607 #define COMPI2opP_code_mask 0x1f
1609 #define init_COMPI2opP \
1612 COMPI2opP_dst_bits, COMPI2opP_dst_mask, \
1613 COMPI2opP_src_bits, COMPI2opP_src_mask, \
1614 COMPI2opP_op_bits, COMPI2opP_op_mask, \
1615 COMPI2opP_code_bits, COMPI2opP_code_mask \
1620 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1621 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1622 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1627 unsigned short opcode
;
1642 #define DagMODim_opcode 0x9e60
1643 #define DagMODim_i_bits 0
1644 #define DagMODim_i_mask 0x3
1645 #define DagMODim_m_bits 2
1646 #define DagMODim_m_mask 0x3
1647 #define DagMODim_op_bits 4
1648 #define DagMODim_op_mask 0x1
1649 #define DagMODim_code2_bits 5
1650 #define DagMODim_code2_mask 0x3
1651 #define DagMODim_br_bits 7
1652 #define DagMODim_br_mask 0x1
1653 #define DagMODim_code_bits 8
1654 #define DagMODim_code_mask 0xff
1656 #define init_DagMODim \
1659 DagMODim_i_bits, DagMODim_i_mask, \
1660 DagMODim_m_bits, DagMODim_m_mask, \
1661 DagMODim_op_bits, DagMODim_op_mask, \
1662 DagMODim_code2_bits, DagMODim_code2_mask, \
1663 DagMODim_br_bits, DagMODim_br_mask, \
1664 DagMODim_code_bits, DagMODim_code_mask \
1668 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1669 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1670 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1675 unsigned short opcode
;
1684 #define DagMODik_opcode 0x9f60
1685 #define DagMODik_i_bits 0
1686 #define DagMODik_i_mask 0x3
1687 #define DagMODik_op_bits 2
1688 #define DagMODik_op_mask 0x3
1689 #define DagMODik_code_bits 3
1690 #define DagMODik_code_mask 0xfff
1692 #define init_DagMODik \
1695 DagMODik_i_bits, DagMODik_i_mask, \
1696 DagMODik_op_bits, DagMODik_op_mask, \
1697 DagMODik_code_bits, DagMODik_code_mask \
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