1 /* bfin.h -- Header file for ADI Blackfin opcode table
2 Copyright 2005, 2010 Free Software Foundation, Inc.
4 This file is part of GDB, GAS, and the GNU binutils.
6 GDB, GAS, and the GNU binutils are free software; you can redistribute
7 them and/or modify them under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either version 3,
9 or (at your option) any later version.
11 GDB, GAS, and the GNU binutils are distributed in the hope that they
12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 the GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING3. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
21 /* Common to all DSP32 instructions. */
22 #define BIT_MULTI_INS 0x0800
24 /* This just sets the multi instruction bit of a DSP32 instruction. */
25 #define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS;
28 /* DSP instructions (32 bit) */
31 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
32 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
33 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
34 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
76 #define DSP32Mac_opcode 0xc0000000
77 #define DSP32Mac_src1_bits 0
78 #define DSP32Mac_src1_mask 0x7
79 #define DSP32Mac_src0_bits 3
80 #define DSP32Mac_src0_mask 0x7
81 #define DSP32Mac_dst_bits 6
82 #define DSP32Mac_dst_mask 0x7
83 #define DSP32Mac_h10_bits 9
84 #define DSP32Mac_h10_mask 0x1
85 #define DSP32Mac_h00_bits 10
86 #define DSP32Mac_h00_mask 0x1
87 #define DSP32Mac_op0_bits 11
88 #define DSP32Mac_op0_mask 0x3
89 #define DSP32Mac_w0_bits 13
90 #define DSP32Mac_w0_mask 0x1
91 #define DSP32Mac_h11_bits 14
92 #define DSP32Mac_h11_mask 0x1
93 #define DSP32Mac_h01_bits 15
94 #define DSP32Mac_h01_mask 0x1
95 #define DSP32Mac_op1_bits 16
96 #define DSP32Mac_op1_mask 0x3
97 #define DSP32Mac_w1_bits 18
98 #define DSP32Mac_w1_mask 0x1
99 #define DSP32Mac_p_bits 19
100 #define DSP32Mac_p_mask 0x1
101 #define DSP32Mac_MM_bits 20
102 #define DSP32Mac_MM_mask 0x1
103 #define DSP32Mac_mmod_bits 21
104 #define DSP32Mac_mmod_mask 0xf
105 #define DSP32Mac_code2_bits 25
106 #define DSP32Mac_code2_mask 0x3
107 #define DSP32Mac_M_bits 27
108 #define DSP32Mac_M_mask 0x1
109 #define DSP32Mac_code_bits 28
110 #define DSP32Mac_code_mask 0xf
112 #define init_DSP32Mac \
115 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
116 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
117 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
118 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
119 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
120 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
121 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
122 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
123 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
124 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
125 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
126 DSP32Mac_p_bits, DSP32Mac_p_mask, \
127 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
128 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
129 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
130 DSP32Mac_M_bits, DSP32Mac_M_mask, \
131 DSP32Mac_code_bits, DSP32Mac_code_mask \
135 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
136 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
137 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
138 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
141 typedef DSP32Mac DSP32Mult
;
142 #define DSP32Mult_opcode 0xc2000000
144 #define init_DSP32Mult \
147 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
148 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
149 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
150 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
151 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
152 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
153 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
154 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
155 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
156 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
157 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
158 DSP32Mac_p_bits, DSP32Mac_p_mask, \
159 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
160 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
161 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
162 DSP32Mac_M_bits, DSP32Mac_M_mask, \
163 DSP32Mac_code_bits, DSP32Mac_code_mask \
167 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
168 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
169 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
170 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
175 unsigned long opcode
;
204 #define DSP32Alu_opcode 0xc4000000
205 #define DSP32Alu_src1_bits 0
206 #define DSP32Alu_src1_mask 0x7
207 #define DSP32Alu_src0_bits 3
208 #define DSP32Alu_src0_mask 0x7
209 #define DSP32Alu_dst1_bits 6
210 #define DSP32Alu_dst1_mask 0x7
211 #define DSP32Alu_dst0_bits 9
212 #define DSP32Alu_dst0_mask 0x7
213 #define DSP32Alu_x_bits 12
214 #define DSP32Alu_x_mask 0x1
215 #define DSP32Alu_s_bits 13
216 #define DSP32Alu_s_mask 0x1
217 #define DSP32Alu_aop_bits 14
218 #define DSP32Alu_aop_mask 0x3
219 #define DSP32Alu_aopcde_bits 16
220 #define DSP32Alu_aopcde_mask 0x1f
221 #define DSP32Alu_HL_bits 21
222 #define DSP32Alu_HL_mask 0x1
223 #define DSP32Alu_dontcare_bits 22
224 #define DSP32Alu_dontcare_mask 0x7
225 #define DSP32Alu_code2_bits 25
226 #define DSP32Alu_code2_mask 0x3
227 #define DSP32Alu_M_bits 27
228 #define DSP32Alu_M_mask 0x1
229 #define DSP32Alu_code_bits 28
230 #define DSP32Alu_code_mask 0xf
232 #define init_DSP32Alu \
235 DSP32Alu_src1_bits, DSP32Alu_src1_mask, \
236 DSP32Alu_src0_bits, DSP32Alu_src0_mask, \
237 DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \
238 DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \
239 DSP32Alu_x_bits, DSP32Alu_x_mask, \
240 DSP32Alu_s_bits, DSP32Alu_s_mask, \
241 DSP32Alu_aop_bits, DSP32Alu_aop_mask, \
242 DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \
243 DSP32Alu_HL_bits, DSP32Alu_HL_mask, \
244 DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \
245 DSP32Alu_code2_bits, DSP32Alu_code2_mask, \
246 DSP32Alu_M_bits, DSP32Alu_M_mask, \
247 DSP32Alu_code_bits, DSP32Alu_code_mask \
251 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
252 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
253 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
254 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
259 unsigned long opcode
;
284 #define DSP32Shift_opcode 0xc6000000
285 #define DSP32Shift_src1_bits 0
286 #define DSP32Shift_src1_mask 0x7
287 #define DSP32Shift_src0_bits 3
288 #define DSP32Shift_src0_mask 0x7
289 #define DSP32Shift_dst1_bits 6
290 #define DSP32Shift_dst1_mask 0x7
291 #define DSP32Shift_dst0_bits 9
292 #define DSP32Shift_dst0_mask 0x7
293 #define DSP32Shift_HLs_bits 12
294 #define DSP32Shift_HLs_mask 0x3
295 #define DSP32Shift_sop_bits 14
296 #define DSP32Shift_sop_mask 0x3
297 #define DSP32Shift_sopcde_bits 16
298 #define DSP32Shift_sopcde_mask 0x1f
299 #define DSP32Shift_dontcare_bits 21
300 #define DSP32Shift_dontcare_mask 0x3
301 #define DSP32Shift_code2_bits 23
302 #define DSP32Shift_code2_mask 0xf
303 #define DSP32Shift_M_bits 27
304 #define DSP32Shift_M_mask 0x1
305 #define DSP32Shift_code_bits 28
306 #define DSP32Shift_code_mask 0xf
308 #define init_DSP32Shift \
311 DSP32Shift_src1_bits, DSP32Shift_src1_mask, \
312 DSP32Shift_src0_bits, DSP32Shift_src0_mask, \
313 DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \
314 DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \
315 DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \
316 DSP32Shift_sop_bits, DSP32Shift_sop_mask, \
317 DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \
318 DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \
319 DSP32Shift_code2_bits, DSP32Shift_code2_mask, \
320 DSP32Shift_M_bits, DSP32Shift_M_mask, \
321 DSP32Shift_code_bits, DSP32Shift_code_mask \
325 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
326 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
327 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
328 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
333 unsigned long opcode
;
356 #define DSP32ShiftImm_opcode 0xc6800000
357 #define DSP32ShiftImm_src1_bits 0
358 #define DSP32ShiftImm_src1_mask 0x7
359 #define DSP32ShiftImm_immag_bits 3
360 #define DSP32ShiftImm_immag_mask 0x3f
361 #define DSP32ShiftImm_dst0_bits 9
362 #define DSP32ShiftImm_dst0_mask 0x7
363 #define DSP32ShiftImm_HLs_bits 12
364 #define DSP32ShiftImm_HLs_mask 0x3
365 #define DSP32ShiftImm_sop_bits 14
366 #define DSP32ShiftImm_sop_mask 0x3
367 #define DSP32ShiftImm_sopcde_bits 16
368 #define DSP32ShiftImm_sopcde_mask 0x1f
369 #define DSP32ShiftImm_dontcare_bits 21
370 #define DSP32ShiftImm_dontcare_mask 0x3
371 #define DSP32ShiftImm_code2_bits 23
372 #define DSP32ShiftImm_code2_mask 0xf
373 #define DSP32ShiftImm_M_bits 27
374 #define DSP32ShiftImm_M_mask 0x1
375 #define DSP32ShiftImm_code_bits 28
376 #define DSP32ShiftImm_code_mask 0xf
378 #define init_DSP32ShiftImm \
380 DSP32ShiftImm_opcode, \
381 DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \
382 DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \
383 DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \
384 DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \
385 DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \
386 DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \
387 DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \
388 DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \
389 DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \
390 DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \
396 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
397 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
398 |.offset........................................................|
399 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
404 unsigned long opcode
;
421 #define LDSTidxI_opcode 0xe4000000
422 #define LDSTidxI_offset_bits 0
423 #define LDSTidxI_offset_mask 0xffff
424 #define LDSTidxI_reg_bits 16
425 #define LDSTidxI_reg_mask 0x7
426 #define LDSTidxI_ptr_bits 19
427 #define LDSTidxI_ptr_mask 0x7
428 #define LDSTidxI_sz_bits 22
429 #define LDSTidxI_sz_mask 0x3
430 #define LDSTidxI_Z_bits 24
431 #define LDSTidxI_Z_mask 0x1
432 #define LDSTidxI_W_bits 25
433 #define LDSTidxI_W_mask 0x1
434 #define LDSTidxI_code_bits 26
435 #define LDSTidxI_code_mask 0x3f
437 #define init_LDSTidxI \
440 LDSTidxI_offset_bits, LDSTidxI_offset_mask, \
441 LDSTidxI_reg_bits, LDSTidxI_reg_mask, \
442 LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \
443 LDSTidxI_sz_bits, LDSTidxI_sz_mask, \
444 LDSTidxI_Z_bits, LDSTidxI_Z_mask, \
445 LDSTidxI_W_bits, LDSTidxI_W_mask, \
446 LDSTidxI_code_bits, LDSTidxI_code_mask \
451 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
452 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
453 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
458 unsigned short opcode
;
475 #define LDST_opcode 0x9000
476 #define LDST_reg_bits 0
477 #define LDST_reg_mask 0x7
478 #define LDST_ptr_bits 3
479 #define LDST_ptr_mask 0x7
480 #define LDST_Z_bits 6
481 #define LDST_Z_mask 0x1
482 #define LDST_aop_bits 7
483 #define LDST_aop_mask 0x3
484 #define LDST_W_bits 9
485 #define LDST_W_mask 0x1
486 #define LDST_sz_bits 10
487 #define LDST_sz_mask 0x3
488 #define LDST_code_bits 12
489 #define LDST_code_mask 0xf
494 LDST_reg_bits, LDST_reg_mask, \
495 LDST_ptr_bits, LDST_ptr_mask, \
496 LDST_Z_bits, LDST_Z_mask, \
497 LDST_aop_bits, LDST_aop_mask, \
498 LDST_W_bits, LDST_W_mask, \
499 LDST_sz_bits, LDST_sz_mask, \
500 LDST_code_bits, LDST_code_mask \
504 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
505 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
506 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
511 unsigned short opcode
;
526 #define LDSTii_opcode 0xa000
527 #define LDSTii_reg_bit 0
528 #define LDSTii_reg_mask 0x7
529 #define LDSTii_ptr_bit 3
530 #define LDSTii_ptr_mask 0x7
531 #define LDSTii_offset_bit 6
532 #define LDSTii_offset_mask 0xf
533 #define LDSTii_op_bit 10
534 #define LDSTii_op_mask 0x3
535 #define LDSTii_W_bit 12
536 #define LDSTii_W_mask 0x1
537 #define LDSTii_code_bit 13
538 #define LDSTii_code_mask 0x7
540 #define init_LDSTii \
543 LDSTii_reg_bit, LDSTii_reg_mask, \
544 LDSTii_ptr_bit, LDSTii_ptr_mask, \
545 LDSTii_offset_bit, LDSTii_offset_mask, \
546 LDSTii_op_bit, LDSTii_op_mask, \
547 LDSTii_W_bit, LDSTii_W_mask, \
548 LDSTii_code_bit, LDSTii_code_mask \
553 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
554 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
555 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
560 unsigned short opcode
;
571 #define LDSTiiFP_opcode 0xb800
572 #define LDSTiiFP_reg_bits 0
573 #define LDSTiiFP_reg_mask 0xf
574 #define LDSTiiFP_offset_bits 4
575 #define LDSTiiFP_offset_mask 0x1f
576 #define LDSTiiFP_W_bits 9
577 #define LDSTiiFP_W_mask 0x1
578 #define LDSTiiFP_code_bits 10
579 #define LDSTiiFP_code_mask 0x3f
581 #define init_LDSTiiFP \
584 LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \
585 LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \
586 LDSTiiFP_W_bits, LDSTiiFP_W_mask, \
587 LDSTiiFP_code_bits, LDSTiiFP_code_mask \
591 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
592 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
593 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
598 unsigned short opcode
;
613 #define DspLDST_opcode 0x9c00
614 #define DspLDST_reg_bits 0
615 #define DspLDST_reg_mask 0x7
616 #define DspLDST_i_bits 3
617 #define DspLDST_i_mask 0x3
618 #define DspLDST_m_bits 5
619 #define DspLDST_m_mask 0x3
620 #define DspLDST_aop_bits 7
621 #define DspLDST_aop_mask 0x3
622 #define DspLDST_W_bits 9
623 #define DspLDST_W_mask 0x1
624 #define DspLDST_code_bits 10
625 #define DspLDST_code_mask 0x3f
627 #define init_DspLDST \
630 DspLDST_reg_bits, DspLDST_reg_mask, \
631 DspLDST_i_bits, DspLDST_i_mask, \
632 DspLDST_m_bits, DspLDST_m_mask, \
633 DspLDST_aop_bits, DspLDST_aop_mask, \
634 DspLDST_W_bits, DspLDST_W_mask, \
635 DspLDST_code_bits, DspLDST_code_mask \
640 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
641 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
642 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
647 unsigned short opcode
;
662 #define LDSTpmod_opcode 0x8000
663 #define LDSTpmod_ptr_bits 0
664 #define LDSTpmod_ptr_mask 0x7
665 #define LDSTpmod_idx_bits 3
666 #define LDSTpmod_idx_mask 0x7
667 #define LDSTpmod_reg_bits 6
668 #define LDSTpmod_reg_mask 0x7
669 #define LDSTpmod_aop_bits 9
670 #define LDSTpmod_aop_mask 0x3
671 #define LDSTpmod_W_bits 11
672 #define LDSTpmod_W_mask 0x1
673 #define LDSTpmod_code_bits 12
674 #define LDSTpmod_code_mask 0xf
676 #define init_LDSTpmod \
679 LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \
680 LDSTpmod_idx_bits, LDSTpmod_idx_mask, \
681 LDSTpmod_reg_bits, LDSTpmod_reg_mask, \
682 LDSTpmod_aop_bits, LDSTpmod_aop_mask, \
683 LDSTpmod_W_bits, LDSTpmod_W_mask, \
684 LDSTpmod_code_bits, LDSTpmod_code_mask \
689 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
690 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
691 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
696 unsigned short opcode
;
707 #define LOGI2op_opcode 0x4800
708 #define LOGI2op_dst_bits 0
709 #define LOGI2op_dst_mask 0x7
710 #define LOGI2op_src_bits 3
711 #define LOGI2op_src_mask 0x1f
712 #define LOGI2op_opc_bits 8
713 #define LOGI2op_opc_mask 0x7
714 #define LOGI2op_code_bits 11
715 #define LOGI2op_code_mask 0x1f
717 #define init_LOGI2op \
720 LOGI2op_dst_bits, LOGI2op_dst_mask, \
721 LOGI2op_src_bits, LOGI2op_src_mask, \
722 LOGI2op_opc_bits, LOGI2op_opc_mask, \
723 LOGI2op_code_bits, LOGI2op_code_mask \
728 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
729 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
730 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
735 unsigned short opcode
;
746 #define ALU2op_opcode 0x4000
747 #define ALU2op_dst_bits 0
748 #define ALU2op_dst_mask 0x7
749 #define ALU2op_src_bits 3
750 #define ALU2op_src_mask 0x7
751 #define ALU2op_opc_bits 6
752 #define ALU2op_opc_mask 0xf
753 #define ALU2op_code_bits 10
754 #define ALU2op_code_mask 0x3f
756 #define init_ALU2op \
759 ALU2op_dst_bits, ALU2op_dst_mask, \
760 ALU2op_src_bits, ALU2op_src_mask, \
761 ALU2op_opc_bits, ALU2op_opc_mask, \
762 ALU2op_code_bits, ALU2op_code_mask \
767 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
768 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
769 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
774 unsigned short opcode
;
785 #define BRCC_opcode 0x1000
786 #define BRCC_offset_bits 0
787 #define BRCC_offset_mask 0x3ff
788 #define BRCC_B_bits 10
789 #define BRCC_B_mask 0x1
790 #define BRCC_T_bits 11
791 #define BRCC_T_mask 0x1
792 #define BRCC_code_bits 12
793 #define BRCC_code_mask 0xf
798 BRCC_offset_bits, BRCC_offset_mask, \
799 BRCC_B_bits, BRCC_B_mask, \
800 BRCC_T_bits, BRCC_T_mask, \
801 BRCC_code_bits, BRCC_code_mask \
806 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
807 | 0 | 0 | 1 | 0 |.offset........................................|
808 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
813 unsigned short opcode
;
820 #define UJump_opcode 0x2000
821 #define UJump_offset_bits 0
822 #define UJump_offset_mask 0xfff
823 #define UJump_code_bits 12
824 #define UJump_code_mask 0xf
829 UJump_offset_bits, UJump_offset_mask, \
830 UJump_code_bits, UJump_code_mask \
835 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
836 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
837 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
842 unsigned short opcode
;
851 #define ProgCtrl_opcode 0x0000
852 #define ProgCtrl_poprnd_bits 0
853 #define ProgCtrl_poprnd_mask 0xf
854 #define ProgCtrl_prgfunc_bits 4
855 #define ProgCtrl_prgfunc_mask 0xf
856 #define ProgCtrl_code_bits 8
857 #define ProgCtrl_code_mask 0xff
859 #define init_ProgCtrl \
862 ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \
863 ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \
864 ProgCtrl_code_bits, ProgCtrl_code_mask \
868 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
869 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
870 |.lsw...........................................................|
871 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
877 unsigned long opcode
;
886 #define CALLa_opcode 0xe2000000
887 #define CALLa_addr_bits 0
888 #define CALLa_addr_mask 0xffffff
889 #define CALLa_S_bits 24
890 #define CALLa_S_mask 0x1
891 #define CALLa_code_bits 25
892 #define CALLa_code_mask 0x7f
897 CALLa_addr_bits, CALLa_addr_mask, \
898 CALLa_S_bits, CALLa_S_mask, \
899 CALLa_code_bits, CALLa_code_mask \
904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
905 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
911 unsigned short opcode
;
922 #define PseudoDbg_opcode 0xf800
923 #define PseudoDbg_reg_bits 0
924 #define PseudoDbg_reg_mask 0x7
925 #define PseudoDbg_grp_bits 3
926 #define PseudoDbg_grp_mask 0x7
927 #define PseudoDbg_fn_bits 6
928 #define PseudoDbg_fn_mask 0x3
929 #define PseudoDbg_code_bits 8
930 #define PseudoDbg_code_mask 0xff
932 #define init_PseudoDbg \
935 PseudoDbg_reg_bits, PseudoDbg_reg_mask, \
936 PseudoDbg_grp_bits, PseudoDbg_grp_mask, \
937 PseudoDbg_fn_bits, PseudoDbg_fn_mask, \
938 PseudoDbg_code_bits, PseudoDbg_code_mask \
942 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
943 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
944 |.expected......................................................|
945 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
950 unsigned long opcode
;
965 #define PseudoDbg_Assert_opcode 0xf0000000
966 #define PseudoDbg_Assert_expected_bits 0
967 #define PseudoDbg_Assert_expected_mask 0xffff
968 #define PseudoDbg_Assert_regtest_bits 16
969 #define PseudoDbg_Assert_regtest_mask 0x7
970 #define PseudoDbg_Assert_grp_bits 19
971 #define PseudoDbg_Assert_grp_mask 0x7
972 #define PseudoDbg_Assert_dbgop_bits 22
973 #define PseudoDbg_Assert_dbgop_mask 0x3
974 #define PseudoDbg_Assert_dontcare_bits 24
975 #define PseudoDbg_Assert_dontcare_mask 0x7
976 #define PseudoDbg_Assert_code_bits 27
977 #define PseudoDbg_Assert_code_mask 0x1f
979 #define init_PseudoDbg_Assert \
981 PseudoDbg_Assert_opcode, \
982 PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
983 PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
984 PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
985 PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
986 PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
987 PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
991 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
992 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
993 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
998 unsigned short opcode
;
1005 #define PseudoChr_opcode 0xf900
1006 #define PseudoChr_ch_bits 0
1007 #define PseudoChr_ch_mask 0xff
1008 #define PseudoChr_code_bits 8
1009 #define PseudoChr_code_mask 0xff
1011 #define init_PseudoChr \
1014 PseudoChr_ch_bits, PseudoChr_ch_mask, \
1015 PseudoChr_code_bits, PseudoChr_code_mask \
1019 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1020 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
1021 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1026 unsigned short opcode
;
1037 #define CaCTRL_opcode 0x0240
1038 #define CaCTRL_reg_bits 0
1039 #define CaCTRL_reg_mask 0x7
1040 #define CaCTRL_op_bits 3
1041 #define CaCTRL_op_mask 0x3
1042 #define CaCTRL_a_bits 5
1043 #define CaCTRL_a_mask 0x1
1044 #define CaCTRL_code_bits 6
1045 #define CaCTRL_code_mask 0x3fff
1047 #define init_CaCTRL \
1050 CaCTRL_reg_bits, CaCTRL_reg_mask, \
1051 CaCTRL_op_bits, CaCTRL_op_mask, \
1052 CaCTRL_a_bits, CaCTRL_a_mask, \
1053 CaCTRL_code_bits, CaCTRL_code_mask \
1057 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1058 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
1059 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1064 unsigned short opcode
;
1079 #define PushPopMultiple_opcode 0x0400
1080 #define PushPopMultiple_pr_bits 0
1081 #define PushPopMultiple_pr_mask 0x7
1082 #define PushPopMultiple_dr_bits 3
1083 #define PushPopMultiple_dr_mask 0x7
1084 #define PushPopMultiple_W_bits 6
1085 #define PushPopMultiple_W_mask 0x1
1086 #define PushPopMultiple_p_bits 7
1087 #define PushPopMultiple_p_mask 0x1
1088 #define PushPopMultiple_d_bits 8
1089 #define PushPopMultiple_d_mask 0x1
1090 #define PushPopMultiple_code_bits 8
1091 #define PushPopMultiple_code_mask 0x1
1093 #define init_PushPopMultiple \
1095 PushPopMultiple_opcode, \
1096 PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \
1097 PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \
1098 PushPopMultiple_W_bits, PushPopMultiple_W_mask, \
1099 PushPopMultiple_p_bits, PushPopMultiple_p_mask, \
1100 PushPopMultiple_d_bits, PushPopMultiple_d_mask, \
1101 PushPopMultiple_code_bits, PushPopMultiple_code_mask \
1105 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1106 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
1107 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1112 unsigned short opcode
;
1123 #define PushPopReg_opcode 0x0100
1124 #define PushPopReg_reg_bits 0
1125 #define PushPopReg_reg_mask 0x7
1126 #define PushPopReg_grp_bits 3
1127 #define PushPopReg_grp_mask 0x7
1128 #define PushPopReg_W_bits 6
1129 #define PushPopReg_W_mask 0x1
1130 #define PushPopReg_code_bits 7
1131 #define PushPopReg_code_mask 0x1ff
1133 #define init_PushPopReg \
1135 PushPopReg_opcode, \
1136 PushPopReg_reg_bits, PushPopReg_reg_mask, \
1137 PushPopReg_grp_bits, PushPopReg_grp_mask, \
1138 PushPopReg_W_bits, PushPopReg_W_mask, \
1139 PushPopReg_code_bits, PushPopReg_code_mask, \
1143 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1144 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
1145 |.framesize.....................................................|
1146 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1151 unsigned long opcode
;
1160 #define Linkage_opcode 0xe8000000
1161 #define Linkage_framesize_bits 0
1162 #define Linkage_framesize_mask 0xffff
1163 #define Linkage_R_bits 16
1164 #define Linkage_R_mask 0x1
1165 #define Linkage_code_bits 17
1166 #define Linkage_code_mask 0x7fff
1168 #define init_Linkage \
1171 Linkage_framesize_bits, Linkage_framesize_mask, \
1172 Linkage_R_bits, Linkage_R_mask, \
1173 Linkage_code_bits, Linkage_code_mask \
1177 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1178 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
1179 |.reg...........| - | - |.eoffset...............................|
1180 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1185 unsigned long opcode
;
1202 #define LoopSetup_opcode 0xe0800000
1203 #define LoopSetup_eoffset_bits 0
1204 #define LoopSetup_eoffset_mask 0x3ff
1205 #define LoopSetup_dontcare_bits 10
1206 #define LoopSetup_dontcare_mask 0x3
1207 #define LoopSetup_reg_bits 12
1208 #define LoopSetup_reg_mask 0xf
1209 #define LoopSetup_soffset_bits 16
1210 #define LoopSetup_soffset_mask 0xf
1211 #define LoopSetup_c_bits 20
1212 #define LoopSetup_c_mask 0x1
1213 #define LoopSetup_rop_bits 21
1214 #define LoopSetup_rop_mask 0x3
1215 #define LoopSetup_code_bits 23
1216 #define LoopSetup_code_mask 0x1ff
1218 #define init_LoopSetup \
1221 LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \
1222 LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \
1223 LoopSetup_reg_bits, LoopSetup_reg_mask, \
1224 LoopSetup_soffset_bits, LoopSetup_soffset_mask, \
1225 LoopSetup_c_bits, LoopSetup_c_mask, \
1226 LoopSetup_rop_bits, LoopSetup_rop_mask, \
1227 LoopSetup_code_bits, LoopSetup_code_mask \
1231 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1232 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
1233 |.hword.........................................................|
1234 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1239 unsigned long opcode
;
1256 #define LDIMMhalf_opcode 0xe1000000
1257 #define LDIMMhalf_hword_bits 0
1258 #define LDIMMhalf_hword_mask 0xffff
1259 #define LDIMMhalf_reg_bits 16
1260 #define LDIMMhalf_reg_mask 0x7
1261 #define LDIMMhalf_grp_bits 19
1262 #define LDIMMhalf_grp_mask 0x3
1263 #define LDIMMhalf_S_bits 21
1264 #define LDIMMhalf_S_mask 0x1
1265 #define LDIMMhalf_H_bits 22
1266 #define LDIMMhalf_H_mask 0x1
1267 #define LDIMMhalf_Z_bits 23
1268 #define LDIMMhalf_Z_mask 0x1
1269 #define LDIMMhalf_code_bits 24
1270 #define LDIMMhalf_code_mask 0xff
1272 #define init_LDIMMhalf \
1275 LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \
1276 LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \
1277 LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \
1278 LDIMMhalf_S_bits, LDIMMhalf_S_mask, \
1279 LDIMMhalf_H_bits, LDIMMhalf_H_mask, \
1280 LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \
1281 LDIMMhalf_code_bits, LDIMMhalf_code_mask \
1286 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1287 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1288 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1293 unsigned short opcode
;
1302 #define CC2dreg_opcode 0x0200
1303 #define CC2dreg_reg_bits 0
1304 #define CC2dreg_reg_mask 0x7
1305 #define CC2dreg_op_bits 3
1306 #define CC2dreg_op_mask 0x3
1307 #define CC2dreg_code_bits 5
1308 #define CC2dreg_code_mask 0x7fff
1310 #define init_CC2dreg \
1313 CC2dreg_reg_bits, CC2dreg_reg_mask, \
1314 CC2dreg_op_bits, CC2dreg_op_mask, \
1315 CC2dreg_code_bits, CC2dreg_code_mask \
1320 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1321 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1322 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1327 unsigned short opcode
;
1338 #define PTR2op_opcode 0x4400
1339 #define PTR2op_dst_bits 0
1340 #define PTR2op_dst_mask 0x7
1341 #define PTR2op_src_bits 3
1342 #define PTR2op_src_mask 0x7
1343 #define PTR2op_opc_bits 6
1344 #define PTR2op_opc_mask 0x7
1345 #define PTR2op_code_bits 9
1346 #define PTR2op_code_mask 0x7f
1348 #define init_PTR2op \
1351 PTR2op_dst_bits, PTR2op_dst_mask, \
1352 PTR2op_src_bits, PTR2op_src_mask, \
1353 PTR2op_opc_bits, PTR2op_opc_mask, \
1354 PTR2op_code_bits, PTR2op_code_mask \
1359 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1360 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1361 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1366 unsigned short opcode
;
1379 #define COMP3op_opcode 0x5000
1380 #define COMP3op_src0_bits 0
1381 #define COMP3op_src0_mask 0x7
1382 #define COMP3op_src1_bits 3
1383 #define COMP3op_src1_mask 0x7
1384 #define COMP3op_dst_bits 6
1385 #define COMP3op_dst_mask 0x7
1386 #define COMP3op_opc_bits 9
1387 #define COMP3op_opc_mask 0x7
1388 #define COMP3op_code_bits 12
1389 #define COMP3op_code_mask 0xf
1391 #define init_COMP3op \
1394 COMP3op_src0_bits, COMP3op_src0_mask, \
1395 COMP3op_src1_bits, COMP3op_src1_mask, \
1396 COMP3op_dst_bits, COMP3op_dst_mask, \
1397 COMP3op_opc_bits, COMP3op_opc_mask, \
1398 COMP3op_code_bits, COMP3op_code_mask \
1402 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1403 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1404 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1409 unsigned short opcode
;
1424 #define CCmv_opcode 0x0600
1425 #define CCmv_src_bits 0
1426 #define CCmv_src_mask 0x7
1427 #define CCmv_dst_bits 3
1428 #define CCmv_dst_mask 0x7
1429 #define CCmv_s_bits 6
1430 #define CCmv_s_mask 0x1
1431 #define CCmv_d_bits 7
1432 #define CCmv_d_mask 0x1
1433 #define CCmv_T_bits 8
1434 #define CCmv_T_mask 0x1
1435 #define CCmv_code_bits 9
1436 #define CCmv_code_mask 0x7f
1441 CCmv_src_bits, CCmv_src_mask, \
1442 CCmv_dst_bits, CCmv_dst_mask, \
1443 CCmv_s_bits, CCmv_s_mask, \
1444 CCmv_d_bits, CCmv_d_mask, \
1445 CCmv_T_bits, CCmv_T_mask, \
1446 CCmv_code_bits, CCmv_code_mask \
1451 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1452 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1453 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1458 unsigned short opcode
;
1473 #define CCflag_opcode 0x0800
1474 #define CCflag_x_bits 0
1475 #define CCflag_x_mask 0x7
1476 #define CCflag_y_bits 3
1477 #define CCflag_y_mask 0x7
1478 #define CCflag_G_bits 6
1479 #define CCflag_G_mask 0x1
1480 #define CCflag_opc_bits 7
1481 #define CCflag_opc_mask 0x7
1482 #define CCflag_I_bits 10
1483 #define CCflag_I_mask 0x1
1484 #define CCflag_code_bits 11
1485 #define CCflag_code_mask 0x1f
1487 #define init_CCflag \
1490 CCflag_x_bits, CCflag_x_mask, \
1491 CCflag_y_bits, CCflag_y_mask, \
1492 CCflag_G_bits, CCflag_G_mask, \
1493 CCflag_opc_bits, CCflag_opc_mask, \
1494 CCflag_I_bits, CCflag_I_mask, \
1495 CCflag_code_bits, CCflag_code_mask, \
1500 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1501 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1502 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1507 unsigned short opcode
;
1518 #define CC2stat_opcode 0x0300
1519 #define CC2stat_cbit_bits 0
1520 #define CC2stat_cbit_mask 0x1f
1521 #define CC2stat_op_bits 5
1522 #define CC2stat_op_mask 0x3
1523 #define CC2stat_D_bits 7
1524 #define CC2stat_D_mask 0x1
1525 #define CC2stat_code_bits 8
1526 #define CC2stat_code_mask 0xff
1528 #define init_CC2stat \
1531 CC2stat_cbit_bits, CC2stat_cbit_mask, \
1532 CC2stat_op_bits, CC2stat_op_mask, \
1533 CC2stat_D_bits, CC2stat_D_mask, \
1534 CC2stat_code_bits, CC2stat_code_mask \
1539 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1540 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1541 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1546 unsigned short opcode
;
1559 #define RegMv_opcode 0x3000
1560 #define RegMv_src_bits 0
1561 #define RegMv_src_mask 0x7
1562 #define RegMv_dst_bits 3
1563 #define RegMv_dst_mask 0x7
1564 #define RegMv_gs_bits 6
1565 #define RegMv_gs_mask 0x7
1566 #define RegMv_gd_bits 9
1567 #define RegMv_gd_mask 0x7
1568 #define RegMv_code_bits 12
1569 #define RegMv_code_mask 0xf
1571 #define init_RegMv \
1574 RegMv_src_bits, RegMv_src_mask, \
1575 RegMv_dst_bits, RegMv_dst_mask, \
1576 RegMv_gs_bits, RegMv_gs_mask, \
1577 RegMv_gd_bits, RegMv_gd_mask, \
1578 RegMv_code_bits, RegMv_code_mask \
1583 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1584 | 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
1585 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1590 unsigned short opcode
;
1601 #define COMPI2opD_opcode 0x6000
1602 #define COMPI2opD_dst_bits 0
1603 #define COMPI2opD_dst_mask 0x7
1604 #define COMPI2opD_src_bits 3
1605 #define COMPI2opD_src_mask 0x7f
1606 #define COMPI2opD_op_bits 10
1607 #define COMPI2opD_op_mask 0x1
1608 #define COMPI2opD_code_bits 11
1609 #define COMPI2opD_code_mask 0x1f
1611 #define init_COMPI2opD \
1614 COMPI2opD_dst_bits, COMPI2opD_dst_mask, \
1615 COMPI2opD_src_bits, COMPI2opD_src_mask, \
1616 COMPI2opD_op_bits, COMPI2opD_op_mask, \
1617 COMPI2opD_code_bits, COMPI2opD_code_mask \
1621 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1622 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1623 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1626 typedef COMPI2opD COMPI2opP
;
1628 #define COMPI2opP_opcode 0x6800
1629 #define COMPI2opP_dst_bits 0
1630 #define COMPI2opP_dst_mask 0x7
1631 #define COMPI2opP_src_bits 3
1632 #define COMPI2opP_src_mask 0x7f
1633 #define COMPI2opP_op_bits 10
1634 #define COMPI2opP_op_mask 0x1
1635 #define COMPI2opP_code_bits 11
1636 #define COMPI2opP_code_mask 0x1f
1638 #define init_COMPI2opP \
1641 COMPI2opP_dst_bits, COMPI2opP_dst_mask, \
1642 COMPI2opP_src_bits, COMPI2opP_src_mask, \
1643 COMPI2opP_op_bits, COMPI2opP_op_mask, \
1644 COMPI2opP_code_bits, COMPI2opP_code_mask \
1649 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1650 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1651 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1656 unsigned short opcode
;
1671 #define DagMODim_opcode 0x9e60
1672 #define DagMODim_i_bits 0
1673 #define DagMODim_i_mask 0x3
1674 #define DagMODim_m_bits 2
1675 #define DagMODim_m_mask 0x3
1676 #define DagMODim_op_bits 4
1677 #define DagMODim_op_mask 0x1
1678 #define DagMODim_code2_bits 5
1679 #define DagMODim_code2_mask 0x3
1680 #define DagMODim_br_bits 7
1681 #define DagMODim_br_mask 0x1
1682 #define DagMODim_code_bits 8
1683 #define DagMODim_code_mask 0xff
1685 #define init_DagMODim \
1688 DagMODim_i_bits, DagMODim_i_mask, \
1689 DagMODim_m_bits, DagMODim_m_mask, \
1690 DagMODim_op_bits, DagMODim_op_mask, \
1691 DagMODim_code2_bits, DagMODim_code2_mask, \
1692 DagMODim_br_bits, DagMODim_br_mask, \
1693 DagMODim_code_bits, DagMODim_code_mask \
1697 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1698 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1699 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1704 unsigned short opcode
;
1713 #define DagMODik_opcode 0x9f60
1714 #define DagMODik_i_bits 0
1715 #define DagMODik_i_mask 0x3
1716 #define DagMODik_op_bits 2
1717 #define DagMODik_op_mask 0x3
1718 #define DagMODik_code_bits 3
1719 #define DagMODik_code_mask 0xfff
1721 #define init_DagMODik \
1724 DagMODik_i_bits, DagMODik_i_mask, \
1725 DagMODik_op_bits, DagMODik_op_mask, \
1726 DagMODik_code_bits, DagMODik_code_mask \
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