1 /* Header file for targets using CGEN: Cpu tools GENerator.
3 Copyright (C) 1996-2020 Free Software Foundation, Inc.
5 This file is part of GDB, the GNU debugger, and the GNU Binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "cgen/bitset.h"
27 /* ??? IWBN to replace bfd in the name. */
28 #include "bfd_stdint.h"
34 /* ??? This file requires bfd.h but only to get bfd_vma.
35 Seems like an awful lot to require just to get such a fundamental type.
36 Perhaps the definition of bfd_vma can be moved outside of bfd.h.
37 Or perhaps one could duplicate its definition in another file.
38 Until such time, this file conditionally compiles definitions that require
39 bfd_vma using __BFD_H_SEEN__. */
41 /* Enums must be defined before they can be used.
42 Allow them to be used in struct definitions, even though the enum must
44 If CGEN_ARCH isn't defined, this file is being included by something other
45 than <arch>-desc.h. */
47 /* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S.
48 The lack of spaces in the arg list is important for non-stdc systems.
49 This file is included by <arch>-desc.h.
50 It can be included independently of <arch>-desc.h, in which case the arch
51 dependent portions will be declared as "unknown_cgen_foo". */
54 #define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s)
57 /* This file contains the static (unchanging) pieces and as much other stuff
58 as we can reasonably put here. It's generally cleaner to put stuff here
59 rather than having it machine generated if possible. */
61 /* The assembler syntax is made up of expressions (duh...).
62 At the lowest level the values are mnemonics, register names, numbers, etc.
63 Above that are subexpressions, if any (an example might be the
64 "effective address" in m68k cpus). Subexpressions are wip.
65 At the second highest level are the insns themselves. Above that are
66 pseudo-insns, synthetic insns, and macros, if any. */
68 /* Lots of cpu's have a fixed insn size, or one which rarely changes,
69 and it's generally easier to handle these by treating the insn as an
70 integer type, rather than an array of characters. So we allow targets
71 to control this. When an integer type the value is in host byte order,
72 when an array of characters the value is in target byte order. */
74 typedef unsigned int CGEN_INSN_INT
;
75 typedef int64_t CGEN_INSN_LGSINT
; /* large/long SINT */
76 typedef uint64_t CGEN_INSN_LGUINT
; /* large/long UINT */
79 typedef CGEN_INSN_INT CGEN_INSN_BYTES
;
80 typedef CGEN_INSN_INT
*CGEN_INSN_BYTES_PTR
;
82 typedef unsigned char *CGEN_INSN_BYTES
;
83 typedef unsigned char *CGEN_INSN_BYTES_PTR
;
87 #define CGEN_INLINE __inline__
101 typedef struct cgen_insn CGEN_INSN
;
103 /* Opaque pointer version for use by external world. */
105 typedef struct cgen_cpu_desc
*CGEN_CPU_DESC
;
108 Attributes are used to describe various random things associated with
109 an object (ifield, hardware, operand, insn, whatever) and are specified
111 Integer attributes computed at compile time are currently all that's
112 supported, though adding string attributes and run-time computation is
113 straightforward. Integer attribute values are always host int's
114 (signed or unsigned). For portability, this means 32 bits.
115 Integer attributes are further categorized as boolean, bitset, integer,
116 and enum types. Boolean attributes appear frequently enough that they're
117 recorded in one host int. This limits the maximum number of boolean
118 attributes to 32, though that's a *lot* of attributes. */
120 /* Type of attribute values. */
122 typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE
;
123 typedef int CGEN_ATTR_VALUE_ENUM_TYPE
;
126 CGEN_ATTR_VALUE_BITSET_TYPE bitset
;
127 CGEN_ATTR_VALUE_ENUM_TYPE nonbitset
;
128 } CGEN_ATTR_VALUE_TYPE
;
130 /* Struct to record attribute information. */
134 /* Boolean attributes. */
136 /* Non-boolean integer attributes. */
137 CGEN_ATTR_VALUE_TYPE nonbool
[1];
140 /* Define a structure member for attributes with N non-boolean entries.
141 There is no maximum number of non-boolean attributes.
142 There is a maximum of 32 boolean attributes (since they are all recorded
145 #define CGEN_ATTR_TYPE(n) \
146 struct { unsigned int bool_; \
147 CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }
149 /* Return the boolean attributes. */
151 #define CGEN_ATTR_BOOLS(a) ((a)->bool_)
153 /* Non-boolean attribute numbers are offset by this much. */
155 #define CGEN_ATTR_NBOOL_OFFSET 32
157 /* Given a boolean attribute number, return its mask. */
159 #define CGEN_ATTR_MASK(attr) (1 << (attr))
161 /* Return the value of boolean attribute ATTR in ATTRS. */
163 #define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
165 /* Return value of attribute ATTR in ATTR_TABLE for OBJ.
166 OBJ is a pointer to the entity that has the attributes
167 (??? not used at present but is reserved for future purposes - eventually
168 the goal is to allow recording attributes in source form and computing
169 them lazily at runtime, not sure of the details yet). */
171 #define CGEN_ATTR_VALUE(obj, attr_table, attr) \
172 ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
173 ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
174 : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
175 #define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
176 ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
178 /* Attribute name/value tables.
179 These are used to assist parsing of descriptions at run-time. */
187 /* For each domain (ifld,hw,operand,insn), list of attributes. */
192 const CGEN_ATTR_ENTRY
* dfault
;
193 const CGEN_ATTR_ENTRY
* vals
;
196 /* Instruction set variants. */
201 /* Default instruction size (in bits).
202 This is used by the assembler when it encounters an unknown insn. */
203 unsigned int default_insn_bitsize
;
205 /* Base instruction size (in bits).
206 For non-LIW cpus this is generally the length of the smallest insn.
207 For LIW cpus its wip (work-in-progress). For the m32r its 32. */
208 unsigned int base_insn_bitsize
;
210 /* Minimum/maximum instruction size (in bits). */
211 unsigned int min_insn_bitsize
;
212 unsigned int max_insn_bitsize
;
215 /* Machine variants. */
219 /* The argument to bfd_arch_info->scan. */
220 const char *bfd_name
;
221 /* one of enum mach_attr */
223 /* parameter from mach->cpu */
224 unsigned int insn_chunk_bitsize
;
227 /* Parse result (also extraction result).
229 The result of parsing an insn is stored here.
230 To generate the actual insn, this is passed to the insert handler.
231 When printing an insn, the result of extraction is stored here.
232 To print the insn, this is passed to the print handler.
234 It is machine generated so we don't define it here,
235 but we do need a forward decl for the handler fns.
237 There is one member for each possible field in the insn.
238 The type depends on the field.
239 Also recorded here is the computed length of the insn for architectures
243 typedef struct cgen_fields CGEN_FIELDS
;
245 /* Total length of the insn, as recorded in the `fields' struct. */
246 /* ??? The field insert handler has lots of opportunities for optimization
247 if it ever gets inlined. On architectures where insns all have the same
248 size, may wish to detect that and make this macro a constant - to allow
249 further optimizations. */
251 #define CGEN_FIELDS_BITSIZE(fields) ((fields)->length)
253 /* Extraction support for variable length insn sets. */
255 /* When disassembling we don't know the number of bytes to read at the start.
256 So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest
257 are read when needed. This struct controls this. It is basically the
258 disassemble_info stuff, except that we provide a cache for values already
259 read (since bytes can typically be read several times to fetch multiple
260 operands that may be in them), and that extraction of fields is needed
261 in contexts other than disassembly. */
264 /* A pointer to the disassemble_info struct.
265 We don't require dis-asm.h so we use void * for the type here.
266 If NULL, BYTES is full of valid data (VALID == -1). */
268 /* Points to a working buffer of sufficient size. */
269 unsigned char *insn_bytes
;
270 /* Mask of bytes that are valid in INSN_BYTES. */
274 /* Associated with each insn or expression is a set of "handlers" for
275 performing operations like parsing, printing, etc. These require a bfd_vma
276 value to be passed around but we don't want all applications to need bfd.h.
277 So this stuff is only provided if bfd.h has been included. */
280 CD is a cpu table descriptor.
281 INSN is a pointer to a struct describing the insn being parsed.
282 STRP is a pointer to a pointer to the text being parsed.
283 FIELDS is a pointer to a cgen_fields struct in which the results are placed.
284 If the expression is successfully parsed, *STRP is updated.
285 If not it is left alone.
286 The result is NULL if success or an error message. */
287 typedef const char * (cgen_parse_fn
)
288 (CGEN_CPU_DESC
, const CGEN_INSN
*insn_
,
289 const char **strp_
, CGEN_FIELDS
*fields_
);
292 CD is a cpu table descriptor.
293 INSN is a pointer to a struct describing the insn being parsed.
294 FIELDS is a pointer to a cgen_fields struct from which the values
296 INSNP is a pointer to a buffer in which to place the insn.
297 PC is the pc value of the insn.
298 The result is an error message or NULL if success. */
300 #ifdef __BFD_H_SEEN__
301 typedef const char * (cgen_insert_fn
)
302 (CGEN_CPU_DESC
, const CGEN_INSN
*insn_
,
303 CGEN_FIELDS
*fields_
, CGEN_INSN_BYTES_PTR insnp_
,
306 typedef const char * (cgen_insert_fn
) ();
310 CD is a cpu table descriptor.
311 INSN is a pointer to a struct describing the insn being parsed.
312 The second argument is a pointer to a struct controlling extraction
313 (only used for variable length insns).
314 EX_INFO is a pointer to a struct for controlling reading of further
316 BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order).
317 FIELDS is a pointer to a cgen_fields struct in which the results are placed.
318 PC is the pc value of the insn.
319 The result is the length of the insn in bits or zero if not recognized. */
321 #ifdef __BFD_H_SEEN__
322 typedef int (cgen_extract_fn
)
323 (CGEN_CPU_DESC
, const CGEN_INSN
*insn_
,
324 CGEN_EXTRACT_INFO
*ex_info_
, CGEN_INSN_INT base_insn_
,
325 CGEN_FIELDS
*fields_
, bfd_vma pc_
);
327 typedef int (cgen_extract_fn
) ();
331 CD is a cpu table descriptor.
332 INFO is a pointer to the disassembly info.
333 Eg: disassemble_info. It's defined as `PTR' so this file can be included
335 INSN is a pointer to a struct describing the insn being printed.
336 FIELDS is a pointer to a cgen_fields struct.
337 PC is the pc value of the insn.
338 LEN is the length of the insn, in bits. */
340 #ifdef __BFD_H_SEEN__
341 typedef void (cgen_print_fn
)
342 (CGEN_CPU_DESC
, void * info_
, const CGEN_INSN
*insn_
,
343 CGEN_FIELDS
*fields_
, bfd_vma pc_
, int len_
);
345 typedef void (cgen_print_fn
) ();
348 /* Parse/insert/extract/print handlers.
350 Indices into the handler tables.
351 We could use pointers here instead, but 90% of them are generally identical
352 and that's a lot of redundant data. Making these unsigned char indices
353 into tables of pointers saves a bit of space.
354 Using indices also keeps assembler code out of the disassembler and
357 struct cgen_opcode_handler
359 unsigned char parse
, insert
, extract
, print
;
362 /* Assembler interface.
364 The interface to the assembler is intended to be clean in the sense that
365 libopcodes.a is a standalone entity and could be used with any assembler.
366 Not that one would necessarily want to do that but rather that it helps
367 keep a clean interface. The interface will obviously be slanted towards
368 GAS, but at least it's a start.
369 ??? Note that one possible user of the assembler besides GAS is GDB.
371 Parsing is controlled by the assembler which calls
372 CGEN_SYM (assemble_insn). If it can parse and build the entire insn
373 it doesn't call back to the assembler. If it needs/wants to call back
374 to the assembler, cgen_parse_operand_fn is called which can either
376 - return a number to be inserted in the insn
377 - return a "register" value to be inserted
378 (the register might not be a register per pe)
379 - queue the argument and return a marker saying the expression has been
380 queued (eg: a fix-up)
381 - return an error message indicating the expression wasn't recognizable
383 The result is an error message or NULL for success.
384 The parsed value is stored in the bfd_vma *. */
386 /* Values for indicating what the caller wants. */
388 enum cgen_parse_operand_type
390 CGEN_PARSE_OPERAND_INIT
,
391 CGEN_PARSE_OPERAND_INTEGER
,
392 CGEN_PARSE_OPERAND_ADDRESS
,
393 CGEN_PARSE_OPERAND_SYMBOLIC
396 /* Values for indicating what was parsed. */
398 enum cgen_parse_operand_result
400 CGEN_PARSE_OPERAND_RESULT_NUMBER
,
401 CGEN_PARSE_OPERAND_RESULT_REGISTER
,
402 CGEN_PARSE_OPERAND_RESULT_QUEUED
,
403 CGEN_PARSE_OPERAND_RESULT_ERROR
406 #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */
407 typedef const char * (cgen_parse_operand_fn
)
409 enum cgen_parse_operand_type
, const char **, int, int,
410 enum cgen_parse_operand_result
*, bfd_vma
*);
412 typedef const char * (cgen_parse_operand_fn
) ();
415 /* Set the cgen_parse_operand_fn callback. */
417 extern void cgen_set_parse_operand_fn
418 (CGEN_CPU_DESC
, cgen_parse_operand_fn
);
420 /* Called before trying to match a table entry with the insn. */
422 extern void cgen_init_parse_operand (CGEN_CPU_DESC
);
424 /* Operand values (keywords, integers, symbols, etc.) */
426 /* Types of assembler elements. */
430 CGEN_ASM_NONE
, CGEN_ASM_KEYWORD
, CGEN_ASM_MAX
434 enum cgen_hw_type
{ CGEN_HW_MAX
};
437 /* List of hardware elements. */
442 enum cgen_hw_type type
;
443 /* There is currently no example where both index specs and value specs
444 are required, so for now both are clumped under "asm_data". */
445 enum cgen_asm_type asm_type
;
447 #ifndef CGEN_HW_NBOOL_ATTRS
448 #define CGEN_HW_NBOOL_ATTRS 1
450 CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS
) attrs
;
451 #define CGEN_HW_ATTRS(hw) (&(hw)->attrs)
454 /* Return value of attribute ATTR in HW. */
456 #define CGEN_HW_ATTR_VALUE(hw, attr) \
457 CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))
459 /* Table of hardware elements for selected mach, computed at runtime.
460 enum cgen_hw_type is an index into this table (specifically `entries'). */
463 /* Pointer to null terminated table of all compiled in entries. */
464 const CGEN_HW_ENTRY
*init_entries
;
465 unsigned int entry_size
; /* since the attribute member is variable sized */
466 /* Array of all entries, initial and run-time added. */
467 const CGEN_HW_ENTRY
**entries
;
468 /* Number of elements in `entries'. */
469 unsigned int num_entries
;
470 /* For now, xrealloc is called each time a new entry is added at runtime.
471 ??? May wish to keep track of some slop to reduce the number of calls to
472 xrealloc, except that there's unlikely to be many and not expected to be
473 in speed critical code. */
476 extern const CGEN_HW_ENTRY
* cgen_hw_lookup_by_name
477 (CGEN_CPU_DESC
, const char *);
478 extern const CGEN_HW_ENTRY
* cgen_hw_lookup_by_num
479 (CGEN_CPU_DESC
, unsigned int);
481 /* This struct is used to describe things like register names, etc. */
483 typedef struct cgen_keyword_entry
485 /* Name (as in register name). */
488 /* Value (as in register number).
489 The value cannot be -1 as that is used to indicate "not found".
490 IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */
494 This should, but technically needn't, appear last. It is a variable sized
495 array in that one architecture may have 1 nonbool attribute and another
496 may have more. Having this last means the non-architecture specific code
497 needn't care. The goal is to eventually record
498 attributes in their raw form, evaluate them at run-time, and cache the
499 values, so this worry will go away anyway. */
500 /* ??? Moving this last should be done by treating keywords like insn lists
501 and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */
502 /* FIXME: Not used yet. */
503 #ifndef CGEN_KEYWORD_NBOOL_ATTRS
504 #define CGEN_KEYWORD_NBOOL_ATTRS 1
506 CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS
) attrs
;
508 /* ??? Putting these here means compiled in entries can't be const.
509 Not a really big deal, but something to consider. */
510 /* Next name hash table entry. */
511 struct cgen_keyword_entry
*next_name
;
512 /* Next value hash table entry. */
513 struct cgen_keyword_entry
*next_value
;
514 } CGEN_KEYWORD_ENTRY
;
516 /* Top level struct for describing a set of related keywords
517 (e.g. register names).
519 This struct supports run-time entry of new values, and hashed lookups. */
521 typedef struct cgen_keyword
523 /* Pointer to initial [compiled in] values. */
524 CGEN_KEYWORD_ENTRY
*init_entries
;
526 /* Number of entries in `init_entries'. */
527 unsigned int num_init_entries
;
529 /* Hash table used for name lookup. */
530 CGEN_KEYWORD_ENTRY
**name_hash_table
;
532 /* Hash table used for value lookup. */
533 CGEN_KEYWORD_ENTRY
**value_hash_table
;
535 /* Number of entries in the hash_tables. */
536 unsigned int hash_table_size
;
538 /* Pointer to null keyword "" entry if present. */
539 const CGEN_KEYWORD_ENTRY
*null_entry
;
541 /* String containing non-alphanumeric characters used
543 At present, the highest number of entries used is 1. */
544 char nonalpha_chars
[8];
547 /* Structure used for searching. */
551 /* Table being searched. */
552 const CGEN_KEYWORD
*table
;
554 /* Specification of what is being searched for. */
557 /* Current index in hash table. */
558 unsigned int current_hash
;
560 /* Current element in current hash chain. */
561 CGEN_KEYWORD_ENTRY
*current_entry
;
562 } CGEN_KEYWORD_SEARCH
;
564 /* Lookup a keyword from its name. */
566 const CGEN_KEYWORD_ENTRY
*cgen_keyword_lookup_name
567 (CGEN_KEYWORD
*, const char *);
569 /* Lookup a keyword from its value. */
571 const CGEN_KEYWORD_ENTRY
*cgen_keyword_lookup_value
572 (CGEN_KEYWORD
*, int);
576 void cgen_keyword_add (CGEN_KEYWORD
*, CGEN_KEYWORD_ENTRY
*);
578 /* Keyword searching.
579 This can be used to retrieve every keyword, or a subset. */
581 CGEN_KEYWORD_SEARCH cgen_keyword_search_init
582 (CGEN_KEYWORD
*, const char *);
583 const CGEN_KEYWORD_ENTRY
*cgen_keyword_search_next
584 (CGEN_KEYWORD_SEARCH
*);
586 /* Operand value support routines. */
588 extern const char *cgen_parse_keyword
589 (CGEN_CPU_DESC
, const char **, CGEN_KEYWORD
*, long *);
590 #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */
591 extern const char *cgen_parse_signed_integer
592 (CGEN_CPU_DESC
, const char **, int, long *);
593 extern const char *cgen_parse_unsigned_integer
594 (CGEN_CPU_DESC
, const char **, int, unsigned long *);
595 extern const char *cgen_parse_address
596 (CGEN_CPU_DESC
, const char **, int, int,
597 enum cgen_parse_operand_result
*, bfd_vma
*);
598 extern const char *cgen_validate_signed_integer
600 extern const char *cgen_validate_unsigned_integer
601 (unsigned long, unsigned long, unsigned long);
606 /* ??? This duplicates the values in arch.h. Revisit.
607 These however need the CGEN_ prefix [as does everything in this file]. */
608 /* ??? Targets may need to add their own modes so we may wish to move this
609 to <arch>-opc.h, or add a hook. */
612 CGEN_MODE_VOID
, /* ??? rename simulator's VM to VOID? */
613 CGEN_MODE_BI
, CGEN_MODE_QI
, CGEN_MODE_HI
, CGEN_MODE_SI
, CGEN_MODE_DI
,
614 CGEN_MODE_UBI
, CGEN_MODE_UQI
, CGEN_MODE_UHI
, CGEN_MODE_USI
, CGEN_MODE_UDI
,
615 CGEN_MODE_SF
, CGEN_MODE_DF
, CGEN_MODE_XF
, CGEN_MODE_TF
,
616 CGEN_MODE_TARGET_MAX
,
617 CGEN_MODE_INT
, CGEN_MODE_UINT
,
621 /* FIXME: Until simulator is updated. */
623 #define CGEN_MODE_VM CGEN_MODE_VOID
628 enum cgen_operand_type
{ CGEN_OPERAND_MAX
};
631 /* "nil" indicator for the operand instance table */
632 #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
634 /* A tree of these structs represents the multi-ifield
635 structure of an operand's hw-index value, if it exists. */
639 typedef struct cgen_maybe_multi_ifield
641 int count
; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
642 n: indexed by array of more cgen_maybe_multi_ifields. */
646 const struct cgen_maybe_multi_ifield
* multi
;
647 const struct cgen_ifld
* leaf
;
650 CGEN_MAYBE_MULTI_IFLD
;
652 /* This struct defines each entry in the operand table. */
656 /* Name as it appears in the syntax string. */
660 enum cgen_operand_type type
;
662 /* The hardware element associated with this operand. */
663 enum cgen_hw_type hw_type
;
665 /* FIXME: We don't yet record ifield definitions, which we should.
666 When we do it might make sense to delete start/length (since they will
667 be duplicated in the ifield's definition) and replace them with a
668 pointer to the ifield entry. */
671 This is just a hint, and may be unused in more complex operands.
672 May be unused for a modifier. */
675 /* The number of bits in the operand.
676 This is just a hint, and may be unused in more complex operands.
677 May be unused for a modifier. */
678 unsigned char length
;
680 /* The (possibly-multi) ifield used as an index for this operand, if it
681 is indexed by a field at all. This substitutes / extends the start and
682 length fields above, but unsure at this time whether they are used
684 CGEN_MAYBE_MULTI_IFLD index_fields
;
685 #if 0 /* ??? Interesting idea but relocs tend to get too complicated,
686 and ABI dependent, for simple table lookups to work. */
687 /* Ideally this would be the internal (external?) reloc type. */
692 This should, but technically needn't, appear last. It is a variable sized
693 array in that one architecture may have 1 nonbool attribute and another
694 may have more. Having this last means the non-architecture specific code
695 needn't care, now or tomorrow. The goal is to eventually record
696 attributes in their raw form, evaluate them at run-time, and cache the
697 values, so this worry will go away anyway. */
698 #ifndef CGEN_OPERAND_NBOOL_ATTRS
699 #define CGEN_OPERAND_NBOOL_ATTRS 1
701 CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS
) attrs
;
702 #define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
705 /* Return value of attribute ATTR in OPERAND. */
707 #define CGEN_OPERAND_ATTR_VALUE(operand, attr) \
708 CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))
710 /* Table of operands for selected mach/isa, computed at runtime.
711 enum cgen_operand_type is an index into this table (specifically
715 /* Pointer to null terminated table of all compiled in entries. */
716 const CGEN_OPERAND
*init_entries
;
717 unsigned int entry_size
; /* since the attribute member is variable sized */
718 /* Array of all entries, initial and run-time added. */
719 const CGEN_OPERAND
**entries
;
720 /* Number of elements in `entries'. */
721 unsigned int num_entries
;
722 /* For now, xrealloc is called each time a new entry is added at runtime.
723 ??? May wish to keep track of some slop to reduce the number of calls to
724 xrealloc, except that there's unlikely to be many and not expected to be
725 in speed critical code. */
726 } CGEN_OPERAND_TABLE
;
728 extern const CGEN_OPERAND
* cgen_operand_lookup_by_name
729 (CGEN_CPU_DESC
, const char *);
730 extern const CGEN_OPERAND
* cgen_operand_lookup_by_num
731 (CGEN_CPU_DESC
, int);
733 /* Instruction operand instances.
735 For each instruction, a list of the hardware elements that are read and
736 written are recorded. */
738 /* The type of the instance. */
740 enum cgen_opinst_type
{
741 /* End of table marker. */
743 CGEN_OPINST_INPUT
, CGEN_OPINST_OUTPUT
748 /* Input or output indicator. */
749 enum cgen_opinst_type type
;
751 /* Name of operand. */
754 /* The hardware element referenced. */
755 enum cgen_hw_type hw_type
;
757 /* The mode in which the operand is being used. */
760 /* The operand table entry CGEN_OPERAND_NIL if there is none
761 (i.e. an explicit hardware reference). */
762 enum cgen_operand_type op_type
;
764 /* If `operand' is "nil", the index (e.g. into array of registers). */
768 ??? This perhaps should be a real attribute struct but there's
769 no current need, so we save a bit of space and just have a set of
770 flags. The interface is such that this can easily be made attributes
771 should it prove useful. */
773 #define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs)
774 /* Return value of attribute ATTR in OPINST. */
775 #define CGEN_OPINST_ATTR(opinst, attr) \
776 ((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
777 /* Operand is conditionally referenced (read/written). */
778 #define CGEN_OPINST_COND_REF 1
783 Each insn format and subexpression has one of these.
785 The syntax "string" consists of characters (n > 0 && n < 128), and operand
786 values (n >= 128), and is terminated by 0. Operand values are 128 + index
787 into the operand table. The operand table doesn't exist in C, per se, as
788 the data is recorded in the parse/insert/extract/print switch statements. */
790 /* This should be at least as large as necessary for any target. */
791 #define CGEN_MAX_SYNTAX_ELEMENTS 48
793 /* A target may know its own precise maximum. Assert that it falls below
795 #ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS
796 #if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS
797 #error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS"
801 typedef unsigned short CGEN_SYNTAX_CHAR_TYPE
;
805 CGEN_SYNTAX_CHAR_TYPE syntax
[CGEN_MAX_SYNTAX_ELEMENTS
];
808 #define CGEN_SYNTAX_STRING(syn) (syn->syntax)
809 #define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
810 #define CGEN_SYNTAX_CHAR(c) ((unsigned char)c)
811 #define CGEN_SYNTAX_FIELD(c) ((c) - 128)
812 #define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
814 /* ??? I can't currently think of any case where the mnemonic doesn't come
815 first [and if one ever doesn't building the hash tables will be tricky].
816 However, we treat mnemonics as just another operand of the instruction.
817 A value of 1 means "this is where the mnemonic appears". 1 isn't
818 special other than it's a non-printable ASCII char. */
820 #define CGEN_SYNTAX_MNEMONIC 1
821 #define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC)
823 /* Instruction fields.
825 ??? We currently don't allow adding fields at run-time.
826 Easy to fix when needed. */
828 typedef struct cgen_ifld
{
829 /* Enum of ifield. */
831 #define CGEN_IFLD_NUM(f) ((f)->num)
833 /* Name of the field, distinguishes it from all other fields. */
835 #define CGEN_IFLD_NAME(f) ((f)->name)
837 /* Default offset, in bits, from the start of the insn to the word
838 containing the field. */
840 #define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset)
842 /* Default length of the word containing the field. */
844 #define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size)
846 /* Default starting bit number.
847 Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */
849 #define CGEN_IFLD_START(f) ((f)->start)
851 /* Length of the field, in bits. */
853 #define CGEN_IFLD_LENGTH(f) ((f)->length)
855 #ifndef CGEN_IFLD_NBOOL_ATTRS
856 #define CGEN_IFLD_NBOOL_ATTRS 1
858 CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS
) attrs
;
859 #define CGEN_IFLD_ATTRS(f) (&(f)->attrs)
862 /* Return value of attribute ATTR in IFLD. */
863 #define CGEN_IFLD_ATTR_VALUE(ifld, attr) \
864 CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))
866 /* Instruction data. */
868 /* Instruction formats.
870 Instructions are grouped by format. Associated with an instruction is its
871 format. Each insn's opcode table entry contains a format table entry.
872 ??? There is usually very few formats compared with the number of insns,
873 so one can reduce the size of the opcode table by recording the format table
874 as a separate entity. Given that we currently don't, format table entries
875 are also distinguished by their operands. This increases the size of the
876 table, but reduces the number of tables. It's all minutiae anyway so it
877 doesn't really matter [at this point in time].
879 ??? Support for variable length ISA's is wip. */
881 /* Accompanying each iformat description is a list of its fields. */
884 const CGEN_IFLD
*ifld
;
885 #define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld)
888 /* This should be at least as large as necessary for any target. */
889 #define CGEN_MAX_IFMT_OPERANDS 16
891 /* A target may know its own precise maximum. Assert that it falls below
893 #ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS
894 #if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS
895 #error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS"
902 /* Length that MASK and VALUE have been calculated to
903 [VALUE is recorded elsewhere].
904 Normally it is base_insn_bitsize. On [V]LIW architectures where the base
905 insn size may be larger than the size of an insn, this field is less than
906 base_insn_bitsize. */
907 unsigned char mask_length
;
908 #define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length)
910 /* Total length of instruction, in bits. */
911 unsigned char length
;
912 #define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length)
914 /* Mask to apply to the first MASK_LENGTH bits.
915 Each insn's value is stored with the insn.
916 The first step in recognizing an insn for disassembly is
917 (opcode & mask) == value. */
919 #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
921 /* Instruction fields.
922 +1 for trailing NULL. */
923 CGEN_IFMT_IFLD iflds
[CGEN_MAX_IFMT_OPERANDS
+ 1];
924 #define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds)
927 /* Instruction values. */
931 /* The opcode portion of the base insn. */
932 CGEN_INSN_INT base_value
;
934 #ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS
935 /* Extra opcode values beyond base_value. */
936 unsigned long ifield_values
[CGEN_MAX_EXTRA_OPCODE_OPERANDS
];
940 /* Instruction opcode table.
941 This contains the syntax and format data of an instruction. */
943 /* ??? Some ports already have an opcode table yet still need to use the rest
944 of what cgen_insn has. Plus keeping the opcode data with the operand
945 instance data can create a pretty big file. So we keep them separately.
946 Not sure this is a good idea in the long run. */
950 /* Indices into parse/insert/extract/print handler tables. */
951 struct cgen_opcode_handler handlers
;
952 #define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers)
956 #define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax)
959 const CGEN_IFMT
*format
;
960 #define CGEN_OPCODE_FORMAT(opc) ((opc)->format)
961 #define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc))
962 #define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc))
963 #define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc))
965 /* Instruction opcode value. */
967 #define CGEN_OPCODE_VALUE(opc) (& (opc)->value)
968 #define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value)
969 #define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc))
972 /* Instruction attributes.
973 This is made a published type as applications can cache a pointer to
974 the attributes for speed. */
976 #ifndef CGEN_INSN_NBOOL_ATTRS
977 #define CGEN_INSN_NBOOL_ATTRS 1
979 typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS
) CGEN_INSN_ATTR_TYPE
;
981 /* Enum of architecture independent attributes. */
984 /* ??? Numbers here are recorded in two places. */
985 typedef enum cgen_insn_attr
{
988 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS))
991 /* This struct defines each entry in the instruction table. */
995 /* Each real instruction is enumerated. */
996 /* ??? This may go away in time. */
998 #define CGEN_INSN_NUM(insn) ((insn)->base->num)
1000 /* Name of entry (that distinguishes it from all other entries). */
1001 /* ??? If mnemonics have operands, try to print full mnemonic. */
1003 #define CGEN_INSN_NAME(insn) ((insn)->base->name)
1005 /* Mnemonic. This is used when parsing and printing the insn.
1006 In the case of insns that have operands on the mnemonics, this is
1007 only the constant part. E.g. for conditional execution of an `add' insn,
1008 where the full mnemonic is addeq, addne, etc., and the condition is
1009 treated as an operand, this is only "add". */
1010 const char *mnemonic
;
1011 #define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic)
1013 /* Total length of instruction, in bits. */
1015 #define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize)
1017 #if 0 /* ??? Disabled for now as there is a problem with embedded newlines
1018 and the table is already pretty big. Should perhaps be moved
1019 to a file of its own. */
1020 /* Semantics, as RTL. */
1021 /* ??? Plain text or bytecodes? */
1022 /* ??? Note that the operand instance table could be computed at run-time
1023 if we parse this and cache the results. Something to eventually do. */
1025 #define CGEN_INSN_RTX(insn) ((insn)->base->rtx)
1029 This must appear last. It is a variable sized array in that one
1030 architecture may have 1 nonbool attribute and another may have more.
1031 Having this last means the non-architecture specific code needn't
1032 care. The goal is to eventually record attributes in their raw form,
1033 evaluate them at run-time, and cache the values, so this worry will go
1035 CGEN_INSN_ATTR_TYPE attrs
;
1036 #define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs)
1037 /* Return value of attribute ATTR in INSN. */
1038 #define CGEN_INSN_ATTR_VALUE(insn, attr) \
1039 CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
1040 #define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
1041 CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
1044 /* Return non-zero if INSN is the "invalid" insn marker. */
1046 #define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0)
1048 /* Main struct contain instruction information.
1049 BASE is always present, the rest is present only if asked for. */
1053 /* ??? May be of use to put a type indicator here.
1054 Then this struct could different info for different classes of insns. */
1055 /* ??? A speedup can be had by moving `base' into this struct.
1057 const CGEN_IBASE
*base
;
1058 const CGEN_OPCODE
*opcode
;
1059 const CGEN_OPINST
*opinst
;
1061 /* Regex to disambiguate overloaded opcodes */
1063 #define CGEN_INSN_RX(insn) ((insn)->rx)
1064 #define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5)
1067 /* Instruction lists.
1068 This is used for adding new entries and for creating the hash lists. */
1070 typedef struct cgen_insn_list
1072 struct cgen_insn_list
*next
;
1073 const CGEN_INSN
*insn
;
1076 /* Table of instructions. */
1080 const CGEN_INSN
*init_entries
;
1081 unsigned int entry_size
; /* since the attribute member is variable sized */
1082 unsigned int num_init_entries
;
1083 CGEN_INSN_LIST
*new_entries
;
1086 /* Return number of instructions. This includes any added at run-time. */
1088 extern int cgen_insn_count (CGEN_CPU_DESC
);
1089 extern int cgen_macro_insn_count (CGEN_CPU_DESC
);
1091 /* Macros to access the other insn elements not recorded in CGEN_IBASE. */
1093 /* Fetch INSN's operand instance table. */
1094 /* ??? Doesn't handle insns added at runtime. */
1095 #define CGEN_INSN_OPERANDS(insn) ((insn)->opinst)
1097 /* Return INSN's opcode table entry. */
1098 #define CGEN_INSN_OPCODE(insn) ((insn)->opcode)
1100 /* Return INSN's handler data. */
1101 #define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn))
1103 /* Return INSN's syntax. */
1104 #define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn))
1106 /* Return size of base mask in bits. */
1107 #define CGEN_INSN_MASK_BITSIZE(insn) \
1108 CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn))
1110 /* Return mask of base part of INSN. */
1111 #define CGEN_INSN_BASE_MASK(insn) \
1112 CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn))
1114 /* Return value of base part of INSN. */
1115 #define CGEN_INSN_BASE_VALUE(insn) \
1116 CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn))
1118 /* Standard way to test whether INSN is supported by MACH.
1119 MACH is one of enum mach_attr.
1120 The "|1" is because the base mach is always selected. */
1121 #define CGEN_INSN_MACH_HAS_P(insn, mach) \
1122 ((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)
1124 /* Macro instructions.
1125 Macro insns aren't real insns, they map to one or more real insns.
1126 E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or
1129 Macro insns can expand to nothing (e.g. a nop that is optimized away).
1130 This is useful in multi-insn macros that build a constant in a register.
1131 Of course this isn't the default behaviour and must be explicitly enabled.
1133 Assembly of macro-insns is relatively straightforward. Disassembly isn't.
1134 However, disassembly of at least some kinds of macro insns is important
1135 in order that the disassembled code preserve the readability of the original
1136 insn. What is attempted here is to disassemble all "simple" macro-insns,
1137 where "simple" is currently defined to mean "expands to one real insn".
1139 Simple macro-insns are handled specially. They are emitted as ALIAS's
1140 of real insns. This simplifies their handling since there's usually more
1141 of them than any other kind of macro-insn, and proper disassembly of them
1142 falls out for free. */
1144 /* For each macro-insn there may be multiple expansion possibilities,
1145 depending on the arguments. This structure is accessed via the `data'
1146 member of CGEN_INSN. */
1148 typedef struct cgen_minsn_expansion
{
1149 /* Function to do the expansion.
1150 If the expansion fails (e.g. "no match") NULL is returned.
1151 Space for the expansion is obtained with malloc.
1152 It is up to the caller to free it. */
1154 (const struct cgen_minsn_expansion
*,
1155 const char *, const char **, int *,
1157 #define CGEN_MIEXPN_FN(ex) ((ex)->fn)
1159 /* Instruction(s) the macro expands to.
1160 The format of STR is defined by FN.
1161 It is typically the assembly code of the real insn, but it could also be
1162 the original Scheme expression or a tokenized form of it (with FN being
1163 an appropriate interpreter). */
1165 #define CGEN_MIEXPN_STR(ex) ((ex)->str)
1166 } CGEN_MINSN_EXPANSION
;
1169 When supported, this function will convert the input string to another
1170 string and the parser will be invoked recursively. The output string
1171 may contain further macro invocations. */
1173 extern const char * cgen_expand_macro_insn
1174 (CGEN_CPU_DESC
, const struct cgen_minsn_expansion
*,
1175 const char *, const char **, int *, CGEN_OPERAND
**);
1177 /* The assembler insn table is hashed based on some function of the mnemonic
1178 (the actually hashing done is up to the target, but we provide a few
1179 examples like the first letter or a function of the entire mnemonic). */
1181 extern CGEN_INSN_LIST
* cgen_asm_lookup_insn
1182 (CGEN_CPU_DESC
, const char *);
1183 #define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string))
1184 #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next)
1186 /* The disassembler insn table is hashed based on some function of machine
1187 instruction (the actually hashing done is up to the target). */
1189 extern CGEN_INSN_LIST
* cgen_dis_lookup_insn
1190 (CGEN_CPU_DESC
, const char *, CGEN_INSN_INT
);
1191 /* FIXME: delete these two */
1192 #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value))
1193 #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next)
1195 /* The CPU description.
1196 A copy of this is created when the cpu table is "opened".
1197 All global state information is recorded here.
1198 Access macros are provided for "public" members. */
1200 typedef struct cgen_cpu_desc
1202 /* Bitmap of selected machine(s) (a la BFD machine number). */
1205 /* Bitmap of selected isa(s). */
1207 #define CGEN_CPU_ISAS(cd) ((cd)->isas)
1209 /* Current endian. */
1210 enum cgen_endian endian
;
1211 #define CGEN_CPU_ENDIAN(cd) ((cd)->endian)
1213 /* Current insn endian. */
1214 enum cgen_endian insn_endian
;
1215 #define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian)
1217 /* Word size (in bits). */
1218 /* ??? Or maybe maximum word size - might we ever need to allow a cpu table
1219 to be opened for both sparc32/sparc64?
1220 ??? Another alternative is to create a table of selected machs and
1221 lazily fetch the data from there. */
1222 unsigned int word_bitsize
;
1224 /* Instruction chunk size (in bits), for purposes of endianness
1226 unsigned int insn_chunk_bitsize
;
1228 /* Indicator if sizes are unknown.
1229 This is used by default_insn_bitsize,base_insn_bitsize if there is a
1230 difference between the selected isa's. */
1231 #define CGEN_SIZE_UNKNOWN 65535
1233 /* Default instruction size (in bits).
1234 This is used by the assembler when it encounters an unknown insn. */
1235 unsigned int default_insn_bitsize
;
1237 /* Base instruction size (in bits).
1238 For non-LIW cpus this is generally the length of the smallest insn.
1239 For LIW cpus its wip (work-in-progress). For the m32r its 32. */
1240 unsigned int base_insn_bitsize
;
1242 /* Minimum/maximum instruction size (in bits). */
1243 unsigned int min_insn_bitsize
;
1244 unsigned int max_insn_bitsize
;
1246 /* Instruction set variants. */
1247 const CGEN_ISA
*isa_table
;
1249 /* Machine variants. */
1250 const CGEN_MACH
*mach_table
;
1252 /* Hardware elements. */
1253 CGEN_HW_TABLE hw_table
;
1255 /* Instruction fields. */
1256 const CGEN_IFLD
*ifld_table
;
1259 CGEN_OPERAND_TABLE operand_table
;
1261 /* Main instruction table. */
1262 CGEN_INSN_TABLE insn_table
;
1263 #define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table)
1265 /* Macro instructions are defined separately and are combined with real
1266 insns during hash table computation. */
1267 CGEN_INSN_TABLE macro_insn_table
;
1269 /* Copy of CGEN_INT_INSN_P. */
1272 /* Called to rebuild the tables after something has changed. */
1273 void (*rebuild_tables
) (CGEN_CPU_DESC
);
1275 /* Operand parser callback. */
1276 cgen_parse_operand_fn
* parse_operand_fn
;
1278 /* Parse/insert/extract/print cover fns for operands. */
1279 const char * (*parse_operand
)
1280 (CGEN_CPU_DESC
, int opindex_
, const char **, CGEN_FIELDS
*fields_
);
1281 #ifdef __BFD_H_SEEN__
1282 const char * (*insert_operand
)
1283 (CGEN_CPU_DESC
, int opindex_
, CGEN_FIELDS
*fields_
,
1284 CGEN_INSN_BYTES_PTR
, bfd_vma pc_
);
1285 int (*extract_operand
)
1286 (CGEN_CPU_DESC
, int opindex_
, CGEN_EXTRACT_INFO
*, CGEN_INSN_INT
,
1287 CGEN_FIELDS
*fields_
, bfd_vma pc_
);
1288 void (*print_operand
)
1289 (CGEN_CPU_DESC
, int opindex_
, void * info_
, CGEN_FIELDS
* fields_
,
1290 void const *attrs_
, bfd_vma pc_
, int length_
);
1292 const char * (*insert_operand
) ();
1293 int (*extract_operand
) ();
1294 void (*print_operand
) ();
1296 #define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand)
1297 #define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand)
1298 #define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand)
1299 #define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand)
1301 /* Size of CGEN_FIELDS struct. */
1302 unsigned int sizeof_fields
;
1303 #define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields)
1305 /* Set the bitsize field. */
1306 void (*set_fields_bitsize
) (CGEN_FIELDS
*fields_
, int size_
);
1307 #define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize)
1309 /* CGEN_FIELDS accessors. */
1310 int (*get_int_operand
)
1311 (CGEN_CPU_DESC
, int opindex_
, const CGEN_FIELDS
*fields_
);
1312 void (*set_int_operand
)
1313 (CGEN_CPU_DESC
, int opindex_
, CGEN_FIELDS
*fields_
, int value_
);
1314 #ifdef __BFD_H_SEEN__
1315 bfd_vma (*get_vma_operand
)
1316 (CGEN_CPU_DESC
, int opindex_
, const CGEN_FIELDS
*fields_
);
1317 void (*set_vma_operand
)
1318 (CGEN_CPU_DESC
, int opindex_
, CGEN_FIELDS
*fields_
, bfd_vma value_
);
1320 long (*get_vma_operand
) ();
1321 void (*set_vma_operand
) ();
1323 #define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand)
1324 #define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand)
1325 #define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand)
1326 #define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand)
1328 /* Instruction parse/insert/extract/print handlers. */
1329 /* FIXME: make these types uppercase. */
1330 cgen_parse_fn
* const *parse_handlers
;
1331 cgen_insert_fn
* const *insert_handlers
;
1332 cgen_extract_fn
* const *extract_handlers
;
1333 cgen_print_fn
* const *print_handlers
;
1334 #define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse])
1335 #define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert])
1336 #define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract])
1337 #define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print])
1339 /* Return non-zero if insn should be added to hash table. */
1340 int (* asm_hash_p
) (const CGEN_INSN
*);
1342 /* Assembler hash function. */
1343 unsigned int (* asm_hash
) (const char *);
1345 /* Number of entries in assembler hash table. */
1346 unsigned int asm_hash_size
;
1348 /* Return non-zero if insn should be added to hash table. */
1349 int (* dis_hash_p
) (const CGEN_INSN
*);
1351 /* Disassembler hash function. */
1352 unsigned int (* dis_hash
) (const char *, CGEN_INSN_INT
);
1354 /* Number of entries in disassembler hash table. */
1355 unsigned int dis_hash_size
;
1357 /* Assembler instruction hash table. */
1358 CGEN_INSN_LIST
**asm_hash_table
;
1359 CGEN_INSN_LIST
*asm_hash_table_entries
;
1361 /* Disassembler instruction hash table. */
1362 CGEN_INSN_LIST
**dis_hash_table
;
1363 CGEN_INSN_LIST
*dis_hash_table_entries
;
1365 /* This field could be turned into a bitfield if room for other flags is needed. */
1366 unsigned int signed_overflow_ok_p
;
1371 #ifndef CGEN_WORD_ENDIAN
1372 #define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd)
1374 #ifndef CGEN_INSN_WORD_ENDIAN
1375 #define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd)
1378 /* Prototypes of major functions. */
1379 /* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC.
1380 Not the init fns though, as that would drag in things that mightn't be
1381 used and might not even exist. */
1383 /* Argument types to cpu_open. */
1385 enum cgen_cpu_open_arg
{
1387 /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */
1389 /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */
1390 CGEN_CPU_OPEN_MACHS
,
1391 /* Select machine, arg is mach's bfd name.
1392 Multiple machines can be specified by repeated use. */
1393 CGEN_CPU_OPEN_BFDMACH
,
1394 /* Select endian, arg is CGEN_ENDIAN_*. */
1395 CGEN_CPU_OPEN_ENDIAN
,
1396 /* Select instruction endian, arg is CGEN_ENDIAN_*. */
1397 CGEN_CPU_OPEN_INSN_ENDIAN
,
1400 /* Open a cpu descriptor table for use.
1401 ??? We only support ISO C stdargs here, not K&R.
1402 Laziness, plus experiment to see if anything requires K&R - eventually
1403 K&R will no longer be supported - e.g. GDB is currently trying this. */
1405 extern CGEN_CPU_DESC
CGEN_SYM (cpu_open
) (enum cgen_cpu_open_arg
, ...);
1407 /* Cover fn to handle simple case. */
1409 extern CGEN_CPU_DESC
CGEN_SYM (cpu_open_1
)
1410 (const char *mach_name_
, enum cgen_endian endian_
);
1414 extern void CGEN_SYM (cpu_close
) (CGEN_CPU_DESC
);
1416 /* Initialize the opcode table for use.
1417 Called by init_asm/init_dis. */
1419 extern void CGEN_SYM (init_opcode_table
) (CGEN_CPU_DESC cd_
);
1421 /* build the insn selection regex.
1422 called by init_opcode_table */
1424 extern char * CGEN_SYM(build_insn_regex
) (CGEN_INSN
*insn_
);
1426 /* Initialize the ibld table for use.
1427 Called by init_asm/init_dis. */
1429 extern void CGEN_SYM (init_ibld_table
) (CGEN_CPU_DESC cd_
);
1431 /* Initialize an cpu table for assembler or disassembler use.
1432 These must be called immediately after cpu_open. */
1434 extern void CGEN_SYM (init_asm
) (CGEN_CPU_DESC
);
1435 extern void CGEN_SYM (init_dis
) (CGEN_CPU_DESC
);
1437 /* Initialize the operand instance table for use. */
1439 extern void CGEN_SYM (init_opinst_table
) (CGEN_CPU_DESC cd_
);
1441 /* Assemble an instruction. */
1443 extern const CGEN_INSN
* CGEN_SYM (assemble_insn
)
1444 (CGEN_CPU_DESC
, const char *, CGEN_FIELDS
*,
1445 CGEN_INSN_BYTES_PTR
, char **);
1447 extern const CGEN_KEYWORD
CGEN_SYM (operand_mach
);
1448 extern int CGEN_SYM (get_mach
) (const char *);
1450 /* Operand index computation. */
1451 extern const CGEN_INSN
* cgen_lookup_insn
1452 (CGEN_CPU_DESC
, const CGEN_INSN
* insn_
,
1453 CGEN_INSN_INT int_value_
, unsigned char *bytes_value_
,
1454 int length_
, CGEN_FIELDS
*fields_
, int alias_p_
);
1455 extern void cgen_get_insn_operands
1456 (CGEN_CPU_DESC
, const CGEN_INSN
* insn_
,
1457 const CGEN_FIELDS
*fields_
, int *indices_
);
1458 extern const CGEN_INSN
* cgen_lookup_get_insn_operands
1459 (CGEN_CPU_DESC
, const CGEN_INSN
*insn_
,
1460 CGEN_INSN_INT int_value_
, unsigned char *bytes_value_
,
1461 int length_
, int *indices_
, CGEN_FIELDS
*fields_
);
1463 /* Cover fns to bfd_get/set. */
1465 extern CGEN_INSN_INT cgen_get_insn_value
1466 (CGEN_CPU_DESC
, unsigned char *, int);
1467 extern void cgen_put_insn_value
1468 (CGEN_CPU_DESC
, unsigned char *, int, CGEN_INSN_INT
);
1470 extern CGEN_INSN_INT cgen_get_base_insn_value
1471 (CGEN_CPU_DESC
, unsigned char *, int);
1472 extern void cgen_put_base_insn_value
1473 (CGEN_CPU_DESC
, unsigned char *, int, CGEN_INSN_INT
);
1475 /* Read in a cpu description file.
1476 ??? For future concerns, including adding instructions to the assembler/
1477 disassembler at run-time. */
1479 extern const char * cgen_read_cpu_file (CGEN_CPU_DESC
, const char * filename_
);
1481 /* Allow signed overflow of instruction fields. */
1482 extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC
);
1484 /* Generate an error message if a signed field in an instruction overflows. */
1485 extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC
);
1487 /* Will an error message be generated if a signed field in an instruction overflows ? */
1488 extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC
);
1494 #endif /* OPCODE_CGEN_H */