1 /* crx.h -- Header file for CRX opcode and register tables.
2 Copyright 2004 Free Software Foundation, Inc.
3 Contributed by Tomer Levi, NSC, Israel.
4 Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
5 Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
7 This file is part of GAS, GDB and the GNU binutils.
9 GAS, GDB, and GNU binutils is free software; you can redistribute it
10 and/or modify it under the terms of the GNU General Public License as
11 published by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GAS, GDB, and GNU binutils are distributed in the hope that they will be
15 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 /* CRX core/debug Registers :
27 The enums are used as indices to CRX registers table (crx_regtab).
28 Therefore, order MUST be preserved. */
32 /* 32-bit general purpose registers. */
33 r0
, r1
, r2
, r3
, r4
, r5
, r6
, r7
, r8
, r9
,
34 r10
, r11
, r12
, r13
, r14
, r15
, ra
, sp
,
35 /* 32-bit user registers. */
36 u0
, u1
, u2
, u3
, u4
, u5
, u6
, u7
, u8
, u9
,
37 u10
, u11
, u12
, u13
, u14
, u15
, ura
, usp
,
38 /* hi and lo registers. */
40 /* hi and lo user registers. */
42 /* Processor Status Register. */
44 /* Configuration Register. */
46 /* Coprocessor Configuration Register. */
48 /* Cashe Configuration Register. */
50 /* Interrupt Base Register. */
52 /* Interrupt Stack Pointer Register. */
54 /* Coprocessor Enable Register. */
56 /* Program Counter Register. */
64 /* CRX Coprocessor registers and special registers :
65 The enums are used as indices to CRX coprocessor registers table
66 (crx_copregtab). Therefore, order MUST be preserved. */
70 /* Coprocessor registers. */
71 c0
= MAX_REG
, c1
, c2
, c3
, c4
, c5
, c6
, c7
, c8
,
72 c9
, c10
, c11
, c12
, c13
, c14
, c15
,
73 /* Coprocessor special registers. */
74 cs0
, cs1
,cs2
, cs3
, cs4
, cs5
, cs6
, cs7
, cs8
,
75 cs9
, cs10
, cs11
, cs12
, cs13
, cs14
, cs15
,
76 /* Not a Coprocessor register. */
82 /* CRX Register types. */
86 CRX_PC_REGTYPE
, /* pc type */
87 CRX_R_REGTYPE
, /* r<N> */
88 CRX_U_REGTYPE
, /* u<N> */
89 CRX_C_REGTYPE
, /* c<N> */
90 CRX_CS_REGTYPE
, /* cs<N> */
91 CRX_MTPR_REGTYPE
, /* mtpr */
92 CRX_CFG_REGTYPE
/* *hi|lo, *cfg, psr */
96 /* CRX argument types :
97 The argument types correspond to instructions operands
105 rbase - register base
107 copr - coprocessor register
108 copsr - coprocessor special register. */
112 arg_r
, arg_c
, arg_cr
, arg_dc
, arg_dcr
, arg_sc
,
113 arg_ic
, arg_icr
, arg_rbase
, arg_copr
, arg_copsr
,
114 /* Not an argument. */
119 /* CRX operand types :
120 The operand types correspond to instructions operands
123 cst4 - 4-bit encoded constant
124 iN - N-bit immediate field
125 d, dispsN - N-bit immediate signed displacement
126 dispuN - N-bit immediate unsigned displacement
127 absN - N-bit absolute address
128 rbase - 4-bit genaral-purpose register specifier
129 regr - 4-bit genaral-purpose register specifier
130 regr8 - 8-bit register address space
131 copregr - coprocessor register
132 copsregr - coprocessor special register
133 scl2 - 2-bit scaling factor for memory index
134 ridx - register index. */
139 /* Immediate operands. */
141 /* Unsigned immediate operands. */
143 /* Signed displacement operands. */
144 d5
, d9
, d17
, d25
, d33
,
145 /* Absolute operands. */
147 /* Register relative operands. */
149 rbase_dispu8
, rbase_dispu12
, rbase_dispu16
, rbase_dispu28
, rbase_dispu32
,
150 /* Index operands. */
151 rbase_ridx_scl2_dispu6
, rbase_ridx_scl2_dispu22
,
152 /* Register and processor register operands. */
153 regr
, regr8
, copregr
,copregr8
,copsregr
,
154 /* Not an operand. */
156 /* Maximum supported operand. */
161 /* CRX instruction types. */
164 #define LD_STOR_INS 2
166 #define ARITH_BYTE_INS 4
169 #define BRANCH_NEQ_INS 7
170 #define LD_STOR_INS_INC 8
171 #define STOR_IMM_INS 9
172 #define CSTBIT_INS 10
177 #define COP_BRANCH_INS 15
178 #define COP_REG_INS 16
179 #define COPS_REG_INS 17
180 #define DCR_BRANCH_INS 18
184 /* Maximum value supported for instruction types. */
185 #define CRX_INS_MAX (1 << 5)
186 /* Mask to record an instruction type. */
187 #define CRX_INS_MASK (CRX_INS_MAX - 1)
188 /* Return instruction type, given instruction's attributes. */
189 #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
191 /* Indicates whether this instruction has a register list as parameter. */
192 #define REG_LIST CRX_INS_MAX
193 /* The operands in binary and assembly are placed in reverse order.
194 load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
195 #define REVERSE_MATCH (REG_LIST << 1)
197 /* Kind of displacement map used DISPU[BWD]4. */
198 #define DISPUB4 (REVERSE_MATCH << 1)
199 #define DISPUW4 (DISPUB4 << 1)
200 #define DISPUD4 (DISPUW4 << 1)
201 #define CST4MAP (DISPUB4 | DISPUW4 | DISPUD4)
203 /* Printing formats, where the instruction prefix isn't consecutive. */
204 #define FMT_1 (DISPUD4 << 1) /* 0xF0F00000 */
205 #define FMT_2 (FMT_1 << 1) /* 0xFFF0FF00 */
206 #define FMT_3 (FMT_2 << 1) /* 0xFFF00F00 */
207 #define FMT_4 (FMT_3 << 1) /* 0xFFF0F000 */
208 #define FMT_5 (FMT_4 << 1) /* 0xFFF0FFF0 */
209 #define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
211 #define RELAXABLE (FMT_5 << 1)
213 /* Maximum operands per instruction. */
214 #define MAX_OPERANDS 5
215 /* Maximum words per instruction. */
217 /* Maximum register name length. */
218 #define MAX_REGNAME_LEN 10
219 /* Maximum instruction length. */
220 #define MAX_INST_LEN 256
222 /* Single operand description. */
227 operand_type op_type
;
228 /* Operand location within the opcode. */
233 /* Instruction data structure used in instruction table. */
238 const char *mnemonic
;
239 /* Size (in words). */
241 /* Constant prefix (matched by the disassembler). */
243 /* Match size (in bits). */
247 /* Operands (always last, so unreferenced operands are initialized). */
248 operand_desc operands
[MAX_OPERANDS
];
252 /* Data structure for a single instruction's arguments (Operands). */
256 /* Register or base register. */
258 /* Index register. */
260 /* Coprocessor register. */
262 /* Constant/immediate/absolute value. */
263 unsigned long int constant
;
264 /* Scaled index mode. */
268 /* Size of the argument (in bits) required to represent. */
270 /* Indicates whether a constant is positive or negative. */
275 /* Internal structure to hold the various entities
276 corresponding to the current assembling instruction. */
280 /* Number of arguments. */
282 /* The argument data structure for storing args (operands). */
283 argument arg
[MAX_OPERANDS
];
284 /* The following fields are required only by CRX-assembler. */
286 /* Expression used for setting the fixups (if any). */
288 bfd_reloc_code_real_type rtype
;
290 /* Instruction size (in bytes). */
295 /* Structure to hold information about predefined operands. */
299 /* Size (in bits). */
300 unsigned int bit_size
;
306 /* Structure to hold trap handler information. */
312 /* Index in dispatch table. */
317 /* Structure to hold information about predefined registers. */
321 /* Name (string representation). */
323 /* Value (enum representation). */
328 /* Coprocessor register. */
331 /* Register image. */
338 /* Structure to hold a cst4 operand mapping. */
342 /* The binary value which is written to the object file. */
344 /* The value which is mapped. */
349 /* CRX opcode table. */
350 extern const inst crx_instruction
[];
351 extern const int crx_num_opcodes
;
352 #define NUMOPCODES crx_num_opcodes
354 /* CRX operands table. */
355 extern const operand_entry crx_optab
[];
357 /* CRX registers table. */
358 extern const reg_entry crx_regtab
[];
359 extern const int crx_num_regs
;
360 #define NUMREGS crx_num_regs
362 /* CRX coprocessor registers table. */
363 extern const reg_entry crx_copregtab
[];
364 extern const int crx_num_copregs
;
365 #define NUMCOPREGS crx_num_copregs
367 /* CRX trap/interrupt table. */
368 extern const trap_entry crx_traps
[];
369 extern const int crx_num_traps
;
370 #define NUMTRAPS crx_num_traps
372 /* cst4 operand mapping. */
373 extern const cst4_entry cst4_map
[];
374 extern const int cst4_maps
;
376 /* Current instruction we're assembling. */
377 extern const inst
*instruction
;
379 /* A macro for representing the instruction "constant" opcode, that is,
380 the FIXED part of the instruction. The "constant" opcode is represented
381 as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
383 #define BIN(OPC,SHIFT) (OPC << SHIFT)
385 /* Is the current instruction type is TYPE ? */
386 #define IS_INSN_TYPE(TYPE) \
387 (CRX_INS_TYPE(instruction->flags) == TYPE)
389 /* Is the current instruction mnemonic is MNEMONIC ? */
390 #define IS_INSN_MNEMONIC(MNEMONIC) \
391 (strcmp(instruction->mnemonic,MNEMONIC) == 0)
393 /* Does the current instruction has register list ? */
394 #define INST_HAS_REG_LIST \
395 (instruction->flags & REG_LIST)
397 /* Long long type handling. */
398 /* Replace all appearances of 'long long int' with LONGLONG. */
399 typedef long long int LONGLONG
;
400 typedef unsigned long long ULONGLONG
;