include/opcode/crx.h

   1 /* crx.h -- Header file for CRX opcode and register tables.
   2    Copyright 2004 Free Software Foundation, Inc.
   3    Contributed by Tomer Levi, NSC, Israel.
   4    Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
   5    Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
   6
   7    This file is part of GAS, GDB and the GNU binutils.
   8
   9    GAS, GDB, and GNU binutils is free software; you can redistribute it
  10    and/or modify it under the terms of the GNU General Public License as
  11    published by the Free Software Foundation; either version 2, or (at your
  12    option) any later version.
  13
  14    GAS, GDB, and GNU binutils are distributed in the hope that they will be
  15    useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef _CRX_H_
  24 #define _CRX_H_
  25
  26 /* CRX core/debug Registers :
  27    The enums are used as indices to CRX registers table (crx_regtab).
  28    Therefore, order MUST be preserved.  */
  29
  30 typedef enum
  31   {
  32     /* 32-bit general purpose registers.  */
  33     r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
  34     r10, r11, r12, r13, r14, r15, ra, sp,
  35     /* 32-bit user registers.  */
  36     u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
  37     u10, u11, u12, u13, u14, u15, ura, usp,
  38     /* hi and lo registers.  */
  39     hi, lo,
  40     /* hi and lo user registers.  */
  41     uhi, ulo,
  42     /* Processor Status Register.  */
  43     psr,
  44     /* Interrupt Base Register.  */
  45     intbase,
  46     /* Interrupt Stack Pointer Register.  */
  47     isp,
  48     /* Configuration Register.  */
  49     cfg,
  50     /* Coprocessor Configuration Register.  */
  51     cpcfg,
  52     /* Coprocessor Enable Register.  */
  53     cen,
  54     /* Not a register.  */
  55     nullregister,
  56     MAX_REG
  57   }
  58 reg;
  59
  60 /* CRX Coprocessor registers and special registers :
  61    The enums are used as indices to CRX coprocessor registers table
  62    (crx_copregtab). Therefore, order MUST be preserved.  */
  63
  64 typedef enum
  65   {
  66     /* Coprocessor registers.  */
  67     c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
  68     c9, c10, c11, c12, c13, c14, c15,
  69     /* Coprocessor special registers.  */
  70     cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
  71     cs9, cs10, cs11, cs12, cs13, cs14, cs15,
  72     /* Not a Coprocessor register.  */
  73     nullcopregister,
  74     MAX_COPREG
  75   }
  76 copreg;
  77
  78 /* CRX Register types. */
  79
  80 typedef enum
  81   {
  82     CRX_R_REGTYPE,    /*  r<N>    */
  83     CRX_U_REGTYPE,    /*  u<N>    */
  84     CRX_C_REGTYPE,    /*  c<N>    */
  85     CRX_CS_REGTYPE,   /*  cs<N>   */
  86     CRX_CFG_REGTYPE   /*  configuration register   */
  87   }
  88 reg_type;
  89
  90 /* CRX argument types :
  91    The argument types correspond to instructions operands
  92
  93    Argument types :
  94    r - register
  95    c - constant
  96    i - immediate
  97    idxr - index register
  98    rbase - register base
  99    s - star ('*')
 100    copr - coprocessor register
 101    copsr - coprocessor special register.  */
 102
 103 typedef enum
 104   {
 105     arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc,
 106     arg_idxr, arg_rbase, arg_copr, arg_copsr,
 107     /* Not an argument.  */
 108     nullargs
 109   }
 110 argtype;
 111
 112 /* CRX operand types :
 113    The operand types correspond to instructions operands.  */
 114
 115 typedef enum
 116   {
 117     dummy,
 118     /* 4-bit encoded constant.  */
 119     cst4,
 120     /* N-bit immediate.  */
 121     i16, i32,
 122     /* N-bit unsigned immediate.  */
 123     ui3, ui4, ui5, ui16,
 124     /* N-bit signed displacement.  */
 125     disps9, disps17, disps25, disps32,
 126     /* N-bit unsigned displacement.  */
 127     dispu5,
 128     /* N-bit escaped displacement.  */
 129     dispe9,
 130     /* N-bit absolute address.  */
 131     abs16, abs32,
 132     /* Register relative.  */
 133     rbase, rbase_cst4,
 134     rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
 135     /* Register index.  */
 136     rindex_disps6, rindex_disps22,
 137     /* 4-bit genaral-purpose register specifier.  */
 138     regr,
 139     /* 8-bit register address space.  */
 140     regr8,
 141     /* coprocessor register.  */
 142     copregr,
 143     /* coprocessor special register.  */
 144     copsregr,
 145     /* Not an operand.  */
 146     nulloperand,
 147     /* Maximum supported operand.  */
 148     MAX_OPRD
 149   }
 150 operand_type;
 151
 152 /* CRX instruction types.  */
 153
 154 #define NO_TYPE_INS       0
 155 #define ARITH_INS         1
 156 #define LD_STOR_INS       2
 157 #define BRANCH_INS        3
 158 #define ARITH_BYTE_INS    4
 159 #define CMPBR_INS         5
 160 #define SHIFT_INS         6
 161 #define BRANCH_NEQ_INS    7
 162 #define LD_STOR_INS_INC   8
 163 #define STOR_IMM_INS      9
 164 #define CSTBIT_INS       10
 165 #define SYS_INS          11
 166 #define JMP_INS          12
 167 #define MUL_INS          13
 168 #define DIV_INS          14
 169 #define COP_BRANCH_INS   15
 170 #define COP_REG_INS      16
 171 #define COPS_REG_INS     17
 172 #define DCR_BRANCH_INS   18
 173 #define MMC_INS          19
 174 #define MMU_INS          20
 175
 176 /* Maximum value supported for instruction types.  */
 177 #define CRX_INS_MAX     (1 << 5)
 178 /* Mask to record an instruction type.  */
 179 #define CRX_INS_MASK    (CRX_INS_MAX - 1)
 180 /* Return instruction type, given instruction's attributes.  */
 181 #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
 182
 183 /* Indicates whether this instruction has a register list as parameter.  */
 184 #define REG_LIST        CRX_INS_MAX
 185 /* The operands in binary and assembly are placed in reverse order.
 186    load - (REVERSE_MATCH)/store - (! REVERSE_MATCH).  */
 187 #define REVERSE_MATCH  (1 << 6)
 188
 189 /* Kind of displacement map used DISPU[BWD]4.  */
 190 #define DISPUB4        (1 << 7)
 191 #define DISPUW4        (1 << 8)
 192 #define DISPUD4        (1 << 9)
 193 #define DISPU4MAP      (DISPUB4 | DISPUW4 | DISPUD4)
 194
 195 /* Printing formats, where the instruction prefix isn't consecutive.  */
 196 #define FMT_1          (1 << 10)   /* 0xF0F00000 */
 197 #define FMT_2          (1 << 11)   /* 0xFFF0FF00 */
 198 #define FMT_3          (1 << 12)   /* 0xFFF00F00 */
 199 #define FMT_4          (1 << 13)   /* 0xFFF0F000 */
 200 #define FMT_5          (1 << 14)   /* 0xFFF0FFF0 */
 201 #define FMT_CRX        (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
 202
 203 /* Indicates whether this instruction can be relaxed.  */
 204 #define RELAXABLE      (1 << 15)
 205
 206 /* Indicates that instruction uses user registers (and not
 207    general-purpose registers) as operands.  */
 208 #define USER_REG       (1 << 16)
 209
 210 /* Indicates that instruction can perfom a cst4 mapping.  */
 211 #define CST4MAP        (1 << 17)
 212
 213 /* Instruction shouldn't allow 'sp' usage.  */
 214 #define NO_SP          (1 << 18)
 215
 216 /* Instruction shouldn't allow to push a register which is used as a rptr.  */
 217 #define NO_RPTR        (1 << 19)
 218
 219 /* Maximum operands per instruction.  */
 220 #define MAX_OPERANDS      5
 221 /* Maximum words per instruction.  */
 222 #define MAX_WORDS         3
 223 /* Maximum register name length. */
 224 #define MAX_REGNAME_LEN   10
 225 /* Maximum instruction length. */
 226 #define MAX_INST_LEN      256
 227
 228
 229 /* Values defined for the flags field of a struct operand_entry.  */
 230
 231 /* Operand must be an unsigned number.  */
 232 #define OPERAND_UNSIGNED  (1 << 0)
 233 /* Operand must be a signed number.  */
 234 #define OPERAND_SIGNED    (1 << 1)
 235 /* A cst4 operand.  */
 236 #define OPERAND_CST4      (1 << 2)
 237 /* Operand must be an even number.  */
 238 #define OPERAND_EVEN      (1 << 3)
 239 /* Operand is shifted right.  */
 240 #define OPERAND_SHIFT     (1 << 4)
 241 /* Operand is shifted right and decremented.  */
 242 #define OPERAND_SHIFT_DEC (1 << 5)
 243 /* Operand has reserved escape sequences.  */
 244 #define OPERAND_ESC       (1 << 6)
 245
 246 /* Single operand description.  */
 247
 248 typedef struct
 249   {
 250     /* Operand type.  */
 251     operand_type op_type;
 252     /* Operand location within the opcode.  */
 253     unsigned int shift;
 254   }
 255 operand_desc;
 256
 257 /* Instruction data structure used in instruction table.  */
 258
 259 typedef struct
 260   {
 261     /* Name.  */
 262     const char *mnemonic;
 263     /* Size (in words).  */
 264     unsigned int size;
 265     /* Constant prefix (matched by the disassembler).  */
 266     unsigned long match;
 267     /* Match size (in bits).  */
 268     int match_bits;
 269     /* Attributes.  */
 270     unsigned int flags;
 271     /* Operands (always last, so unreferenced operands are initialized).  */
 272     operand_desc operands[MAX_OPERANDS];
 273   }
 274 inst;
 275
 276 /* Data structure for a single instruction's arguments (Operands).  */
 277
 278 typedef struct
 279   {
 280     /* Register or base register.  */
 281     reg r;
 282     /* Index register.  */
 283     reg i_r;
 284     /* Coprocessor register.  */
 285     copreg cr;
 286     /* Constant/immediate/absolute value.  */
 287     unsigned long int constant;
 288     /* Scaled index mode.  */
 289     unsigned int scale;
 290     /* Argument type.  */
 291     argtype type;
 292     /* Size of the argument (in bits) required to represent.  */
 293     int size;
 294     /* Indicates whether a constant is positive or negative.  */
 295     int signflag;
 296   }
 297 argument;
 298
 299 /* Internal structure to hold the various entities
 300    corresponding to the current assembling instruction.  */
 301
 302 typedef struct
 303   {
 304     /* Number of arguments.  */
 305     int nargs;
 306     /* The argument data structure for storing args (operands).  */
 307     argument arg[MAX_OPERANDS];
 308 /* The following fields are required only by CRX-assembler.  */
 309 #ifdef TC_CRX
 310     /* Expression used for setting the fixups (if any).  */
 311     expressionS exp;
 312     bfd_reloc_code_real_type rtype;
 313 #endif /* TC_CRX */
 314     /* Instruction size (in bytes).  */
 315     int size;
 316   }
 317 ins;
 318
 319 /* Structure to hold information about predefined operands.  */
 320
 321 typedef struct
 322   {
 323     /* Size (in bits).  */
 324     unsigned int bit_size;
 325     /* Argument type.  */
 326     argtype arg_type;
 327     /* One bit syntax flags.  */
 328     int flags;
 329   }
 330 operand_entry;
 331
 332 /* Structure to hold trap handler information.  */
 333
 334 typedef struct
 335   {
 336     /* Trap name.  */
 337     char *name;
 338     /* Index in dispatch table.  */
 339     unsigned int entry;
 340   }
 341 trap_entry;
 342
 343 /* Structure to hold information about predefined registers.  */
 344
 345 typedef struct
 346   {
 347     /* Name (string representation).  */
 348     char *name;
 349     /* Value (enum representation).  */
 350     union
 351     {
 352       /* Register.  */
 353       reg reg_val;
 354       /* Coprocessor register.  */
 355       copreg copreg_val;
 356     } value;
 357     /* Register image.  */
 358     int image;
 359     /* Register type.  */
 360     reg_type type;
 361   }
 362 reg_entry;
 363
 364 /* Structure to hold a cst4 operand mapping.  */
 365
 366 typedef struct
 367   {
 368     /* The binary value which is written to the object file.  */
 369     int binary;
 370     /* The value which is mapped.  */
 371     int value;
 372   }
 373 cst4_entry;
 374
 375 /* CRX opcode table.  */
 376 extern const inst crx_instruction[];
 377 extern const int crx_num_opcodes;
 378 #define NUMOPCODES crx_num_opcodes
 379
 380 /* CRX operands table.  */
 381 extern const operand_entry crx_optab[];
 382
 383 /* CRX registers table.  */
 384 extern const reg_entry crx_regtab[];
 385 extern const int crx_num_regs;
 386 #define NUMREGS crx_num_regs
 387
 388 /* CRX coprocessor registers table.  */
 389 extern const reg_entry crx_copregtab[];
 390 extern const int crx_num_copregs;
 391 #define NUMCOPREGS crx_num_copregs
 392
 393 /* CRX trap/interrupt table.  */
 394 extern const trap_entry crx_traps[];
 395 extern const int crx_num_traps;
 396 #define NUMTRAPS crx_num_traps
 397
 398 /* cst4 operand mapping.  */
 399 extern const cst4_entry cst4_map[];
 400 extern const int cst4_maps;
 401
 402 /* Current instruction we're assembling.  */
 403 extern const inst *instruction;
 404
 405 /* A macro for representing the instruction "constant" opcode, that is,
 406    the FIXED part of the instruction. The "constant" opcode is represented
 407    as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
 408    over that range.  */
 409 #define BIN(OPC,SHIFT)  (OPC << SHIFT)
 410
 411 /* Is the current instruction type is TYPE ?  */
 412 #define IS_INSN_TYPE(TYPE)            \
 413   (CRX_INS_TYPE(instruction->flags) == TYPE)
 414
 415 /* Is the current instruction mnemonic is MNEMONIC ?  */
 416 #define IS_INSN_MNEMONIC(MNEMONIC)    \
 417   (strcmp(instruction->mnemonic,MNEMONIC) == 0)
 418
 419 /* Does the current instruction has register list ?  */
 420 #define INST_HAS_REG_LIST             \
 421   (instruction->flags & REG_LIST)
 422
 423 /* Long long type handling.  */
 424 /* Replace all appearances of 'long long int' with LONGLONG.  */
 425 typedef long long int LONGLONG;
 426 typedef unsigned long long ULONGLONG;
 427
 428 #endif /* _CRX_H_ */