1 /* d10v.h -- Header file for D10V opcode table
2 Copyright 1996 Free Software Foundation, Inc.
3 Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 1, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* Format Specifier */
26 #define FM01 0x40000000
27 #define FM10 0x80000000
28 #define FM11 0xC0000000
31 #define OPCODE_DIVS 0x14002800
33 /* The opcode table is an array of struct d10v_opcode. */
37 /* The opcode name. */
40 /* the opcode format */
43 /* These numbers were picked so we can do if( i & SHORT_OPCODE) */
44 #define SHORT_OPCODE 1
46 #define SHORT_2 1 /* short with 2 operands */
47 #define SHORT_B 3 /* short with 8-bit branch */
48 #define LONG_B 8 /* long with 16-bit branch */
49 #define LONG_L 10 /* long with 3 operands */
50 #define LONG_R 12 /* reserved */
52 /* just a placeholder for variable-length instructions */
53 /* for example, "bra" will be a fake for "bra.s" and bra.l" */
54 /* which will immediately follow in the opcode table. */
55 #define OPCODE_FAKE 32
57 /* the number of cycles */
60 /* the execution unit(s) used */
67 /* execution type; parallel or sequential */
69 #define PARONLY 1 /* parallel only */
70 #define SEQ 2 /* must be sequential */
71 #define PAR 3 /* may be parallel */
72 #define BRANCH_LINK 4 /* subroutine call. sequential and aligned */
77 /* mask. if( (i & mask) == opcode ) then match */
80 /* An array of operand codes. Each code is an index into the
81 operand table. They appear in the order which the operands must
82 appear in assembly code, and are terminated by a zero. */
83 unsigned char operands
[6];
86 /* The table itself is sorted by major opcode number, and is otherwise
87 in the order in which the disassembler should consider
89 extern const struct d10v_opcode d10v_opcodes
[];
90 extern const int d10v_num_opcodes
;
92 /* The operands table is an array of struct d10v_operand. */
95 /* The number of bits in the operand. */
98 /* How far the operand is left shifted in the instruction. */
101 /* One bit syntax flags. */
105 /* Elements in the table are retrieved by indexing with values from
106 the operands field of the d10v_opcodes table. */
108 extern const struct d10v_operand d10v_operands
[];
110 /* Values defined for the flags field of a struct d10v_operand. */
112 /* the operand must be an even number */
113 #define OPERAND_EVEN (1)
115 /* the operand must be an odd number */
116 #define OPERAND_ODD (2)
118 /* this is the destination register; it will be modified */
119 /* this is used by the optimizer */
120 #define OPERAND_DEST (4)
122 /* number or symbol */
123 #define OPERAND_NUM (8)
125 /* address or label */
126 #define OPERAND_ADDR (0x10)
129 #define OPERAND_REG (0x20)
131 /* postincrement + */
132 #define OPERAND_PLUS (0x40)
134 /* postdecrement - */
135 #define OPERAND_MINUS (0x80)
138 #define OPERAND_ATSIGN (0x100)
141 #define OPERAND_ATPAR (0x200)
144 #define OPERAND_ACC (0x400)
147 #define OPERAND_FLAG (0x800)
149 /* control register */
150 #define OPERAND_CONTROL (0x1000)
152 /* predecrement mode '@-sp' */
153 #define OPERAND_ATMINUS (0x2000)
156 #define OPERAND_SIGNED (0x4000)
158 /* Structure to hold information about predefined registers. */
161 char *name
; /* name to recognize */
162 char *pname
; /* name to print for this register */
166 extern const struct pd_reg pre_defined_registers
[];
169 /* an expressionS only has one register type, so we fake it */
170 /* by setting high bits to indicate type */
171 #define REGISTER_MASK 0xFF