1 /* Table of opcodes for the DLX microprocess.
2 Copyright 2002, 2010 Free Software Foundation, Inc.
4 This file is part of GDB and GAS.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 Initially created by Kuang Hwa Lin, 2002. */
23 /* Following are the function codes for the Special OP (ALU). */
24 #define ALUOP 0x00000000
25 #define SPECIALOP 0x00000000
27 #define NOPF 0x00000000
28 #define SLLF 0x00000004
29 #define SRLF 0x00000006
30 #define SRAF 0x00000007
32 #define SEQUF 0x00000010
33 #define SNEUF 0x00000011
34 #define SLTUF 0x00000012
35 #define SGTUF 0x00000013
36 #define SLEUF 0x00000014
37 #define SGEUF 0x00000015
39 #define ADDF 0x00000020
40 #define ADDUF 0x00000021
41 #define SUBF 0x00000022
42 #define SUBUF 0x00000023
43 #define ANDF 0x00000024
44 #define ORF 0x00000025
45 #define XORF 0x00000026
47 #define SEQF 0x00000028
48 #define SNEF 0x00000029
49 #define SLTF 0x0000002A
50 #define SGTF 0x0000002B
51 #define SLEF 0x0000002C
52 #define SGEF 0x0000002D
53 /* Following special functions was not mentioned in the
54 Hennessy's book but was implemented in the RTL. */
55 #define MVTSF 0x00000030
56 #define MVFSF 0x00000031
57 #define BSWAPF 0x00000032
58 #define LUTF 0x00000033
59 /* Following special functions was mentioned in the
60 Hennessy's book but was not implemented in the RTL. */
61 #define MULTF 0x00000005
62 #define MULTUF 0x00000006
63 #define DIVF 0x00000007
64 #define DIVUF 0x00000008
67 /* Following are the rest of the OPcodes:
68 JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26)
69 ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26)
70 ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26)
71 RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26)
72 BREAKOP= (0x014 << 26)
73 SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26)
74 SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26)
75 LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26)
76 LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26)
77 LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26),
78 SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26)
79 SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26)
80 SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */
81 #define JOP 0x08000000
82 #define JALOP 0x0c000000
83 #define BEQOP 0x10000000
84 #define BNEOP 0x14000000
86 #define ADDIOP 0x20000000
87 #define ADDUIOP 0x24000000
88 #define SUBIOP 0x28000000
89 #define SUBUIOP 0x2c000000
90 #define ANDIOP 0x30000000
91 #define ORIOP 0x34000000
92 #define XORIOP 0x38000000
93 #define LHIOP 0x3c000000
94 #define RFEOP 0x40000000
95 #define TRAPOP 0x44000000
96 #define JROP 0x48000000
97 #define JALROP 0x4c000000
98 #define BREAKOP 0x50000000
100 #define SEQIOP 0x60000000
101 #define SNEIOP 0x64000000
102 #define SLTIOP 0x68000000
103 #define SGTIOP 0x6c000000
104 #define SLEIOP 0x70000000
105 #define SGEIOP 0x74000000
107 #define LBOP 0x80000000
108 #define LHOP 0x84000000
109 #define LWOP 0x8c000000
110 #define LBUOP 0x90000000
111 #define LHUOP 0x94000000
114 #define SBOP 0xa0000000
115 #define SHOP 0xa4000000
116 #define SWOP 0xac000000
119 #define SEQUIOP 0xc0000000
120 #define SNEUIOP 0xc4000000
121 #define SLTUIOP 0xc8000000
122 #define SGTUIOP 0xcc000000
123 #define SLEUIOP 0xd0000000
124 #define SGEUIOP 0xd4000000
126 #define SLLIOP 0xd8000000
127 #define SRLIOP 0xdc000000
128 #define SRAIOP 0xe0000000
130 /* Following 3 ops was added to provide the MP atonmic operation. */
131 #define LSBUOP 0x98000000
132 #define LSHUOP 0x9c000000
133 #define LSWOP 0xb0000000
135 /* Following opcode was defined in the Hennessy's book as
136 "normal" opcode but was implemented in the RTL as special
139 #define MVTSOP 0x50000000
140 #define MVFSOP 0x54000000
145 /* Name of the instruction. */
149 unsigned long opcode
;
151 /* A string of characters which describe the operands.
152 Valid characters are:
153 , Itself. The character appears in the assembly code.
154 a rs1 The register number is in bits 21-25 of the instruction.
155 b rs2/rd The register number is in bits 16-20 of the instruction.
156 c rd. The register number is in bits 11-15 of the instruction.
157 f FUNC bits 0-10 of the instruction.
158 i An immediate operand is in bits 0-16 of the instruction. 0 extended
159 I An immediate operand is in bits 0-16 of the instruction. sign extended
160 d An 16 bit PC relative displacement.
161 D An immediate operand is in bits 0-25 of the instruction.
162 N No opperands needed, for nops.
163 P it can be a register or a 16 bit operand. */
167 static const struct dlx_opcode dlx_opcodes
[] =
169 /* Arithmetic and Logic R-TYPE instructions. */
170 { "nop", (ALUOP
|NOPF
), "N" }, /* NOP */
171 { "add", (ALUOP
|ADDF
), "c,a,b" }, /* Add */
172 { "addu", (ALUOP
|ADDUF
), "c,a,b" }, /* Add Unsigned */
173 { "sub", (ALUOP
|SUBF
), "c,a,b" }, /* SUB */
174 { "subu", (ALUOP
|SUBUF
), "c,a,b" }, /* Sub Unsigned */
175 { "mult", (ALUOP
|MULTF
), "c,a,b" }, /* MULTIPLY */
176 { "multu", (ALUOP
|MULTUF
), "c,a,b" }, /* MULTIPLY Unsigned */
177 { "div", (ALUOP
|DIVF
), "c,a,b" }, /* DIVIDE */
178 { "divu", (ALUOP
|DIVUF
), "c,a,b" }, /* DIVIDE Unsigned */
179 { "and", (ALUOP
|ANDF
), "c,a,b" }, /* AND */
180 { "or", (ALUOP
|ORF
), "c,a,b" }, /* OR */
181 { "xor", (ALUOP
|XORF
), "c,a,b" }, /* Exclusive OR */
182 { "sll", (ALUOP
|SLLF
), "c,a,b" }, /* SHIFT LEFT LOGICAL */
183 { "sra", (ALUOP
|SRAF
), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */
184 { "srl", (ALUOP
|SRLF
), "c,a,b" }, /* SHIFT RIGHT LOGICAL */
185 { "seq", (ALUOP
|SEQF
), "c,a,b" }, /* Set if equal */
186 { "sne", (ALUOP
|SNEF
), "c,a,b" }, /* Set if not equal */
187 { "slt", (ALUOP
|SLTF
), "c,a,b" }, /* Set if less */
188 { "sgt", (ALUOP
|SGTF
), "c,a,b" }, /* Set if greater */
189 { "sle", (ALUOP
|SLEF
), "c,a,b" }, /* Set if less or equal */
190 { "sge", (ALUOP
|SGEF
), "c,a,b" }, /* Set if greater or equal */
191 { "sequ", (ALUOP
|SEQUF
), "c,a,b" }, /* Set if equal unsigned */
192 { "sneu", (ALUOP
|SNEUF
), "c,a,b" }, /* Set if not equal unsigned */
193 { "sltu", (ALUOP
|SLTUF
), "c,a,b" }, /* Set if less unsigned */
194 { "sgtu", (ALUOP
|SGTUF
), "c,a,b" }, /* Set if greater unsigned */
195 { "sleu", (ALUOP
|SLEUF
), "c,a,b" }, /* Set if less or equal unsigned*/
196 { "sgeu", (ALUOP
|SGEUF
), "c,a,b" }, /* Set if greater or equal */
197 { "mvts", (ALUOP
|MVTSF
), "c,a" }, /* Move to special register */
198 { "mvfs", (ALUOP
|MVFSF
), "c,a" }, /* Move from special register */
199 { "bswap", (ALUOP
|BSWAPF
), "c,a,b" }, /* ??? Was not documented */
200 { "lut", (ALUOP
|LUTF
), "c,a,b" }, /* ????? same as above */
202 /* Arithmetic and Logical Immediate I-TYPE instructions. */
203 { "addi", ADDIOP
, "b,a,I" }, /* Add Immediate */
204 { "addui", ADDUIOP
, "b,a,i" }, /* Add Usigned Immediate */
205 { "subi", SUBIOP
, "b,a,I" }, /* Sub Immediate */
206 { "subui", SUBUIOP
, "b,a,i" }, /* Sub Unsigned Immedated */
207 { "andi", ANDIOP
, "b,a,i" }, /* AND Immediate */
208 { "ori", ORIOP
, "b,a,i" }, /* OR Immediate */
209 { "xori", XORIOP
, "b,a,i" }, /* Exclusive OR Immediate */
210 { "slli", SLLIOP
, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */
211 { "srai", SRAIOP
, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */
212 { "srli", SRLIOP
, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/
213 { "seqi", SEQIOP
, "b,a,i" }, /* Set if equal */
214 { "snei", SNEIOP
, "b,a,i" }, /* Set if not equal */
215 { "slti", SLTIOP
, "b,a,i" }, /* Set if less */
216 { "sgti", SGTIOP
, "b,a,i" }, /* Set if greater */
217 { "slei", SLEIOP
, "b,a,i" }, /* Set if less or equal */
218 { "sgei", SGEIOP
, "b,a,i" }, /* Set if greater or equal */
219 { "sequi", SEQUIOP
, "b,a,i" }, /* Set if equal */
220 { "sneui", SNEUIOP
, "b,a,i" }, /* Set if not equal */
221 { "sltui", SLTUIOP
, "b,a,i" }, /* Set if less */
222 { "sgtui", SGTUIOP
, "b,a,i" }, /* Set if greater */
223 { "sleui", SLEUIOP
, "b,a,i" }, /* Set if less or equal */
224 { "sgeui", SGEUIOP
, "b,a,i" }, /* Set if greater or equal */
225 /* Macros for I type instructions. */
226 { "mov", ADDIOP
, "b,P" }, /* a move macro */
227 { "movu", ADDUIOP
, "b,P" }, /* a move macro, unsigned */
231 { "mvts", MVTSOP
, "b,a" }, /* Move From Integer to Special */
232 { "mvfs", MVFSOP
, "b,a" }, /* Move From Special to Integer */
235 /* Load high Immediate I-TYPE instruction. */
236 { "lhi", LHIOP
, "b,i" }, /* Load High Immediate */
237 { "lui", LHIOP
, "b,i" }, /* Load High Immediate */
238 { "sethi", LHIOP
, "b,i" }, /* Load High Immediate */
240 /* LOAD/STORE BYTE 8 bits I-TYPE. */
241 { "lb", LBOP
, "b,a,I" }, /* Load Byte */
242 { "lbu", LBUOP
, "b,a,I" }, /* Load Byte Unsigned */
243 { "ldstbu", LSBUOP
, "b,a,I" }, /* Load store Byte Unsigned */
244 { "sb", SBOP
, "b,a,I" }, /* Store Byte */
246 /* LOAD/STORE HALFWORD 16 bits. */
247 { "lh", LHOP
, "b,a,I" }, /* Load Halfword */
248 { "lhu", LHUOP
, "b,a,I" }, /* Load Halfword Unsigned */
249 { "ldsthu", LSHUOP
, "b,a,I" }, /* Load Store Halfword Unsigned */
250 { "sh", SHOP
, "b,a,I" }, /* Store Halfword */
252 /* LOAD/STORE WORD 32 bits. */
253 { "lw", LWOP
, "b,a,I" }, /* Load Word */
254 { "sw", SWOP
, "b,a,I" }, /* Store Word */
255 { "ldstw", LSWOP
, "b,a,I" }, /* Load Store Word */
257 /* Branch PC-relative, 16 bits offset. */
258 { "beqz", BEQOP
, "a,d" }, /* Branch if a == 0 */
259 { "bnez", BNEOP
, "a,d" }, /* Branch if a != 0 */
260 { "beq", BEQOP
, "a,d" }, /* Branch if a == 0 */
261 { "bne", BNEOP
, "a,d" }, /* Branch if a != 0 */
263 /* Jumps Trap and RFE J-TYPE. */
264 { "j", JOP
, "D" }, /* Jump, PC-relative 26 bits */
265 { "jal", JALOP
, "D" }, /* JAL, PC-relative 26 bits */
266 { "break", BREAKOP
, "D" }, /* break to OS */
267 { "trap" , TRAPOP
, "D" }, /* TRAP to OS */
268 { "rfe", RFEOP
, "N" }, /* Return From Exception */
270 { "call", JOP
, "D" }, /* Jump, PC-relative 26 bits */
272 /* Jumps Trap and RFE I-TYPE. */
273 { "jr", JROP
, "a" }, /* Jump Register, Abs (32 bits) */
274 { "jalr", JALROP
, "a" }, /* JALR, Abs (32 bits) */
276 { "retr", JROP
, "a" }, /* Jump Register, Abs (32 bits) */
278 { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES.
279 This lets code examine entry i + 1 without
280 checking if we've run off the end of the table. */
283 const unsigned int num_dlx_opcodes
= (((sizeof dlx_opcodes
) / (sizeof dlx_opcodes
[0])) - 1);
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