1 /* Opcode table for the H8/300
2 Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002
3 Free Software Foundation, Inc.
4 Written by Steve Chamberlain <sac@cygnus.com>.
6 This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
23 /* Instructions are stored as a sequence of nibbles.
24 If the nibble has value 15 or less than the representation is complete.
25 Otherwise, we record what it contains with several flags. */
51 #define MEMRELAX 0x20 /* move insn which may relax */
58 #define SRC_IN_DST 0x400
67 #define DISPREG 0x100000
68 #define IGNORE 0x200000
69 #define E 0x400000 /* FIXME: end of nibble sequence? */
71 #define B30 0x1000000 /* bit 3 must be low */
72 #define B31 0x2000000 /* bit 3 must be high */
75 #define ABSJMP 0x10000000
76 #define ABS8MEM 0x20000000
77 #define PCREL 0x40000000
78 #define MEMIND 0x80000000
83 #define SIZE (L_2|L_3|L_8|L_16|L_32|L_P|L_24)
84 #define MODE (REG|IMM|DISP|IND|INC|DEC|CCR|ABS|MEMIND|EXR)
86 #define RD8 (DST|L_8|REG)
87 #define RD16 (DST|L_16|REG)
88 #define RD32 (DST|L_32|REG)
89 #define RS8 (SRC|L_8|REG)
90 #define RS16 (SRC|L_16|REG)
91 #define RS32 (SRC|L_32|REG)
93 #define RSP (SRC|L_P|REG)
94 #define RDP (DST|L_P|REG)
96 #define IMM8 (IMM|SRC|L_8)
97 #define IMM16 (IMM|SRC|L_16)
98 #define IMM32 (IMM|SRC|L_32)
100 #define ABS8SRC (SRC|ABS|L_8|ABS8MEM)
101 #define ABS8DST (DST|ABS|L_8|ABS8MEM)
103 #define DISP8 (PCREL|L_8)
104 #define DISP16 (PCREL|L_16)
106 #define DISP8SRC (DISP|L_8|SRC)
107 #define DISP16SRC (DISP|L_16|SRC)
109 #define DISP8DST (DISP|L_8|DST)
110 #define DISP16DST (DISP|L_16|DST)
112 #define ABS16SRC (SRC|ABS|L_16)
113 #define ABS16DST (DST|ABS|L_16)
114 #define ABS24SRC (SRC|ABS|L_24)
115 #define ABS24DST (DST|ABS|L_24)
116 #define ABS32SRC (SRC|ABS|L_32)
117 #define ABS32DST (DST|ABS|L_32)
119 #define RDDEC (DST|DEC)
120 #define RSINC (SRC|INC)
121 #define RDINC (DST|INC)
123 #define RDIND (DST|IND)
124 #define RSIND (SRC|IND)
127 #define OR8 RS8 /* ??? OR as in One Register? */
162 #define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
163 { code, 1, 2, name, {{imm,RD8,E}}, {{op00, op01, imm, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
164 { code, 1, 6, name, {{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}, 0, 0, 0, 0},\
165 { code, 1, 6, name, {{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}\
166 ,{ code, 0, 6, name, {{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0},\
167 { code, 0, 6, name, {{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}
170 #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
171 BITOP(code,imm, name, op00+1, op01, op10,op11, op20,op21,op30),\
172 BITOP(code,RS8, name, op00, op01, op10,op11, op20,op21,op30)
174 #define WTWOP(code,name, op1, op2) \
175 { code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
177 #define BRANCH(code, name, op) \
178 { code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
179 { code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}, 0, 0, 0, 0}
181 #define SOP(code, x,name) \
184 #define NEW_SOP(code, in,x,name) \
186 #define EOP ,0,0,0,0 }
188 #define TWOOP(code, name, op1, op2,op3) \
189 { code,1, 2,name, {{IMM8, RD8, E}}, {{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
190 { code, 1, 2,name, {{RS8, RD8, E}}, {{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
192 #define UNOP(code,name, op1, op2) \
193 { code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
195 #define UNOP3(code, name, op1, op2, op3) \
196 { O(code,SB), 1, 2, name, {{OR8, E, 0}}, {{op1, op2, op3+0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
197 { O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
198 { O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}, 0, 0, 0, 0} \
199 ,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST, E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
200 { O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
201 { O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}, 0, 0, 0, 0}
204 #define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
205 #define IMM24LIST IMM24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
206 #define IMM16LIST IMM16,IGNORE,IGNORE,IGNORE
207 #define A16LIST L_16,IGNORE,IGNORE,IGNORE
208 #define DISP24LIST DISP|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
209 #define DISP32LIST DISP|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
210 #define ABS24LIST ABS|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
211 #define ABS32LIST ABS|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
212 #define A24LIST L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
213 #define A32LIST L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
214 #define PREFIX32 0x0,0x1,0x0,0x0
215 #define PREFIXLDC 0x0,0x1,0x4,0x0
218 #define O(op, size) (op*4+size)
220 #define O_RECOMPILE 0
261 #define O_MOV_TO_MEM 41
299 #define O_MOV_TO_REG 79
314 /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
315 Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */
317 struct h8_opcode h8_opcodes
[] =
319 TWOOP(O(O_ADD
,SB
),"add.b", 0x8, 0x0,0x8),
321 NEW_SOP(O(O_ADD
,SW
),1,2,"add.w"),{{RS16
,RD16
,E
}},{{0x0,0x9,RS16
,RD16
,E
}} EOP
,
322 NEW_SOP(O(O_ADD
,SW
),0,4,"add.w"),{{IMM16
,RD16
,E
}},{{0x7,0x9,0x1,RD16
,IMM16
,IGNORE
,IGNORE
,IGNORE
,E
}} EOP
,
323 NEW_SOP(O(O_ADD
,SL
),0,2,"add.l"),{{RS32
,RD32
,E
}}, {{0x0,0xA,B31
|RS32
,B30
|RD32
,E
}} EOP
,
324 NEW_SOP(O(O_ADD
,SL
),0,6,"add.l"),{{IMM32
,RD32
,E
}},{{0x7,0xA,0x1,B30
|RD32
,IMM32LIST
,E
}} EOP
,
325 NEW_SOP(O(O_ADDS
,SL
),1,2,"adds"), {{KBIT
,RDP
,E
}}, {{0x0,0xB,KBIT
,RDP
,E
,0,0,0,0}} EOP
,
327 TWOOP(O(O_ADDX
,SB
),"addx",0x9,0x0,0xE),
328 TWOOP(O(O_AND
,SB
), "and.b",0xE,0x1,0x6),
330 NEW_SOP(O(O_AND
,SW
),0,2,"and.w"),{{RS16
,RD16
,E
}},{{0x6,0x6,RS16
,RD16
,E
}} EOP
,
331 NEW_SOP(O(O_AND
,SW
),0,4,"and.w"),{{IMM16
,RD16
,E
}},{{0x7,0x9,0x6,RD16
,IMM16
,IGNORE
,IGNORE
,IGNORE
,E
}} EOP
,
333 NEW_SOP(O(O_AND
,SL
),0,6,"and.l"),{{IMM32
,RD32
,E
}},{{0x7,0xA,0x6,B30
|RD32
,IMM32LIST
,E
}} EOP
,
334 NEW_SOP(O(O_AND
,SL
),0,2,"and.l") ,{{RS32
,RD32
,E
}},{{0x0,0x1,0xF,0x0,0x6,0x6,B30
|RS32
,B30
|RD32
,E
}} EOP
,
336 NEW_SOP(O(O_ANDC
,SB
),1,2,"andc"), {{IMM8
,CCR
|DST
,E
}},{{ 0x0,0x6,IMM8
,IGNORE
,E
,0,0,0,0}} EOP
,
337 NEW_SOP(O(O_ANDC
,SB
),1,2,"andc"), {{IMM8
,EXR
|DST
,E
}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8
,IGNORE
,E
,0,0,0,0}} EOP
,
339 BITOP(O(O_BAND
,SB
), IMM3
|B30
,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
340 BRANCH(O(O_BRA
,SB
),"bra",0x0),
341 BRANCH(O(O_BRA
,SB
),"bt",0x0),
342 BRANCH(O(O_BRN
,SB
),"brn",0x1),
343 BRANCH(O(O_BRN
,SB
),"bf",0x1),
344 BRANCH(O(O_BHI
,SB
),"bhi",0x2),
345 BRANCH(O(O_BLS
,SB
),"bls",0x3),
346 BRANCH(O(O_BCC
,SB
),"bcc",0x4),
347 BRANCH(O(O_BCC
,SB
),"bhs",0x4),
348 BRANCH(O(O_BCS
,SB
),"bcs",0x5),
349 BRANCH(O(O_BCS
,SB
),"blo",0x5),
350 BRANCH(O(O_BNE
,SB
),"bne",0x6),
351 BRANCH(O(O_BEQ
,SB
),"beq",0x7),
352 BRANCH(O(O_BVC
,SB
),"bvc",0x8),
353 BRANCH(O(O_BVS
,SB
),"bvs",0x9),
354 BRANCH(O(O_BPL
,SB
),"bpl",0xA),
355 BRANCH(O(O_BMI
,SB
),"bmi",0xB),
356 BRANCH(O(O_BGE
,SB
),"bge",0xC),
357 BRANCH(O(O_BLT
,SB
),"blt",0xD),
358 BRANCH(O(O_BGT
,SB
),"bgt",0xE),
359 BRANCH(O(O_BLE
,SB
),"ble",0xF),
361 EBITOP(O(O_BCLR
,SB
),IMM3
|B30
,"bclr", 0x6,0x2,0x7,0xD,0x7,0xF,0x8),
362 BITOP(O(O_BIAND
,SB
),IMM3
|B31
,"biand",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
363 BITOP(O(O_BILD
,SB
), IMM3
|B31
,"bild", 0x7,0x7,0x7,0xC,0x7,0xE,0x0),
364 BITOP(O(O_BIOR
,SB
), IMM3
|B31
,"bior", 0x7,0x4,0x7,0xC,0x7,0xE,0x0),
365 BITOP(O(O_BIST
,SB
), IMM3
|B31
,"bist", 0x6,0x7,0x7,0xD,0x7,0xF,0x8),
366 BITOP(O(O_BIXOR
,SB
),IMM3
|B31
,"bixor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
367 BITOP(O(O_BLD
,SB
), IMM3
|B30
,"bld", 0x7,0x7,0x7,0xC,0x7,0xE,0x0),
368 EBITOP(O(O_BNOT
,SB
),IMM3
|B30
,"bnot", 0x6,0x1,0x7,0xD,0x7,0xF,0x8),
369 BITOP(O(O_BOR
,SB
), IMM3
|B30
,"bor", 0x7,0x4,0x7,0xC,0x7,0xE,0x0),
370 EBITOP(O(O_BSET
,SB
),IMM3
|B30
,"bset", 0x6,0x0,0x7,0xD,0x7,0xF,0x8),
372 SOP(O(O_BSR
,SB
),6,"bsr"),{{DISP8
,E
,0}},{{ 0x5,0x5,DISP8
,IGNORE
,E
,0,0,0,0}} EOP
,
373 SOP(O(O_BSR
,SB
),6,"bsr"),{{DISP16
,E
,0}},{{ 0x5,0xC,0x0,0x0,DISP16
,IGNORE
,IGNORE
,IGNORE
,E
,0,0,0,0}} EOP
,
374 BITOP(O(O_BST
,SB
), IMM3
|B30
,"bst",0x6,0x7,0x7,0xD,0x7,0xF,0x8),
375 EBITOP(O(O_BTST
,SB
), IMM3
|B30
,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0),
376 BITOP(O(O_BXOR
,SB
), IMM3
|B30
,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
378 TWOOP(O(O_CMP
,SB
), "cmp.b",0xA,0x1,0xC),
379 WTWOP(O(O_CMP
,SW
), "cmp.w",0x1,0xD),
381 NEW_SOP(O(O_CMP
,SW
),1,2,"cmp.w"),{{RS16
,RD16
,E
}},{{0x1,0xD,RS16
,RD16
,E
}} EOP
,
382 NEW_SOP(O(O_CMP
,SW
),0,4,"cmp.w"),{{IMM16
,RD16
,E
}},{{0x7,0x9,0x2,RD16
,IMM16
,IGNORE
,IGNORE
,IGNORE
,E
}} EOP
,
384 NEW_SOP(O(O_CMP
,SL
),0,6,"cmp.l"),{{IMM32
,RD32
,E
}},{{0x7,0xA,0x2,B30
|RD32
,IMM32LIST
,E
}} EOP
,
385 NEW_SOP(O(O_CMP
,SL
),0,2,"cmp.l") ,{{RS32
,RD32
,E
}},{{0x1,0xF,B31
|RS32
,B30
|RD32
,E
}} EOP
,
387 UNOP(O(O_DAA
,SB
), "daa",0x0,0xF),
388 UNOP(O(O_DAS
,SB
), "das",0x1,0xF),
389 UNOP(O(O_DEC
,SB
), "dec.b",0x1,0xA),
391 NEW_SOP(O(O_DEC
, SW
),0,2,"dec.w") ,{{DBIT
,RD16
,E
}},{{0x1,0xB,0x5|DBIT
,RD16
,E
}} EOP
,
392 NEW_SOP(O(O_DEC
, SL
),0,2,"dec.l") ,{{DBIT
,RD32
,E
}},{{0x1,0xB,0x7|DBIT
,RD32
|B30
,E
}} EOP
,
394 NEW_SOP(O(O_DIVU
,SB
),1,13,"divxu.b"), {{RS8
,RD16
,E
}}, {{0x5,0x1,RS8
,RD16
,E
,0,0,0,0}}EOP
,
395 NEW_SOP(O(O_DIVU
,SW
),0,21,"divxu.w"),{{RS16
,RD32
,E
}},{{0x5,0x3,RS16
,B30
|RD32
,E
}}EOP
,
397 NEW_SOP(O(O_DIVS
,SB
),0,13,"divxs.b") ,{{RS8
,RD16
,E
}},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8
,RD16
,E
}} EOP
,
398 NEW_SOP(O(O_DIVS
,SW
),0,21,"divxs.w") ,{{RS16
,RD32
,E
}},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16
,B30
|RD32
,E
}} EOP
,
400 NEW_SOP(O(O_EEPMOV
,SB
),1,4,"eepmov.b"),{{E
,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E
}}EOP
,
401 NEW_SOP(O(O_EEPMOV
,SW
),0,4,"eepmov.w"),{{E
,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E
}} EOP
,
403 NEW_SOP(O(O_EXTS
,SW
),0,2,"exts.w"),{{OR16
,E
,0}},{{0x1,0x7,0xD,OR16
,E
}}EOP
,
404 NEW_SOP(O(O_EXTS
,SL
),0,2,"exts.l"),{{OR32
,E
,0}},{{0x1,0x7,0xF,OR32
|B30
,E
}}EOP
,
406 NEW_SOP(O(O_EXTU
,SW
),0,2,"extu.w"),{{OR16
,E
,0}},{{0x1,0x7,0x5,OR16
,E
}}EOP
,
407 NEW_SOP(O(O_EXTU
,SL
),0,2,"extu.l"),{{OR32
,E
,0}},{{0x1,0x7,0x7,OR32
|B30
,E
}}EOP
,
409 UNOP(O(O_INC
,SB
), "inc",0x0,0xA),
411 NEW_SOP(O(O_INC
,SW
),0,2,"inc.w") ,{{DBIT
,RD16
,E
}},{{0x0,0xB,0x5|DBIT
,RD16
,E
}} EOP
,
412 NEW_SOP(O(O_INC
,SL
),0,2,"inc.l") ,{{DBIT
,RD32
,E
}},{{0x0,0xB,0x7|DBIT
,RD32
|B30
,E
}} EOP
,
414 SOP(O(O_JMP
,SB
),4,"jmp"),{{RSIND
,E
,0}},{{0x5,0x9,B30
|RSIND
,0x0,E
,0,0,0,0}}EOP
,
415 SOP(O(O_JMP
,SB
),6,"jmp"),{{SRC
|ABSJMP
,E
,0}},{{0x5,0xA,SRC
|ABSJMP
,IGNORE
,IGNORE
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
416 SOP(O(O_JMP
,SB
),8,"jmp"),{{SRC
|MEMIND
,E
,0}},{{0x5,0xB,SRC
|MEMIND
,IGNORE
,E
,0,0,0,0}}EOP
,
418 SOP(O(O_JSR
,SB
),6,"jsr"),{{SRC
|RSIND
,E
,0}}, {{0x5,0xD,B30
|RSIND
,0x0,E
,0,0,0,0}}EOP
,
419 SOP(O(O_JSR
,SB
),8,"jsr"),{{SRC
|ABSJMP
,E
,0}},{{0x5,0xE,SRC
|ABSJMP
,IGNORE
,IGNORE
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
420 SOP(O(O_JSR
,SB
),8,"jsr"),{{SRC
|MEMIND
,E
,0}},{{0x5,0xF,SRC
|MEMIND
,IGNORE
,E
,0,0,0,0}}EOP
,
422 NEW_SOP(O(O_LDC
,SB
),1,2,"ldc"),{{IMM8
,CCR
|DST
,E
}}, {{ 0x0,0x7,IMM8
,IGNORE
,E
,0,0,0,0}}EOP
,
423 NEW_SOP(O(O_LDC
,SB
),1,2,"ldc"),{{OR8
,CCR
|DST
,E
}}, {{ 0x0,0x3,0x0,OR8
,E
,0,0,0,0}}EOP
,
424 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{ABS16SRC
,CCR
|DST
,E
}}, {{PREFIXLDC
,0x6,0xB,0x0,0x0,ABS16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
425 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{ABS32SRC
,CCR
|DST
,E
}}, {{PREFIXLDC
,0x6,0xB,0x2,0x0,SRC
|ABS32LIST
,E
}}EOP
,
426 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{DISP
|SRC
|L_16
,CCR
|DST
,E
}},{{PREFIXLDC
,0x6,0xF,B30
|DISPREG
,0,DISP
|L_16
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
427 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{DISP
|SRC
|L_32
,CCR
|DST
,E
}},{{PREFIXLDC
,0x7,0x8,B30
|DISPREG
,0,0x6,0xB,0x2,0x0,SRC
|DISP32LIST
,E
}}EOP
,
428 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{RSINC
,CCR
|DST
,E
}}, {{PREFIXLDC
,0x6,0xD,B30
|RSINC
,0x0,E
}}EOP
,
429 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{RSIND
,CCR
|DST
,E
}}, {{PREFIXLDC
,0x6,0x9,B30
|RDIND
,0x0,E
}} EOP
,
431 NEW_SOP(O(O_LDC
,SB
),1,2,"ldc"),{{IMM8
,EXR
|DST
,E
}}, {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8
,IGNORE
,E
,0,0,0,0}}EOP
,
432 NEW_SOP(O(O_LDC
,SB
),1,2,"ldc"),{{OR8
,EXR
|DST
,E
}}, {{ 0x0,0x3,0x1,OR8
,E
,0,0,0,0}}EOP
,
433 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{ABS16SRC
,EXR
|DST
,E
}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
434 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{ABS32SRC
,EXR
|DST
,E
}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC
|ABS32LIST
,E
}}EOP
,
435 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{DISP
|SRC
|L_16
,EXR
|DST
,E
}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30
|DISPREG
,0,DISP
|L_16
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
436 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{DISP
|SRC
|L_32
,EXR
|DST
,E
}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30
|DISPREG
,0,0x6,0xB,0x2,0x0,SRC
|DISP32LIST
,E
}}EOP
,
437 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{RSINC
,EXR
|DST
,E
}}, {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30
|RSINC
,0x0,E
}}EOP
,
438 NEW_SOP(O(O_LDC
,SB
),0,2,"ldc"),{{RSIND
,EXR
|DST
,E
}}, {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30
|RDIND
,0x0,E
}} EOP
,
440 SOP(O(O_MOV_TO_REG
,SB
),4,"mov.b"),{{ABS
|SRC
|L_16
|MEMRELAX
,RD8
,E
}}, {{ 0x6,0xA,0x0,RD8
,SRC
|ABS
|MEMRELAX
|A16LIST
,E
}}EOP
,
441 SOP(O(O_MOV_TO_REG
,SB
),6,"mov.b"),{{ABS
|SRC
|L_32
|MEMRELAX
,RD8
,E
}}, {{ 0x6,0xA,0x2,RD8
,SRC
|ABS
|MEMRELAX
|A32LIST
,E
}}EOP
,
442 SOP(O(O_MOV_TO_MEM
,SB
),4,"mov.b"),{{RS8
,ABS
|L_16
|MEMRELAX
|DST
,E
}}, {{ 0x6,0xA,0x8,RS8
,DST
|ABS
|MEMRELAX
|A16LIST
,E
}}EOP
,
443 SOP(O(O_MOV_TO_MEM
,SB
),6,"mov.b"),{{RS8
,ABS
|DST
|L_32
|MEMRELAX
,E
}}, {{ 0x6,0xA,0xA,RS8
,DST
|ABS
|MEMRELAX
|A32LIST
,E
}}EOP
,
445 SOP(O(O_MOV_TO_REG
,SB
),6,"mov.b"),{{DISP
|L_32
|SRC
,RD8
,E
}}, {{ 0x7,0x8,B30
|DISPREG
,0x0,0x6,0xA,0x2,RD8
,SRC
|DISP32LIST
,E
}}EOP
,
446 SOP(O(O_MOV_TO_MEM
,SB
),6,"mov.b"),{{RS8
,DISP
|L_32
|DST
,E
}}, {{ 0x7,0x8,B30
|DISPREG
,0x0,0x6,0xA,0xA,RS8
,DST
|DISP32LIST
,E
}}EOP
,
450 SOP(O(O_MOV_TO_REG
,SB
),2,"mov.b"),{{RS8
,RD8
,E
}}, {{ 0x0,0xC,RS8
,RD8
,E
,0,0,0,0}}EOP
,
451 SOP(O(O_MOV_TO_REG
,SB
),2,"mov.b"),{{IMM8
,RD8
,E
}}, {{ 0xF,RD8
,IMM8
,IGNORE
,E
,0,0,0,0}}EOP
,
452 SOP(O(O_MOV_TO_REG
,SB
),4,"mov.b"),{{RSIND
,RD8
,E
}}, {{ 0x6,0x8,B30
|RSIND
,RD8
,E
,0,0,0,0}}EOP
,
453 SOP(O(O_MOV_TO_REG
,SB
),6,"mov.b"),{{DISP16SRC
,RD8
,E
}}, {{ 0x6,0xE,B30
|DISPREG
,RD8
,DISP16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
454 SOP(O(O_MOV_TO_REG
,SB
),6,"mov.b"),{{RSINC
,RD8
,E
}}, {{ 0x6,0xC,B30
|RSINC
,RD8
,E
,0,0,0,0}}EOP
,
456 SOP(O(O_MOV_TO_REG
,SB
),4,"mov.b"),{{ABS8SRC
,RD8
,E
}}, {{ 0x2,RD8
,ABS8SRC
,IGNORE
,E
,0,0,0,0}}EOP
,
457 SOP(O(O_MOV_TO_MEM
,SB
),4,"mov.b"),{{RS8
,RDIND
,E
}}, {{ 0x6,0x8,RDIND
|B31
,RS8
,E
,0,0,0,0}}EOP
,
458 SOP(O(O_MOV_TO_MEM
,SB
),6,"mov.b"),{{RS8
,DISP16DST
,E
}}, {{ 0x6,0xE,DISPREG
|B31
,RS8
,DISP16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
459 SOP(O(O_MOV_TO_MEM
,SB
),6,"mov.b"),{{RS8
,RDDEC
|B31
,E
}}, {{ 0x6,0xC,RDDEC
|B31
,RS8
,E
,0,0,0,0}}EOP
,
461 SOP(O(O_MOV_TO_MEM
,SB
),4,"mov.b"),{{RS8
,ABS8DST
,E
}}, {{ 0x3,RS8
,ABS8DST
,IGNORE
,E
,0,0,0,0}}EOP
,
463 SOP(O(O_MOV_TO_MEM
,SW
),6,"mov.w"),{{RS16
,RDIND
,E
}}, {{ 0x6,0x9,RDIND
|B31
,RS16
,E
,0,0,0,0}}EOP
,
464 SOP(O(O_MOV_TO_REG
,SW
),6,"mov.w"),{{DISP
|L_32
|SRC
,RD16
,E
}},{{ 0x7,0x8,B30
|DISPREG
,0x0,0x6,0xB,0x2,RD16
,SRC
|DISP32LIST
,E
}}EOP
,
465 SOP(O(O_MOV_TO_MEM
,SW
),6,"mov.w"),{{RS16
,DISP
|L_32
|DST
,E
}},{{ 0x7,0x8,B30
|DISPREG
,0x0,0x6,0xB,0xA,RS16
,DST
|DISP32LIST
,E
}}EOP
,
466 SOP(O(O_MOV_TO_REG
,SW
),6,"mov.w"),{{ABS
|L_32
|MEMRELAX
|SRC
,RD16
,E
}},{{ 0x6,0xB,0x2,RD16
,SRC
|MEMRELAX
|ABS32LIST
,E
}}EOP
,
467 SOP(O(O_MOV_TO_MEM
,SW
),6,"mov.w"),{{RS16
,ABS
|L_32
|MEMRELAX
|DST
,E
}},{{ 0x6,0xB,0xA,RS16
,DST
|MEMRELAX
|ABS32LIST
,E
}}EOP
,
468 SOP(O(O_MOV_TO_REG
,SW
),2,"mov.w"),{{RS16
,RD16
,E
}}, {{ 0x0,0xD,RS16
, RD16
,E
,0,0,0,0}}EOP
,
469 SOP(O(O_MOV_TO_REG
,SW
),4,"mov.w"),{{IMM16
,RD16
,E
}}, {{ 0x7,0x9,0x0,RD16
,IMM16
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
470 SOP(O(O_MOV_TO_REG
,SW
),4,"mov.w"),{{RSIND
,RD16
,E
}}, {{ 0x6,0x9,B30
|RSIND
,RD16
,E
,0,0,0,0}}EOP
,
471 SOP(O(O_MOV_TO_REG
,SW
),6,"mov.w"),{{DISP16SRC
,RD16
,E
}}, {{ 0x6,0xF,B30
|DISPREG
,RD16
,DISP16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
472 SOP(O(O_MOV_TO_REG
,SW
),6,"mov.w"),{{RSINC
,RD16
,E
}}, {{ 0x6,0xD,B30
|RSINC
,RD16
,E
,0,0,0,0}}EOP
,
473 SOP(O(O_MOV_TO_REG
,SW
),6,"mov.w"),{{ABS16SRC
,RD16
,E
}}, {{ 0x6,0xB,0x0,RD16
,ABS16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
475 SOP(O(O_MOV_TO_MEM
,SW
),6,"mov.w"),{{RS16
,DISP16DST
,E
}}, {{ 0x6,0xF,DISPREG
|B31
,RS16
,DISP16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
476 SOP(O(O_MOV_TO_MEM
,SW
),6,"mov.w"),{{RS16
,RDDEC
,E
}}, {{ 0x6,0xD,RDDEC
|B31
,RS16
,E
,0,0,0,0}}EOP
,
477 SOP(O(O_MOV_TO_MEM
,SW
),6,"mov.w"),{{RS16
,ABS16DST
,E
}}, {{ 0x6,0xB,0x8,RS16
,ABS16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
479 SOP(O(O_MOV_TO_REG
,SL
),4,"mov.l"),{{IMM32
,RD32
,E
}}, {{ 0x7,0xA,0x0,B30
|RD32
,IMM32LIST
,E
}}EOP
,
480 SOP(O(O_MOV_TO_REG
,SL
),2,"mov.l"),{{RS32
,RD32
,E
}}, {{ 0x0,0xF,B31
|RS32
,B30
|RD32
,E
,0,0,0,0}}EOP
,
482 SOP(O(O_MOV_TO_REG
,SL
),4,"mov.l"),{{RSIND
,RD32
,E
}}, {{ PREFIX32
,0x6,0x9,RSIND
|B30
,B30
|RD32
,E
,0,0,0,0 }}EOP
,
483 SOP(O(O_MOV_TO_REG
,SL
),6,"mov.l"),{{DISP16SRC
,RD32
,E
}}, {{ PREFIX32
,0x6,0xF,DISPREG
|B30
,B30
|RD32
,DISP16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
484 SOP(O(O_MOV_TO_REG
,SL
),6,"mov.l"),{{DISP
|L_32
|SRC
,RD32
,E
}},{{ PREFIX32
,0x7,0x8,B30
|DISPREG
,0x0,0x6,0xB,0x2,B30
|RD32
,SRC
|DISP32LIST
,E
}}EOP
,
485 SOP(O(O_MOV_TO_REG
,SL
),6,"mov.l"),{{RSINC
,RD32
,E
}}, {{ PREFIX32
,0x6,0xD,B30
|RSINC
,B30
|RD32
,E
,0,0,0,0 }}EOP
,
486 SOP(O(O_MOV_TO_REG
,SL
),6,"mov.l"),{{ABS16SRC
,RD32
,E
}}, {{ PREFIX32
,0x6,0xB,0x0,B30
|RD32
,ABS16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
487 SOP(O(O_MOV_TO_REG
,SL
),6,"mov.l"),{{ABS32SRC
|MEMRELAX
,RD32
,E
}}, {{ PREFIX32
,0x6,0xB,0x2,B30
|RD32
,SRC
|MEMRELAX
|ABS32LIST
,E
}}EOP
,
488 SOP(O(O_MOV_TO_MEM
,SL
),6,"mov.l"),{{RS32
,RDIND
,E
}}, {{ PREFIX32
,0x6,0x9,RDIND
|B31
,B30
|RS32
,E
,0,0,0,0 }}EOP
,
489 SOP(O(O_MOV_TO_MEM
,SL
),6,"mov.l"),{{RS32
,DISP16DST
,E
}}, {{ PREFIX32
,0x6,0xF,DISPREG
|B31
,B30
|RS32
,DISP16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
490 SOP(O(O_MOV_TO_MEM
,SL
),6,"mov.l"),{{RS32
,DISP
|L_32
|DST
,E
}},{{ PREFIX32
,0x7,0x8,B31
|DISPREG
,0x0,0x6,0xB,0xA,B30
|RS32
,DST
|DISP32LIST
,E
}}EOP
,
491 SOP(O(O_MOV_TO_MEM
,SL
),6,"mov.l"),{{RS32
,RDDEC
,E
}}, {{ PREFIX32
,0x6,0xD,RDDEC
|B31
,B30
|RS32
,E
,0,0,0,0 }}EOP
,
492 SOP(O(O_MOV_TO_MEM
,SL
),6,"mov.l"),{{RS32
,ABS16DST
,E
}}, {{ PREFIX32
,0x6,0xB,0x8,B30
|RS32
,ABS16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
493 SOP(O(O_MOV_TO_MEM
,SL
),6,"mov.l"),{{RS32
,ABS32DST
|MEMRELAX
,E
}}, {{ PREFIX32
,0x6,0xB,0xA,B30
|RS32
,DST
|MEMRELAX
|ABS32LIST
,E
}}EOP
,
495 SOP(O(O_MOV_TO_REG
,SB
),10,"movfpe"),{{ABS16SRC
,RD8
,E
}},{{ 0x6,0xA,0x4,RD8
,ABS16SRC
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
496 SOP(O(O_MOV_TO_MEM
,SB
),10,"movtpe"),{{RS8
,ABS16DST
,E
}},{{ 0x6,0xA,0xC,RS8
,ABS16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
498 NEW_SOP(O(O_MULU
,SB
),1,14,"mulxu.b"),{{RS8
,RD16
,E
}}, {{ 0x5,0x0,RS8
,RD16
,E
,0,0,0,0}}EOP
,
499 NEW_SOP(O(O_MULU
,SW
),0,14,"mulxu.w"),{{RS16
,RD32
,E
}},{{ 0x5,0x2,RS16
,B30
|RD32
,E
,0,0,0,0}}EOP
,
501 NEW_SOP(O(O_MULS
,SB
),0,20,"mulxs.b"),{{RS8
,RD16
,E
}}, {{ 0x0,0x1,0xc,0x0,0x5,0x0,RS8
,RD16
,E
}}EOP
,
502 NEW_SOP(O(O_MULS
,SW
),0,20,"mulxs.w"),{{RS16
,RD32
,E
}},{{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16
,B30
|RD32
,E
}}EOP
,
504 /* ??? This can use UNOP3. */
505 NEW_SOP(O(O_NEG
,SB
),1,2,"neg.b"),{{ OR8
,E
, 0}},{{ 0x1,0x7,0x8,OR8
,E
,0,0,0,0}}EOP
,
506 NEW_SOP(O(O_NEG
,SW
),0,2,"neg.w"),{{ OR16
,E
,0}},{{ 0x1,0x7,0x9,OR16
,E
}}EOP
,
507 NEW_SOP(O(O_NEG
,SL
),0,2,"neg.l"),{{ OR32
,E
,0}},{{ 0x1,0x7,0xB,B30
|OR32
,E
}}EOP
,
509 NEW_SOP(O(O_NOP
,SN
),1,2,"nop"),{{E
,0,0}},{{ 0x0,0x0,0x0,0x0,E
,0,0,0,0}}EOP
,
511 /* ??? This can use UNOP3. */
512 NEW_SOP(O(O_NOT
,SB
),1,2,"not.b"),{{ OR8
,E
, 0}},{{ 0x1,0x7,0x0,OR8
,E
,0,0,0,0}}EOP
,
513 NEW_SOP(O(O_NOT
,SW
),0,2,"not.w"),{{ OR16
,E
,0}},{{ 0x1,0x7,0x1,OR16
,E
}}EOP
,
514 NEW_SOP(O(O_NOT
,SL
),0,2,"not.l"),{{ OR32
,E
,0}},{{ 0x1,0x7,0x3,B30
|OR32
,E
}}EOP
,
516 TWOOP(O(O_OR
, SB
),"or.b",0xC,0x1,0x4),
517 NEW_SOP(O(O_OR
,SW
),0,4,"or.w"),{{IMM16
,RD16
,E
}},{{0x7,0x9,0x4,RD16
,IMM16
,IGNORE
,IGNORE
,IGNORE
,E
}} EOP
,
518 NEW_SOP(O(O_OR
,SW
),0,2,"or.w"),{{RS16
,RD16
,E
}},{{0x6,0x4,RS16
,RD16
,E
}} EOP
,
520 NEW_SOP(O(O_OR
,SL
),0,6,"or.l"),{{IMM32
,RD32
,E
}},{{0x7,0xA,0x4,B30
|RD32
,IMM32LIST
,E
}} EOP
,
521 NEW_SOP(O(O_OR
,SL
),0,2,"or.l"),{{RS32
,RD32
,E
}},{{0x0,0x1,0xF,0x0,0x6,0x4,B30
|RS32
,B30
|RD32
,E
}} EOP
,
523 NEW_SOP(O(O_ORC
,SB
),1,2,"orc"),{{IMM8
,CCR
|DST
,E
}},{{ 0x0,0x4,IMM8
,IGNORE
,E
,0,0,0,0}}EOP
,
524 NEW_SOP(O(O_ORC
,SB
),1,2,"orc"),{{IMM8
,EXR
|DST
,E
}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8
,IGNORE
,E
,0,0,0,0}}EOP
,
526 NEW_SOP(O(O_MOV_TO_REG
,SW
),1,6,"pop.w"),{{OR16
,E
,0}},{{ 0x6,0xD,0x7,OR16
,E
,0,0,0,0}}EOP
,
527 NEW_SOP(O(O_MOV_TO_REG
,SL
),0,6,"pop.l"),{{OR32
,E
,0}},{{ PREFIX32
,0x6,0xD,0x7,OR32
|B30
,E
,0,0,0,0}}EOP
,
528 NEW_SOP(O(O_MOV_TO_MEM
,SW
),1,6,"push.w"),{{OR16
,E
,0}},{{ 0x6,0xD,0xF,OR16
,E
,0,0,0,0}}EOP
,
529 NEW_SOP(O(O_MOV_TO_MEM
,SL
),0,6,"push.l"),{{OR32
,E
,0}},{{ PREFIX32
,0x6,0xD,0xF,OR32
|B30
,E
,0,0,0,0}}EOP
,
531 UNOP3(O_ROTL
, "rotl", 0x1,0x2,0x8),
532 UNOP3(O_ROTR
, "rotr", 0x1,0x3,0x8),
533 UNOP3(O_ROTXL
, "rotxl",0x1,0x2,0x0),
534 UNOP3(O_ROTXR
, "rotxr",0x1,0x3,0x0),
536 SOP(O(O_BPT
,SN
), 10,"bpt"),{{E
,0,0}},{{ 0x7,0xA,0xF,0xF,E
,0,0,0,0}}EOP
,
537 SOP(O(O_RTE
,SN
), 10,"rte"),{{E
,0,0}},{{ 0x5,0x6,0x7,0x0,E
,0,0,0,0}}EOP
,
538 SOP(O(O_RTS
,SN
), 8,"rts"),{{E
,0,0}},{{ 0x5,0x4,0x7,0x0,E
,0,0,0,0}}EOP
,
540 UNOP3(O_SHAL
, "shal",0x1,0x0,0x8),
541 UNOP3(O_SHAR
, "shar",0x1,0x1,0x8),
542 UNOP3(O_SHLL
, "shll",0x1,0x0,0x0),
543 UNOP3(O_SHLR
, "shlr",0x1,0x1,0x0),
545 SOP(O(O_SLEEP
,SN
),2,"sleep"),{{E
,0,0}},{{ 0x0,0x1,0x8,0x0,E
,0,0,0,0}} EOP
,
547 NEW_SOP(O(O_STC
,SB
), 1,2,"stc"),{{CCR
|SRC
,RD8
,E
}},{{ 0x0,0x2,0x0,RD8
,E
,0,0,0,0}} EOP
,
549 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{CCR
|SRC
,RSIND
,E
}}, {{PREFIXLDC
,0x6,0x9,B31
|RDIND
,0x0,E
}} EOP
,
550 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{CCR
|SRC
,DISP
|DST
|L_16
,E
}},{{PREFIXLDC
,0x6,0xF,B31
|DISPREG
,0,DST
|DISP
|L_16
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
551 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{CCR
|SRC
,DISP
|DST
|L_32
,E
}},{{PREFIXLDC
,0x7,0x8,B30
|DISPREG
,0,0x6,0xB,0xA,0x0,DST
|DISP32LIST
,E
}}EOP
,
552 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{CCR
|SRC
,RDDEC
,E
}}, {{PREFIXLDC
,0x6,0xD,B31
|RDDEC
,0x0,E
}}EOP
,
554 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{CCR
|SRC
,ABS16DST
,E
}}, {{PREFIXLDC
,0x6,0xB,0x8,0x0,ABS16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
555 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{CCR
|SRC
,ABS32DST
,E
}}, {{PREFIXLDC
,0x6,0xB,0xA,0x0,DST
|ABS32LIST
,E
}}EOP
,
557 NEW_SOP(O(O_STC
,SB
), 1,2,"stc"),{{EXR
|SRC
,RD8
,E
}},{{ 0x0,0x2,0x1,RD8
,E
,0,0,0,0}} EOP
,
559 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{EXR
|SRC
,RSIND
,E
}}, {{0x0,0x1,0x4,0x1,0x6,0x9,B31
|RDIND
,0x0,E
}} EOP
,
560 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{EXR
|SRC
,DISP
|DST
|L_16
,E
}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31
|DISPREG
,0,DST
|DISP
|L_16
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
561 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{EXR
|SRC
,DISP
|DST
|L_32
,E
}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30
|DISPREG
,0,0x6,0xB,0xA,0x0,DST
|DISP32LIST
,E
}}EOP
,
562 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{EXR
|SRC
,RDDEC
,E
}}, {{0x0,0x1,0x4,0x1,0x6,0xD,B31
|RDDEC
,0x0,E
}}EOP
,
564 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{EXR
|SRC
,ABS16DST
,E
}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST
,IGNORE
,IGNORE
,IGNORE
,E
}}EOP
,
565 NEW_SOP(O(O_STC
,SB
),0,2,"stc"),{{EXR
|SRC
,ABS32DST
,E
}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST
|ABS32LIST
,E
}}EOP
,
567 SOP(O(O_SUB
,SB
),2,"sub.b"),{{RS8
,RD8
,E
}},{{ 0x1,0x8,RS8
,RD8
,E
,0,0,0,0}}EOP
,
569 NEW_SOP(O(O_SUB
,SW
),1,2,"sub.w"),{{RS16
,RD16
,E
}}, {{0x1,0x9,RS16
,RD16
,E
}} EOP
,
570 NEW_SOP(O(O_SUB
,SW
),0,4,"sub.w"),{{IMM16
,RD16
,E
}}, {{0x7,0x9,0x3,RD16
,IMM16
,IGNORE
,IGNORE
,IGNORE
,E
}} EOP
,
571 NEW_SOP(O(O_SUB
,SL
),0,2,"sub.l") ,{{RS32
,RD32
,E
}}, {{0x1,0xA,B31
|RS32
,B30
|RD32
,E
}} EOP
,
572 NEW_SOP(O(O_SUB
,SL
),0,6,"sub.l"), {{IMM32
,RD32
,E
}},{{0x7,0xA,0x3,B30
|RD32
,IMM32LIST
,E
}} EOP
,
574 SOP(O(O_SUBS
,SL
),2,"subs"),{{KBIT
,RDP
,E
}},{{ 0x1,0xB,KBIT
,RDP
,E
,0,0,0,0}}EOP
,
575 TWOOP(O(O_SUBX
,SB
),"subx",0xB,0x1,0xE),
577 NEW_SOP(O(O_TRAPA
,SB
),0,2,"trapa"),{{ IMM2
,E
}}, {{0x5,0x7,IMM2
,IGNORE
,E
}}EOP
,
578 NEW_SOP(O(O_TAS
,SB
),0,2,"tas"),{{RSIND
,E
}}, {{0x0,0x1,0xe,0x0,0x7,0xb,B30
|RSIND
,0xc,E
}}EOP
,
580 TWOOP(O(O_XOR
, SB
),"xor",0xD,0x1,0x5),
582 NEW_SOP(O(O_XOR
,SW
),0,4,"xor.w"),{{IMM16
,RD16
,E
}},{{0x7,0x9,0x5,RD16
,IMM16
,IGNORE
,IGNORE
,IGNORE
,E
}} EOP
,
583 NEW_SOP(O(O_XOR
,SW
),0,2,"xor.w"),{{RS16
,RD16
,E
}},{{0x6,0x5,RS16
,RD16
,E
}} EOP
,
585 NEW_SOP(O(O_XOR
,SL
),0,6,"xor.l"),{{IMM32
,RD32
,E
}},{{0x7,0xA,0x5,B30
|RD32
,IMM32LIST
,E
}} EOP
,
586 NEW_SOP(O(O_XOR
,SL
),0,2,"xor.l") ,{{RS32
,RD32
,E
}},{{0x0,0x1,0xF,0x0,0x6,0x5,B30
|RS32
,B30
|RD32
,E
}} EOP
,
588 SOP(O(O_XORC
,SB
),2,"xorc"),{{IMM8
,CCR
|DST
,E
}},{{ 0x0,0x5,IMM8
,IGNORE
,E
,0,0,0,0}}EOP
,
589 SOP(O(O_XORC
,SB
),2,"xorc"),{{IMM8
,EXR
|DST
,E
}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8
,IGNORE
,E
,0,0,0,0}}EOP
,
591 NEW_SOP(O(O_CLRMAC
,SN
),1,2,"clrmac"),{{E
, 0, 0}},{{0x0,0x1,0xa,0x0,E
}} EOP
,
592 NEW_SOP(O(O_MAC
,SL
),1,2,"mac"),{{RSINC
,RDINC
,E
}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30
|RSINC
,B30
|RDINC
,E
}} EOP
,
593 NEW_SOP(O(O_LDMAC
,SL
),1,2,"ldmac"),{{RS32
,MACREG
,E
}},{{0x0,0x3,MACREG
,RS32
,E
}} EOP
,
594 NEW_SOP(O(O_STMAC
,SL
),1,2,"stmac"),{{MACREG
,RD32
,E
}},{{0x0,0x2,MACREG
,RD32
,E
}} EOP
,
595 NEW_SOP(O(O_LDM
,SL
),0,6,"ldm.l"),{{RSINC
, RS32
, E
}},{{ 0x0,0x1,IGNORE
,0x0,0x6,0xD,0x7,IGNORE
,E
}}EOP
,
596 NEW_SOP(O(O_STM
,SL
),0,6,"stm.l"),{{RS32
, RDDEC
, E
}},{{0x0,0x1,IGNORE
,0x0,0x6,0xD,0xF,IGNORE
,E
}}EOP
,
597 {0, 0, 0, NULL
, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, 0, 0, 0, 0}
600 extern struct h8_opcode h8_opcodes
[];
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