1 /* i386-opcode.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /* The NON_BROKEN_OPCODES cases use the operands in the reverse order
21 from that documented in the Intel manuals. The opcode values are
22 such that they actually generate different instructions. These
23 values must not be changed, as they are the values generated by the
24 UnixWare assembler, and possibly other ix86 assemblers. */
26 static const template i386_optab
[] = {
30 /* move instructions */
31 #define MOV_AX_DISP32 0xa0
32 { "mov", 2, 0xa0, _
, DW
, { Disp32
, Acc
, 0 } },
33 { "mov", 2, 0x88, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
34 { "mov", 2, 0xb0, _
, ShortFormW
, { Imm
, Reg
, 0 } },
35 { "mov", 2, 0xc6, _
, W
|Modrm
, { Imm
, Reg
|Mem
, 0 } },
36 /* The next instruction accepts WordReg so that `movl %gs,%esi' can be
37 used to move a segment register to a 32 bit register without using
38 a size prefix. This will set the upper 16 bits of the 32 bit
39 register to an implementation defined value (on the Pentium Pro,
40 the implementation defined value is zero). */
41 { "mov", 2, 0x8c, _
, D
|Modrm
, { SReg3
|SReg2
, WordReg
|WordMem
, 0 } },
42 /* move to/from control debug registers */
43 { "mov", 2, 0x0f20, _
, D
|Modrm
, { Control
, Reg32
, 0} },
44 { "mov", 2, 0x0f21, _
, D
|Modrm
, { Debug
, Reg32
, 0} },
45 { "mov", 2, 0x0f24, _
, D
|Modrm
, { Test
, Reg32
, 0} },
47 /* move with sign extend */
48 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
49 conflict with the "movs" string move instruction. Thus,
50 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
51 is not kosher; we must seperate the two instructions. */
52 {"movsbl", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
|Data32
, { Reg8
|Mem
, Reg32
, 0} },
53 {"movsbw", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
|Data16
, { Reg8
|Mem
, Reg16
, 0} },
54 {"movswl", 2, 0x0fbf, _
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
56 /* move with zero extend */
57 {"movzb", 2, 0x0fb6, _
, ReverseRegRegmem
|Modrm
, { Reg8
|Mem
, Reg16
|Reg32
, 0} },
58 {"movzwl", 2, 0x0fb7, _
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
60 /* push instructions */
61 {"push", 1, 0x50, _
, ShortForm
, { WordReg
,0,0 } },
62 {"push", 1, 0xff, 0x6, Modrm
, { WordReg
|WordMem
, 0, 0 } },
63 {"push", 1, 0x6a, _
, 0, { Imm8S
, 0, 0} },
64 {"push", 1, 0x68, _
, 0, { Imm16
|Imm32
, 0, 0} },
65 {"push", 1, 0x06, _
, Seg2ShortForm
, { SReg2
,0,0 } },
66 {"push", 1, 0x0fa0, _
, Seg3ShortForm
, { SReg3
,0,0 } },
68 {"pusha", 0, 0x60, _
, 0, { 0, 0, 0 } },
70 /* pop instructions */
71 {"pop", 1, 0x58, _
, ShortForm
, { WordReg
,0,0 } },
72 {"pop", 1, 0x8f, 0x0, Modrm
, { WordReg
|WordMem
, 0, 0 } },
73 #define POP_SEG_SHORT 0x7
74 {"pop", 1, 0x07, _
, Seg2ShortForm
, { SReg2
,0,0 } },
75 {"pop", 1, 0x0fa1, _
, Seg3ShortForm
, { SReg3
,0,0 } },
77 {"popa", 0, 0x61, _
, 0, { 0, 0, 0 } },
79 /* xchg exchange instructions
80 xchg commutes: we allow both operand orders */
81 {"xchg", 2, 0x90, _
, ShortForm
, { WordReg
, Acc
, 0 } },
82 {"xchg", 2, 0x90, _
, ShortForm
, { Acc
, WordReg
, 0 } },
83 {"xchg", 2, 0x86, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
84 {"xchg", 2, 0x86, _
, W
|Modrm
, { Reg
|Mem
, Reg
, 0 } },
86 /* in/out from ports */
87 {"in", 2, 0xe4, _
, W
, { Imm8
, Acc
, 0 } },
88 {"in", 2, 0xec, _
, W
, { InOutPortReg
, Acc
, 0 } },
89 {"in", 1, 0xe4, _
, W
, { Imm8
, 0, 0 } },
90 {"in", 1, 0xec, _
, W
, { InOutPortReg
, 0, 0 } },
91 {"out", 2, 0xe6, _
, W
, { Acc
, Imm8
, 0 } },
92 {"out", 2, 0xee, _
, W
, { Acc
, InOutPortReg
, 0 } },
93 {"out", 1, 0xe6, _
, W
, { Imm8
, 0, 0 } },
94 {"out", 1, 0xee, _
, W
, { InOutPortReg
, 0, 0 } },
96 /* load effective address */
97 {"lea", 2, 0x8d, _
, Modrm
, { WordMem
, WordReg
, 0 } },
99 /* load segment registers from memory */
100 {"lds", 2, 0xc5, _
, Modrm
, { Mem
, Reg32
, 0} },
101 {"les", 2, 0xc4, _
, Modrm
, { Mem
, Reg32
, 0} },
102 {"lfs", 2, 0x0fb4, _
, Modrm
, { Mem
, Reg32
, 0} },
103 {"lgs", 2, 0x0fb5, _
, Modrm
, { Mem
, Reg32
, 0} },
104 {"lss", 2, 0x0fb2, _
, Modrm
, { Mem
, Reg32
, 0} },
106 /* flags register instructions */
107 {"clc", 0, 0xf8, _
, 0, { 0, 0, 0} },
108 {"cld", 0, 0xfc, _
, 0, { 0, 0, 0} },
109 {"cli", 0, 0xfa, _
, 0, { 0, 0, 0} },
110 {"clts", 0, 0x0f06, _
, 0, { 0, 0, 0} },
111 {"cmc", 0, 0xf5, _
, 0, { 0, 0, 0} },
112 {"lahf", 0, 0x9f, _
, 0, { 0, 0, 0} },
113 {"sahf", 0, 0x9e, _
, 0, { 0, 0, 0} },
114 {"pushfl", 0, 0x9c, _
, Data32
, { 0, 0, 0} },
115 {"popfl", 0, 0x9d, _
, Data32
, { 0, 0, 0} },
116 {"pushfw", 0, 0x9c, _
, Data16
, { 0, 0, 0} },
117 {"popfw", 0, 0x9d, _
, Data16
, { 0, 0, 0} },
118 {"pushf", 0, 0x9c, _
, 0, { 0, 0, 0} },
119 {"popf", 0, 0x9d, _
, 0, { 0, 0, 0} },
120 {"stc", 0, 0xf9, _
, 0, { 0, 0, 0} },
121 {"std", 0, 0xfd, _
, 0, { 0, 0, 0} },
122 {"sti", 0, 0xfb, _
, 0, { 0, 0, 0} },
124 {"add", 2, 0x0, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
125 {"add", 2, 0x83, 0, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
126 {"add", 2, 0x4, _
, W
, { Imm
, Acc
, 0} },
127 {"add", 2, 0x80, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
129 {"inc", 1, 0x40, _
, ShortForm
, { WordReg
, 0, 0} },
130 {"inc", 1, 0xfe, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
132 {"sub", 2, 0x28, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
133 {"sub", 2, 0x83, 5, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
134 {"sub", 2, 0x2c, _
, W
, { Imm
, Acc
, 0} },
135 {"sub", 2, 0x80, 5, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
137 {"dec", 1, 0x48, _
, ShortForm
, { WordReg
, 0, 0} },
138 {"dec", 1, 0xfe, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
140 {"sbb", 2, 0x18, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
141 {"sbb", 2, 0x83, 3, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
142 {"sbb", 2, 0x1c, _
, W
, { Imm
, Acc
, 0} },
143 {"sbb", 2, 0x80, 3, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
145 {"cmp", 2, 0x38, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
146 {"cmp", 2, 0x83, 7, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
147 {"cmp", 2, 0x3c, _
, W
, { Imm
, Acc
, 0} },
148 {"cmp", 2, 0x80, 7, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
150 {"test", 2, 0x84, _
, W
|Modrm
, { Reg
|Mem
, Reg
, 0} },
151 {"test", 2, 0x84, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0} },
152 {"test", 2, 0xa8, _
, W
, { Imm
, Acc
, 0} },
153 {"test", 2, 0xf6, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
155 {"and", 2, 0x20, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
156 {"and", 2, 0x83, 4, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
157 {"and", 2, 0x24, _
, W
, { Imm
, Acc
, 0} },
158 {"and", 2, 0x80, 4, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
160 {"or", 2, 0x08, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
161 {"or", 2, 0x83, 1, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
162 {"or", 2, 0x0c, _
, W
, { Imm
, Acc
, 0} },
163 {"or", 2, 0x80, 1, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
165 {"xor", 2, 0x30, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
166 {"xor", 2, 0x83, 6, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
167 {"xor", 2, 0x34, _
, W
, { Imm
, Acc
, 0} },
168 {"xor", 2, 0x80, 6, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
170 /* iclr with 1 operand is really xor with 2 operands. */
171 {"clr", 1, 0x30, _
, W
|Modrm
|iclrKludge
, { Reg
} },
173 {"adc", 2, 0x10, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
174 {"adc", 2, 0x83, 2, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
175 {"adc", 2, 0x14, _
, W
, { Imm
, Acc
, 0} },
176 {"adc", 2, 0x80, 2, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
178 {"neg", 1, 0xf6, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
179 {"not", 1, 0xf6, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
181 {"aaa", 0, 0x37, _
, 0, { 0, 0, 0} },
182 {"aas", 0, 0x3f, _
, 0, { 0, 0, 0} },
183 {"daa", 0, 0x27, _
, 0, { 0, 0, 0} },
184 {"das", 0, 0x2f, _
, 0, { 0, 0, 0} },
185 {"aad", 0, 0xd50a, _
, 0, { 0, 0, 0} },
186 {"aam", 0, 0xd40a, _
, 0, { 0, 0, 0} },
188 /* conversion insns */
189 /* conversion: intel naming */
190 {"cbw", 0, 0x98, _
, Data16
, { 0, 0, 0} },
191 {"cwd", 0, 0x99, _
, Data16
, { 0, 0, 0} },
192 {"cwde", 0, 0x98, _
, Data32
, { 0, 0, 0} },
193 {"cdq", 0, 0x99, _
, Data32
, { 0, 0, 0} },
195 {"cbtw", 0, 0x98, _
, Data16
, { 0, 0, 0} },
196 {"cwtl", 0, 0x98, _
, Data32
, { 0, 0, 0} },
197 {"cwtd", 0, 0x99, _
, Data16
, { 0, 0, 0} },
198 {"cltd", 0, 0x99, _
, Data32
, { 0, 0, 0} },
200 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
201 expanding 64-bit multiplies, and *cannot* be selected to accomplish
202 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
203 These multiplies can only be selected with single operand forms. */
204 {"mul", 1, 0xf6, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
205 {"imul", 1, 0xf6, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
210 /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
211 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
212 '%eax' in the reg field and '%ecx' in the regmem field if we did not
214 {"imul", 2, 0x0faf, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
215 {"imul", 3, 0x6b, _
, Modrm
|ReverseRegRegmem
, { Imm8S
, WordReg
|Mem
, WordReg
} },
216 {"imul", 3, 0x69, _
, Modrm
|ReverseRegRegmem
, { Imm16
|Imm32
, WordReg
|Mem
, WordReg
} },
218 imul with 2 operands mimicks imul with 3 by puting register both
219 in i.rm.reg & i.rm.regmem fields
221 {"imul", 2, 0x6b, _
, Modrm
|imulKludge
, { Imm8S
, WordReg
, 0} },
222 {"imul", 2, 0x69, _
, Modrm
|imulKludge
, { Imm16
|Imm32
, WordReg
, 0} },
223 {"div", 1, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, 0, 0} },
224 {"div", 2, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
225 {"idiv", 1, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
226 {"idiv", 2, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
228 {"rol", 2, 0xd0, 0, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
229 {"rol", 2, 0xc0, 0, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
230 {"rol", 2, 0xd2, 0, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
231 {"rol", 1, 0xd0, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
233 {"ror", 2, 0xd0, 1, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
234 {"ror", 2, 0xc0, 1, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
235 {"ror", 2, 0xd2, 1, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
236 {"ror", 1, 0xd0, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
238 {"rcl", 2, 0xd0, 2, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
239 {"rcl", 2, 0xc0, 2, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
240 {"rcl", 2, 0xd2, 2, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
241 {"rcl", 1, 0xd0, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
243 {"rcr", 2, 0xd0, 3, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
244 {"rcr", 2, 0xc0, 3, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
245 {"rcr", 2, 0xd2, 3, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
246 {"rcr", 1, 0xd0, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
248 {"sal", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
249 {"sal", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
250 {"sal", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
251 {"sal", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
252 {"shl", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
253 {"shl", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
254 {"shl", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
255 {"shl", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
257 {"shld", 3, 0x0fa4, _
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
258 {"shld", 3, 0x0fa5, _
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
259 {"shld", 2, 0x0fa5, _
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
261 {"shr", 2, 0xd0, 5, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
262 {"shr", 2, 0xc0, 5, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
263 {"shr", 2, 0xd2, 5, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
264 {"shr", 1, 0xd0, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
266 {"shrd", 3, 0x0fac, _
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
267 {"shrd", 3, 0x0fad, _
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
268 {"shrd", 2, 0x0fad, _
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
270 {"sar", 2, 0xd0, 7, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
271 {"sar", 2, 0xc0, 7, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
272 {"sar", 2, 0xd2, 7, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
273 {"sar", 1, 0xd0, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
275 /* control transfer instructions */
276 #define CALL_PC_RELATIVE 0xe8
277 {"call", 1, 0xe8, _
, JumpDword
, { Disp32
, 0, 0} },
278 {"call", 1, 0xff, 2, Modrm
|Data32
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
279 {"callw", 1, 0xff, 2, Modrm
|Data16
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
280 #define CALL_FAR_IMMEDIATE 0x9a
281 {"lcall", 2, 0x9a, _
, JumpInterSegment
, { Imm16
, Imm32
, 0} },
282 {"lcall", 1, 0xff, 3, Modrm
|Data32
, { Mem
, 0, 0} },
283 {"lcallw", 1, 0xff, 3, Modrm
|Data16
, { Mem
, 0, 0} },
285 #define JUMP_PC_RELATIVE 0xeb
286 {"jmp", 1, 0xeb, _
, Jump
, { Disp
, 0, 0} },
287 {"jmp", 1, 0xff, 4, Modrm
, { Reg32
|Mem
|JumpAbsolute
, 0, 0} },
288 #define JUMP_FAR_IMMEDIATE 0xea
289 {"ljmp", 2, 0xea, _
, JumpInterSegment
, { Imm16
, Imm32
, 0} },
290 {"ljmp", 1, 0xff, 5, Modrm
|Data32
, { Mem
, 0, 0} },
292 {"ret", 0, 0xc3, _
, Data32
, { 0, 0, 0} },
293 {"ret", 1, 0xc2, _
, Data32
, { Imm16
, 0, 0} },
294 {"retw", 0, 0xc3, _
, Data16
, { 0, 0, 0} },
295 {"retw", 1, 0xc2, _
, Data16
, { Imm16
, 0, 0} },
296 {"lret", 0, 0xcb, _
, Data32
, { 0, 0, 0} },
297 {"lret", 1, 0xca, _
, Data32
, { Imm16
, 0, 0} },
298 {"lretw", 0, 0xcb, _
, Data16
, { 0, 0, 0} },
299 {"lretw", 1, 0xca, _
, Data16
, { Imm16
, 0, 0} },
300 {"enter", 2, 0xc8, _
, Data32
, { Imm16
, Imm8
, 0} },
301 {"leave", 0, 0xc9, _
, Data32
, { 0, 0, 0} },
302 {"enterw", 2, 0xc8, _
, Data16
, { Imm16
, Imm8
, 0} },
303 {"leavew", 0, 0xc9, _
, Data16
, { 0, 0, 0} },
305 /* conditional jumps */
306 {"jo", 1, 0x70, _
, Jump
, { Disp
, 0, 0} },
308 {"jno", 1, 0x71, _
, Jump
, { Disp
, 0, 0} },
310 {"jb", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
311 {"jc", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
312 {"jnae", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
314 {"jnb", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
315 {"jnc", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
316 {"jae", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
318 {"je", 1, 0x74, _
, Jump
, { Disp
, 0, 0} },
319 {"jz", 1, 0x74, _
, Jump
, { Disp
, 0, 0} },
321 {"jne", 1, 0x75, _
, Jump
, { Disp
, 0, 0} },
322 {"jnz", 1, 0x75, _
, Jump
, { Disp
, 0, 0} },
324 {"jbe", 1, 0x76, _
, Jump
, { Disp
, 0, 0} },
325 {"jna", 1, 0x76, _
, Jump
, { Disp
, 0, 0} },
327 {"jnbe", 1, 0x77, _
, Jump
, { Disp
, 0, 0} },
328 {"ja", 1, 0x77, _
, Jump
, { Disp
, 0, 0} },
330 {"js", 1, 0x78, _
, Jump
, { Disp
, 0, 0} },
332 {"jns", 1, 0x79, _
, Jump
, { Disp
, 0, 0} },
334 {"jp", 1, 0x7a, _
, Jump
, { Disp
, 0, 0} },
335 {"jpe", 1, 0x7a, _
, Jump
, { Disp
, 0, 0} },
337 {"jnp", 1, 0x7b, _
, Jump
, { Disp
, 0, 0} },
338 {"jpo", 1, 0x7b, _
, Jump
, { Disp
, 0, 0} },
340 {"jl", 1, 0x7c, _
, Jump
, { Disp
, 0, 0} },
341 {"jnge", 1, 0x7c, _
, Jump
, { Disp
, 0, 0} },
343 {"jnl", 1, 0x7d, _
, Jump
, { Disp
, 0, 0} },
344 {"jge", 1, 0x7d, _
, Jump
, { Disp
, 0, 0} },
346 {"jle", 1, 0x7e, _
, Jump
, { Disp
, 0, 0} },
347 {"jng", 1, 0x7e, _
, Jump
, { Disp
, 0, 0} },
349 {"jnle", 1, 0x7f, _
, Jump
, { Disp
, 0, 0} },
350 {"jg", 1, 0x7f, _
, Jump
, { Disp
, 0, 0} },
352 #define IS_JUMP_ON_CX_ZERO(o) \
355 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
356 {"jcxz", 1, 0xe3, _
, JumpByte
|Data16
, { Disp
, 0, 0} },
357 {"jecxz", 1, 0xe3, _
, JumpByte
|Data32
, { Disp
, 0, 0} },
359 #define IS_LOOP_ECX_TIMES(o) \
360 (o == 0xe2 || o == 0xe1 || o == 0xe0)
362 {"loop", 1, 0xe2, _
, JumpByte
, { Disp
, 0, 0} },
364 {"loopz", 1, 0xe1, _
, JumpByte
, { Disp
, 0, 0} },
365 {"loope", 1, 0xe1, _
, JumpByte
, { Disp
, 0, 0} },
367 {"loopnz", 1, 0xe0, _
, JumpByte
, { Disp
, 0, 0} },
368 {"loopne", 1, 0xe0, _
, JumpByte
, { Disp
, 0, 0} },
370 /* set byte on flag instructions */
371 {"seto", 1, 0x0f90, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
373 {"setno", 1, 0x0f91, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
375 {"setb", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
376 {"setc", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
377 {"setnae", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
379 {"setnb", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
380 {"setnc", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
381 {"setae", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
383 {"sete", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
384 {"setz", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
386 {"setne", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
387 {"setnz", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
389 {"setbe", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
390 {"setna", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
392 {"setnbe", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
393 {"seta", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
395 {"sets", 1, 0x0f98, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
397 {"setns", 1, 0x0f99, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
399 {"setp", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
400 {"setpe", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
402 {"setnp", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
403 {"setpo", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
405 {"setl", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
406 {"setnge", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
408 {"setnl", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
409 {"setge", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
411 {"setle", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
412 {"setng", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
414 {"setnle", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
415 {"setg", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
417 /* string manipulation */
418 {"cmps", 0, 0xa6, _
, W
|IsString
, { 0, 0, 0} },
419 {"scmp", 0, 0xa6, _
, W
|IsString
, { 0, 0, 0} },
420 {"ins", 0, 0x6c, _
, W
|IsString
, { 0, 0, 0} },
421 {"outs", 0, 0x6e, _
, W
|IsString
, { 0, 0, 0} },
422 {"lods", 0, 0xac, _
, W
|IsString
, { 0, 0, 0} },
423 {"slod", 0, 0xac, _
, W
|IsString
, { 0, 0, 0} },
424 {"movs", 0, 0xa4, _
, W
|IsString
, { 0, 0, 0} },
425 {"smov", 0, 0xa4, _
, W
|IsString
, { 0, 0, 0} },
426 {"scas", 0, 0xae, _
, W
|IsString
, { 0, 0, 0} },
427 {"ssca", 0, 0xae, _
, W
|IsString
, { 0, 0, 0} },
428 {"stos", 0, 0xaa, _
, W
|IsString
, { 0, 0, 0} },
429 {"ssto", 0, 0xaa, _
, W
|IsString
, { 0, 0, 0} },
430 {"xlat", 0, 0xd7, _
, IsString
, { 0, 0, 0} },
432 /* bit manipulation */
433 {"bsf", 2, 0x0fbc, _
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
434 {"bsr", 2, 0x0fbd, _
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
435 {"bt", 2, 0x0fa3, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
436 {"bt", 2, 0x0fba, 4, Modrm
, { Imm8
, Reg
|Mem
, 0} },
437 {"btc", 2, 0x0fbb, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
438 {"btc", 2, 0x0fba, 7, Modrm
, { Imm8
, Reg
|Mem
, 0} },
439 {"btr", 2, 0x0fb3, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
440 {"btr", 2, 0x0fba, 6, Modrm
, { Imm8
, Reg
|Mem
, 0} },
441 {"bts", 2, 0x0fab, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
442 {"bts", 2, 0x0fba, 5, Modrm
, { Imm8
, Reg
|Mem
, 0} },
444 /* interrupts & op. sys insns */
445 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
447 #define INT_OPCODE 0xcd
448 #define INT3_OPCODE 0xcc
449 {"int", 1, 0xcd, _
, 0, { Imm8
, 0, 0} },
450 {"int3", 0, 0xcc, _
, 0, { 0, 0, 0} },
451 {"into", 0, 0xce, _
, 0, { 0, 0, 0} },
452 {"iret", 0, 0xcf, _
, Data32
, { 0, 0, 0} },
453 {"iretw", 0, 0xcf, _
, Data16
, { 0, 0, 0} },
454 /* i386sl, i486sl, later 486, and Pentium */
455 {"rsm", 0, 0x0faa, _
, 0,{ 0, 0, 0} },
457 {"boundl", 2, 0x62, _
, Modrm
|Data32
, { Reg32
, Mem
, 0} },
458 {"boundw", 2, 0x62, _
, Modrm
|Data16
, { Reg16
, Mem
, 0} },
460 {"hlt", 0, 0xf4, _
, 0, { 0, 0, 0} },
461 {"wait", 0, 0x9b, _
, 0, { 0, 0, 0} },
462 /* nop is actually 'xchgl %eax, %eax' */
463 {"nop", 0, 0x90, _
, 0, { 0, 0, 0} },
465 /* protection control */
466 {"arpl", 2, 0x63, _
, Modrm
, { Reg16
, Reg16
|Mem
, 0} },
467 {"lar", 2, 0x0f02, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
468 {"lgdt", 1, 0x0f01, 2, Modrm
, { Mem
, 0, 0} },
469 {"lidt", 1, 0x0f01, 3, Modrm
, { Mem
, 0, 0} },
470 {"lldt", 1, 0x0f00, 2, Modrm
, { WordReg
|Mem
, 0, 0} },
471 {"lmsw", 1, 0x0f01, 6, Modrm
, { WordReg
|Mem
, 0, 0} },
472 {"lsl", 2, 0x0f03, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
473 {"ltr", 1, 0x0f00, 3, Modrm
, { WordReg
|Mem
, 0, 0} },
475 {"sgdt", 1, 0x0f01, 0, Modrm
, { Mem
, 0, 0} },
476 {"sidt", 1, 0x0f01, 1, Modrm
, { Mem
, 0, 0} },
477 {"sldt", 1, 0x0f00, 0, Modrm
, { WordReg
|Mem
, 0, 0} },
478 {"smsw", 1, 0x0f01, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
479 {"str", 1, 0x0f00, 1, Modrm
, { Reg16
|Mem
, 0, 0} },
481 {"verr", 1, 0x0f00, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
482 {"verw", 1, 0x0f00, 5, Modrm
, { WordReg
|Mem
, 0, 0} },
484 /* floating point instructions */
487 {"fld", 1, 0xd9c0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
488 {"flds", 1, 0xd9, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem float */
489 {"fldl", 1, 0xdd, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem double */
490 {"fldl", 1, 0xd9c0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
491 {"fild", 1, 0xdf, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem word (16) */
492 {"fildl", 1, 0xdb, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem dword (32) */
493 {"fildq",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
494 {"fildll",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
495 {"fldt", 1, 0xdb, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem efloat */
496 {"fbld", 1, 0xdf, 4, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem bcd */
499 {"fst", 1, 0xddd0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
500 {"fsts", 1, 0xd9, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
501 {"fstl", 1, 0xdd, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
502 {"fstl", 1, 0xddd0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
503 {"fist", 1, 0xdf, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
504 {"fistl", 1, 0xdb, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
506 /* store (with pop) */
507 {"fstp", 1, 0xddd8, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
508 {"fstps", 1, 0xd9, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
509 {"fstpl", 1, 0xdd, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
510 {"fstpl", 1, 0xddd8, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
511 {"fistp", 1, 0xdf, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
512 {"fistpl",1, 0xdb, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
513 {"fistpq",1, 0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
514 {"fistpll",1,0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
515 {"fstpt", 1, 0xdb, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem efloat */
516 {"fbstp", 1, 0xdf, 6, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem bcd */
518 /* exchange %st<n> with %st0 */
519 {"fxch", 1, 0xd9c8, _
, ShortForm
, { FloatReg
, 0, 0} },
520 {"fxch", 0, 0xd9c9, _
, 0, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
522 /* comparison (without pop) */
523 {"fcom", 1, 0xd8d0, _
, ShortForm
, { FloatReg
, 0, 0} },
524 {"fcoms", 1, 0xd8, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
525 {"ficoml", 1, 0xda, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
526 {"fcoml", 1, 0xdc, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
527 {"fcoml", 1, 0xd8d0, _
, ShortForm
, { FloatReg
, 0, 0} },
528 {"ficoms", 1, 0xde, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
530 /* comparison (with pop) */
531 {"fcomp", 1, 0xd8d8, _
, ShortForm
, { FloatReg
, 0, 0} },
532 {"fcomp", 0, 0xd8d9, _
, 0, {0, 0, 0} }, /* fcomp %st, %st(1) */
533 {"fcomps", 1, 0xd8, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
534 {"ficompl", 1, 0xda, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
535 {"fcompl", 1, 0xdc, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
536 {"fcompl", 1, 0xd8d8, _
, ShortForm
, { FloatReg
, 0, 0} },
537 {"ficomps", 1, 0xde, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
538 {"fcompp", 0, 0xded9, _
, 0, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
540 /* unordered comparison (with pop) */
541 {"fucom", 1, 0xdde0, _
, ShortForm
, { FloatReg
, 0, 0} },
542 {"fucomp", 1, 0xdde8, _
, ShortForm
, { FloatReg
, 0, 0} },
543 {"fucompp", 0, 0xdae9, _
, 0, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
545 {"ftst", 0, 0xd9e4, _
, 0, { 0, 0, 0} }, /* test %st0 */
546 {"fxam", 0, 0xd9e5, _
, 0, { 0, 0, 0} }, /* examine %st0 */
548 /* load constants into %st0 */
549 {"fld1", 0, 0xd9e8, _
, 0, { 0, 0, 0} }, /* %st0 <-- 1.0 */
550 {"fldl2t", 0, 0xd9e9, _
, 0, { 0, 0, 0} }, /* %st0 <-- log2(10) */
551 {"fldl2e", 0, 0xd9ea, _
, 0, { 0, 0, 0} }, /* %st0 <-- log2(e) */
552 {"fldpi", 0, 0xd9eb, _
, 0, { 0, 0, 0} }, /* %st0 <-- pi */
553 {"fldlg2", 0, 0xd9ec, _
, 0, { 0, 0, 0} }, /* %st0 <-- log10(2) */
554 {"fldln2", 0, 0xd9ed, _
, 0, { 0, 0, 0} }, /* %st0 <-- ln(2) */
555 {"fldz", 0, 0xd9ee, _
, 0, { 0, 0, 0} }, /* %st0 <-- 0.0 */
560 {"fadd", 1, 0xd8c0, _
, ShortForm
, { FloatReg
, 0, 0} },
561 {"fadd", 2, 0xd8c0, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
562 {"fadd", 0, 0xdcc1, _
, 0, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
563 {"faddp", 1, 0xdec0, _
, ShortForm
, { FloatReg
, 0, 0} },
564 {"faddp", 2, 0xdec0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
565 {"faddp", 2, 0xdec0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
566 {"faddp", 0, 0xdec1, _
, 0, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
567 {"fadds", 1, 0xd8, 0, Modrm
, { Mem
, 0, 0} },
568 {"fiaddl", 1, 0xda, 0, Modrm
, { Mem
, 0, 0} },
569 {"faddl", 1, 0xdc, 0, Modrm
, { Mem
, 0, 0} },
570 {"fiadds", 1, 0xde, 0, Modrm
, { Mem
, 0, 0} },
573 /* Note: intel has decided that certain of these operations are reversed
574 in assembler syntax. */
575 {"fsub", 1, 0xd8e0, _
, ShortForm
, { FloatReg
, 0, 0} },
576 {"fsub", 2, 0xd8e0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
577 #ifdef NON_BROKEN_OPCODES
578 {"fsub", 2, 0xdce8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
580 {"fsub", 2, 0xdce0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
582 {"fsub", 0, 0xdce1, _
, 0, { 0, 0, 0} },
583 {"fsubp", 1, 0xdee8, _
, ShortForm
, { FloatReg
, 0, 0} },
584 {"fsubp", 2, 0xdee8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
585 #ifdef NON_BROKEN_OPCODES
586 {"fsubp", 2, 0xdee8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
587 {"fsubp", 0, 0xdee9, _
, 0, { 0, 0, 0} },
589 {"fsubp", 2, 0xdee0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
590 {"fsubp", 0, 0xdee1, _
, 0, { 0, 0, 0} },
592 {"fsubs", 1, 0xd8, 4, Modrm
, { Mem
, 0, 0} },
593 {"fisubl", 1, 0xda, 4, Modrm
, { Mem
, 0, 0} },
594 {"fsubl", 1, 0xdc, 4, Modrm
, { Mem
, 0, 0} },
595 {"fisubs", 1, 0xde, 4, Modrm
, { Mem
, 0, 0} },
598 {"fsubr", 1, 0xd8e8, _
, ShortForm
, { FloatReg
, 0, 0} },
599 {"fsubr", 2, 0xd8e8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
600 #ifdef NON_BROKEN_OPCODES
601 {"fsubr", 2, 0xdce0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
603 {"fsubr", 2, 0xdce8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
605 {"fsubr", 0, 0xdce9, _
, 0, { 0, 0, 0} },
606 {"fsubrp", 1, 0xdee0, _
, ShortForm
, { FloatReg
, 0, 0} },
607 {"fsubrp", 2, 0xdee0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
608 #ifdef NON_BROKEN_OPCODES
609 {"fsubrp", 2, 0xdee0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
610 {"fsubrp", 0, 0xdee1, _
, 0, { 0, 0, 0} },
612 {"fsubrp", 2, 0xdee8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
613 {"fsubrp", 0, 0xdee9, _
, 0, { 0, 0, 0} },
615 {"fsubrs", 1, 0xd8, 5, Modrm
, { Mem
, 0, 0} },
616 {"fisubrl", 1, 0xda, 5, Modrm
, { Mem
, 0, 0} },
617 {"fsubrl", 1, 0xdc, 5, Modrm
, { Mem
, 0, 0} },
618 {"fisubrs", 1, 0xde, 5, Modrm
, { Mem
, 0, 0} },
621 {"fmul", 1, 0xd8c8, _
, ShortForm
, { FloatReg
, 0, 0} },
622 {"fmul", 2, 0xd8c8, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
623 {"fmul", 0, 0xdcc9, _
, 0, { 0, 0, 0} },
624 {"fmulp", 1, 0xdec8, _
, ShortForm
, { FloatReg
, 0, 0} },
625 {"fmulp", 2, 0xdec8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
626 {"fmulp", 2, 0xdec8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
627 {"fmulp", 0, 0xdec9, _
, 0, { 0, 0, 0} },
628 {"fmuls", 1, 0xd8, 1, Modrm
, { Mem
, 0, 0} },
629 {"fimull", 1, 0xda, 1, Modrm
, { Mem
, 0, 0} },
630 {"fmull", 1, 0xdc, 1, Modrm
, { Mem
, 0, 0} },
631 {"fimuls", 1, 0xde, 1, Modrm
, { Mem
, 0, 0} },
634 /* Note: intel has decided that certain of these operations are reversed
635 in assembler syntax. */
636 {"fdiv", 1, 0xd8f0, _
, ShortForm
, { FloatReg
, 0, 0} },
637 {"fdiv", 2, 0xd8f0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
638 #ifdef NON_BROKEN_OPCODES
639 {"fdiv", 2, 0xdcf8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
641 {"fdiv", 2, 0xdcf0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
643 {"fdiv", 0, 0xdcf1, _
, 0, { 0, 0, 0} },
644 {"fdivp", 1, 0xdef8, _
, ShortForm
, { FloatReg
, 0, 0} },
645 {"fdivp", 2, 0xdef8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
646 #ifdef NON_BROKEN_OPCODES
647 {"fdivp", 2, 0xdef8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
648 {"fdivp", 0, 0xdef9, _
, 0, { 0, 0, 0} },
650 {"fdivp", 2, 0xdef0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
651 {"fdivp", 0, 0xdef1, _
, 0, { 0, 0, 0} },
653 {"fdivs", 1, 0xd8, 6, Modrm
, { Mem
, 0, 0} },
654 {"fidivl", 1, 0xda, 6, Modrm
, { Mem
, 0, 0} },
655 {"fdivl", 1, 0xdc, 6, Modrm
, { Mem
, 0, 0} },
656 {"fidivs", 1, 0xde, 6, Modrm
, { Mem
, 0, 0} },
659 {"fdivr", 1, 0xd8f8, _
, ShortForm
, { FloatReg
, 0, 0} },
660 {"fdivr", 2, 0xd8f8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
661 #ifdef NON_BROKEN_OPCODES
662 {"fdivr", 2, 0xdcf0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
664 {"fdivr", 2, 0xdcf8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
666 {"fdivr", 0, 0xdcf9, _
, 0, { 0, 0, 0} },
667 {"fdivrp", 1, 0xdef0, _
, ShortForm
, { FloatReg
, 0, 0} },
668 {"fdivrp", 2, 0xdef0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
669 #ifdef NON_BROKEN_OPCODES
670 {"fdivrp", 2, 0xdef0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
671 {"fdivrp", 0, 0xdef1, _
, 0, { 0, 0, 0} },
673 {"fdivrp", 2, 0xdef8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
674 {"fdivrp", 0, 0xdef9, _
, 0, { 0, 0, 0} },
676 {"fdivrs", 1, 0xd8, 7, Modrm
, { Mem
, 0, 0} },
677 {"fidivrl", 1, 0xda, 7, Modrm
, { Mem
, 0, 0} },
678 {"fdivrl", 1, 0xdc, 7, Modrm
, { Mem
, 0, 0} },
679 {"fidivrs", 1, 0xde, 7, Modrm
, { Mem
, 0, 0} },
681 {"f2xm1", 0, 0xd9f0, _
, 0, { 0, 0, 0} },
682 {"fyl2x", 0, 0xd9f1, _
, 0, { 0, 0, 0} },
683 {"fptan", 0, 0xd9f2, _
, 0, { 0, 0, 0} },
684 {"fpatan", 0, 0xd9f3, _
, 0, { 0, 0, 0} },
685 {"fxtract", 0, 0xd9f4, _
, 0, { 0, 0, 0} },
686 {"fprem1", 0, 0xd9f5, _
, 0, { 0, 0, 0} },
687 {"fdecstp", 0, 0xd9f6, _
, 0, { 0, 0, 0} },
688 {"fincstp", 0, 0xd9f7, _
, 0, { 0, 0, 0} },
689 {"fprem", 0, 0xd9f8, _
, 0, { 0, 0, 0} },
690 {"fyl2xp1", 0, 0xd9f9, _
, 0, { 0, 0, 0} },
691 {"fsqrt", 0, 0xd9fa, _
, 0, { 0, 0, 0} },
692 {"fsincos", 0, 0xd9fb, _
, 0, { 0, 0, 0} },
693 {"frndint", 0, 0xd9fc, _
, 0, { 0, 0, 0} },
694 {"fscale", 0, 0xd9fd, _
, 0, { 0, 0, 0} },
695 {"fsin", 0, 0xd9fe, _
, 0, { 0, 0, 0} },
696 {"fcos", 0, 0xd9ff, _
, 0, { 0, 0, 0} },
698 {"fchs", 0, 0xd9e0, _
, 0, { 0, 0, 0} },
699 {"fabs", 0, 0xd9e1, _
, 0, { 0, 0, 0} },
701 /* processor control */
702 {"fninit", 0, 0xdbe3, _
, 0, { 0, 0, 0} },
703 {"finit", 0, 0xdbe3, _
, FWait
, { 0, 0, 0} },
704 {"fldcw", 1, 0xd9, 5, Modrm
, { Mem
, 0, 0} },
705 {"fnstcw", 1, 0xd9, 7, Modrm
, { Mem
, 0, 0} },
706 {"fstcw", 1, 0xd9, 7, FWait
|Modrm
, { Mem
, 0, 0} },
707 {"fnstsw", 1, 0xdfe0, _
, 0, { Acc
, 0, 0} },
708 {"fnstsw", 1, 0xdd, 7, Modrm
, { Mem
, 0, 0} },
709 {"fnstsw", 0, 0xdfe0, _
, 0, { 0, 0, 0} },
710 {"fstsw", 1, 0xdfe0, _
, FWait
, { Acc
, 0, 0} },
711 {"fstsw", 1, 0xdd, 7, FWait
|Modrm
, { Mem
, 0, 0} },
712 {"fstsw", 0, 0xdfe0, _
, FWait
, { 0, 0, 0} },
713 {"fnclex", 0, 0xdbe2, _
, 0, { 0, 0, 0} },
714 {"fclex", 0, 0xdbe2, _
, FWait
, { 0, 0, 0} },
715 {"fnstenv",1, 0xd9, 6, Modrm
, { Mem
, 0, 0} },
716 {"fstenv", 1, 0xd9, 6, FWait
|Modrm
, { Mem
, 0, 0} },
717 {"fldenv", 1, 0xd9, 4, Modrm
, { Mem
, 0, 0} },
718 {"fnsave", 1, 0xdd, 6, Modrm
, { Mem
, 0, 0} },
719 {"fsave", 1, 0xdd, 6, FWait
|Modrm
, { Mem
, 0, 0} },
720 {"frstor", 1, 0xdd, 4, Modrm
, { Mem
, 0, 0} },
721 /* Short forms of fldenv, fstenv use data size prefix. (At least I
722 think so. The PentPro prog ref I have says address size in one
723 place, operand size elsewhere). FIXME: Are these the right names? */
724 {"fnstenvs",1, 0xd9, 6, Modrm
|Data16
, { Mem
, 0, 0} },
725 {"fstenvs", 1, 0xd9, 6, FWait
|Modrm
|Data16
, { Mem
, 0, 0} },
726 {"fldenvs", 1, 0xd9, 4, Modrm
|Data16
, { Mem
, 0, 0} },
728 {"ffree", 1, 0xddc0, _
, ShortForm
, { FloatReg
, 0, 0} },
729 /* P6:free st(i), pop st */
730 {"ffreep", 1, 0xdfc0, _
, ShortForm
, { FloatReg
, 0, 0} },
731 {"fnop", 0, 0xd9d0, _
, 0, { 0, 0, 0} },
732 #define FWAIT_OPCODE 0x9b
733 {"fwait", 0, 0x9b, _
, 0, { 0, 0, 0} },
736 opcode prefixes; we allow them as seperate insns too
737 (see prefix table below)
739 {"aword", 0, 0x67, _
, 0, { 0, 0, 0} },
740 {"addr16", 0, 0x67, _
, 0, { 0, 0, 0} },
741 {"word", 0, 0x66, _
, 0, { 0, 0, 0} },
742 {"data16", 0, 0x66, _
, 0, { 0, 0, 0} },
743 {"lock", 0, 0xf0, _
, 0, { 0, 0, 0} },
744 {"cs", 0, 0x2e, _
, 0, { 0, 0, 0} },
745 {"ds", 0, 0x3e, _
, 0, { 0, 0, 0} },
746 {"es", 0, 0x26, _
, 0, { 0, 0, 0} },
747 {"fs", 0, 0x64, _
, 0, { 0, 0, 0} },
748 {"gs", 0, 0x65, _
, 0, { 0, 0, 0} },
749 {"ss", 0, 0x36, _
, 0, { 0, 0, 0} },
750 {"rep", 0, 0xf3, _
, 0, { 0, 0, 0} },
751 {"repe", 0, 0xf3, _
, 0, { 0, 0, 0} },
752 {"repz", 0, 0xf3, _
, 0, { 0, 0, 0} },
753 {"repne", 0, 0xf2, _
, 0, { 0, 0, 0} },
754 {"repnz", 0, 0xf2, _
, 0, { 0, 0, 0} },
758 {"bswap", 1, 0x0fc8, _
, ShortForm
, { Reg32
,0,0 } },
759 {"xadd", 2, 0x0fc0, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
760 {"cmpxchg", 2, 0x0fb0, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
761 {"invd", 0, 0x0f08, _
, 0, { 0, 0, 0} },
762 {"wbinvd", 0, 0x0f09, _
, 0, { 0, 0, 0} },
763 {"invlpg", 1, 0x0f01, 7, Modrm
, { Mem
, 0, 0} },
765 /* 586 and late 486 extensions */
766 {"cpuid", 0, 0x0fa2, _
, 0, { 0, 0, 0} },
768 /* Pentium extensions */
769 {"wrmsr", 0, 0x0f30, _
, 0, { 0, 0, 0} },
770 {"rdtsc", 0, 0x0f31, _
, 0, { 0, 0, 0} },
771 {"rdmsr", 0, 0x0f32, _
, 0, { 0, 0, 0} },
772 {"cmpxchg8b", 1, 0x0fc7, 1, Modrm
, { Mem
, 0, 0} },
774 /* Pentium Pro extensions */
775 {"rdpmc", 0, 0x0f33, _
, 0, { 0, 0, 0} },
777 {"ud2", 0, 0x0f0b, _
, 0, {0, 0, 0} }, /* official undefined instr. */
779 {"cmovo", 2, 0x0f40, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
780 {"cmovno", 2, 0x0f41, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
781 {"cmovb", 2, 0x0f42, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
782 {"cmovae", 2, 0x0f43, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
783 {"cmove", 2, 0x0f44, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
784 {"cmovne", 2, 0x0f45, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
785 {"cmovbe", 2, 0x0f46, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
786 {"cmova", 2, 0x0f47, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
787 {"cmovs", 2, 0x0f48, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
788 {"cmovns", 2, 0x0f49, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
789 {"cmovp", 2, 0x0f4a, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
790 {"cmovnp", 2, 0x0f4b, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
791 {"cmovl", 2, 0x0f4c, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
792 {"cmovge", 2, 0x0f4d, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
793 {"cmovle", 2, 0x0f4e, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
794 {"cmovg", 2, 0x0f4f, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
796 {"fcmovb", 2, 0xdac0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
797 {"fcmove", 2, 0xdac8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
798 {"fcmovbe",2, 0xdad0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
799 {"fcmovu", 2, 0xdad8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
800 {"fcmovnb", 2, 0xdbc0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
801 {"fcmovne", 2, 0xdbc8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
802 {"fcmovnbe",2, 0xdbd0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
803 {"fcmovnu", 2, 0xdbd8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
805 {"fcomi", 2, 0xdbf0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
806 {"fucomi", 2, 0xdbe8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
807 {"fcomip", 2, 0xdff0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
808 {"fucomip",2, 0xdfe8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
810 /* MMX instructions. */
812 {"emms", 0, 0x0f77, _
, 0, { 0, 0, 0 } },
813 {"movd", 2, 0x0f6e, _
, Modrm
, { Reg32
|WordMem
, RegMMX
, 0 } },
814 {"movd", 2, 0x0f7e, _
, Modrm
, { RegMMX
, Reg32
|WordMem
, 0 } },
815 {"movq", 2, 0x0f6f, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
816 {"movq", 2, 0x0f7f, _
, Modrm
, { RegMMX
, RegMMX
|WordMem
, 0 } },
817 {"packssdw", 2, 0x0f6b, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
818 {"packsswb", 2, 0x0f63, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
819 {"packuswb", 2, 0x0f67, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
820 {"paddb", 2, 0x0ffc, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
821 {"paddw", 2, 0x0ffd, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
822 {"paddd", 2, 0x0ffe, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
823 {"paddsb", 2, 0x0fec, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
824 {"paddsw", 2, 0x0fed, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
825 {"paddusb", 2, 0x0fdc, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
826 {"paddusw", 2, 0x0fdd, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
827 {"pand", 2, 0x0fdb, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
828 {"pandn", 2, 0x0fdf, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
829 {"pcmpeqb", 2, 0x0f74, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
830 {"pcmpeqw", 2, 0x0f75, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
831 {"pcmpeqd", 2, 0x0f76, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
832 {"pcmpgtb", 2, 0x0f64, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
833 {"pcmpgtw", 2, 0x0f65, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
834 {"pcmpgtd", 2, 0x0f66, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
835 {"pmaddwd", 2, 0x0ff5, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
836 {"pmulhw", 2, 0x0fe5, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
837 {"pmullw", 2, 0x0fd5, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
838 {"por", 2, 0x0feb, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
839 {"psllw", 2, 0x0ff1, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
840 {"psllw", 2, 0x0f71, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
841 {"pslld", 2, 0x0ff2, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
842 {"pslld", 2, 0x0f72, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
843 {"psllq", 2, 0x0ff3, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
844 {"psllq", 2, 0x0f73, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
845 {"psraw", 2, 0x0fe1, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
846 {"psraw", 2, 0x0f71, 4, Modrm
, { Imm8
, RegMMX
, 0 } },
847 {"psrad", 2, 0x0fe2, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
848 {"psrad", 2, 0x0f72, 4, Modrm
, { Imm8
, RegMMX
, 0 } },
849 {"psrlw", 2, 0x0fd1, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
850 {"psrlw", 2, 0x0f71, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
851 {"psrld", 2, 0x0fd2, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
852 {"psrld", 2, 0x0f72, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
853 {"psrlq", 2, 0x0fd3, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
854 {"psrlq", 2, 0x0f73, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
855 {"psubb", 2, 0x0ff8, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
856 {"psubw", 2, 0x0ff9, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
857 {"psubd", 2, 0x0ffa, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
858 {"psubsb", 2, 0x0fe8, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
859 {"psubsw", 2, 0x0fe9, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
860 {"psubusb", 2, 0x0fd8, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
861 {"psubusw", 2, 0x0fd9, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
862 {"punpckhbw", 2, 0x0f68, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
863 {"punpckhwd", 2, 0x0f69, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
864 {"punpckhdq", 2, 0x0f6a, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
865 {"punpcklbw", 2, 0x0f60, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
866 {"punpcklwd", 2, 0x0f61, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
867 {"punpckldq", 2, 0x0f62, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
868 {"pxor", 2, 0x0fef, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
870 {"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
874 static const template *const i386_optab_end
875 = i386_optab
+ sizeof (i386_optab
)/sizeof(i386_optab
[0]);
877 /* 386 register table */
879 static const reg_entry i386_regtab
[] = {
881 {"al", Reg8
|Acc
, 0}, {"cl", Reg8
|ShiftCount
, 1}, {"dl", Reg8
, 2},
883 {"ah", Reg8
, 4}, {"ch", Reg8
, 5}, {"dh", Reg8
, 6}, {"bh", Reg8
, 7},
885 {"ax", Reg16
|Acc
, 0}, {"cx", Reg16
, 1}, {"dx", Reg16
|InOutPortReg
, 2}, {"bx", Reg16
, 3},
886 {"sp", Reg16
, 4}, {"bp", Reg16
, 5}, {"si", Reg16
, 6}, {"di", Reg16
, 7},
888 {"eax", Reg32
|Acc
, 0}, {"ecx", Reg32
, 1}, {"edx", Reg32
, 2}, {"ebx", Reg32
, 3},
889 {"esp", Reg32
, 4}, {"ebp", Reg32
, 5}, {"esi", Reg32
, 6}, {"edi", Reg32
, 7},
890 /* segment registers */
891 {"es", SReg2
, 0}, {"cs", SReg2
, 1}, {"ss", SReg2
, 2},
892 {"ds", SReg2
, 3}, {"fs", SReg3
, 4}, {"gs", SReg3
, 5},
893 /* control registers */
894 {"cr0", Control
, 0}, {"cr2", Control
, 2}, {"cr3", Control
, 3},
896 /* debug registers */
897 {"db0", Debug
, 0}, {"db1", Debug
, 1}, {"db2", Debug
, 2},
898 {"db3", Debug
, 3}, {"db6", Debug
, 6}, {"db7", Debug
, 7},
899 {"dr0", Debug
, 0}, {"dr1", Debug
, 1}, {"dr2", Debug
, 2},
900 {"dr3", Debug
, 3}, {"dr6", Debug
, 6}, {"dr7", Debug
, 7},
902 {"tr3", Test
, 3}, {"tr4", Test
, 4}, {"tr5", Test
, 5},
903 {"tr6", Test
, 6}, {"tr7", Test
, 7},
904 /* float registers */
905 {"st(0)", FloatReg
|FloatAcc
, 0},
906 {"st", FloatReg
|FloatAcc
, 0},
907 {"st(1)", FloatReg
, 1}, {"st(2)", FloatReg
, 2},
908 {"st(3)", FloatReg
, 3}, {"st(4)", FloatReg
, 4}, {"st(5)", FloatReg
, 5},
909 {"st(6)", FloatReg
, 6}, {"st(7)", FloatReg
, 7},
910 {"mm0", RegMMX
, 0}, {"mm1", RegMMX
, 1}, {"mm2", RegMMX
, 2},
911 {"mm3", RegMMX
, 3}, {"mm4", RegMMX
, 4}, {"mm5", RegMMX
, 5},
912 {"mm6", RegMMX
, 6}, {"mm7", RegMMX
, 7}
915 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
917 static const reg_entry
*const i386_regtab_end
918 = i386_regtab
+ sizeof(i386_regtab
)/sizeof(i386_regtab
[0]);
921 static const seg_entry cs
= { "cs", 0x2e };
922 static const seg_entry ds
= { "ds", 0x3e };
923 static const seg_entry ss
= { "ss", 0x36 };
924 static const seg_entry es
= { "es", 0x26 };
925 static const seg_entry fs
= { "fs", 0x64 };
926 static const seg_entry gs
= { "gs", 0x65 };
927 static const seg_entry null
= { "", 0x0 };
930 This table is used to store the default segment register implied by all
931 possible memory addressing modes.
932 It is indexed by the mode & modrm entries of the modrm byte as follows:
933 index = (mode<<3) | modrm;
935 static const seg_entry
*const one_byte_segment_defaults
[] = {
937 &ds
, &ds
, &ds
, &ds
, &null
, &ds
, &ds
, &ds
,
939 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
941 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
942 /* mode 3 --- not a memory reference; never referenced */
945 static const seg_entry
*const two_byte_segment_defaults
[] = {
947 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
949 &ds
, &ds
, &ds
, &ds
, &ss
, &ss
, &ds
, &ds
,
951 &ds
, &ds
, &ds
, &ds
, &ss
, &ss
, &ds
, &ds
,
952 /* mode 3 --- not a memory reference; never referenced */
955 static const prefix_entry i386_prefixtab
[] = {
956 #define ADDR_PREFIX_OPCODE 0x67
957 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
958 * (How is this useful?) */
959 #define WORD_PREFIX_OPCODE 0x66
960 { "data16", 0x66 }, /* operand size prefix */
961 #define LOCK_PREFIX_OPCODE 0xf0
962 { "lock", 0xf0 }, /* bus lock prefix */
963 { "wait", 0x9b }, /* wait for coprocessor, not really a prefix */
964 #define CS_PREFIX_OPCODE 0x2e
965 { "cs", 0x2e }, /* segment overrides ... */
966 #define DS_PREFIX_OPCODE 0x3e
968 #define ES_PREFIX_OPCODE 0x26
970 #define FS_PREFIX_OPCODE 0x64
972 #define GS_PREFIX_OPCODE 0x65
974 #define SS_PREFIX_OPCODE 0x36
976 /* REPE & REPNE used to detect rep/repne with a non-string instruction */
979 { "rep", 0xf3 }, /* repeat string instructions */
980 { "repe", 0xf3 }, { "repz", 0xf3 },
981 { "repne", 0xf2 }, { "repnz", 0xf2 }
984 static const prefix_entry
*const i386_prefixtab_end
985 = i386_prefixtab
+ sizeof(i386_prefixtab
)/sizeof(i386_prefixtab
[0]);
987 /* end of i386-opcode.h */