1 /* i386-opcode.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /* The NON_BROKEN_OPCODES cases use the operands in the reverse order
21 from that documented in the Intel manuals. The opcode values are
22 such that they actually generate different instructions. These
23 values must not be changed, as they are the values generated by the
24 UnixWare assembler, and possibly other ix86 assemblers. */
26 static const template i386_optab
[] = {
29 /* move instructions */
30 #define MOV_AX_DISP32 0xa0
31 { "mov", 2, 0xa0, _
, DW
|NoModrm
, { Disp32
, Acc
, 0 } },
32 { "mov", 2, 0x88, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
33 { "mov", 2, 0xb0, _
, ShortFormW
, { Imm
, Reg
, 0 } },
34 { "mov", 2, 0xc6, _
, W
|Modrm
, { Imm
, Reg
|Mem
, 0 } },
35 /* The next instruction accepts WordReg so that `movl %gs,%esi' can be
36 used to move a segment register to a 32 bit register without using
37 a size prefix, which works although Intel does not document it. I
38 think it zeroes the upper 16 bits in the 32 bit register. */
39 { "mov", 2, 0x8c, _
, D
|Modrm
, { SReg3
|SReg2
, WordReg
|WordMem
, 0 } },
40 /* move to/from control debug registers */
41 { "mov", 2, 0x0f20, _
, D
|Modrm
, { Control
, Reg32
, 0} },
42 { "mov", 2, 0x0f21, _
, D
|Modrm
, { Debug
, Reg32
, 0} },
43 { "mov", 2, 0x0f24, _
, D
|Modrm
, { Test
, Reg32
, 0} },
45 /* move with sign extend */
46 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
47 conflict with the "movs" string move instruction. Thus,
48 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
49 is not kosher; we must seperate the two instructions. */
50 {"movsbl", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
|Data32
, { Reg8
|Mem
, Reg32
, 0} },
51 {"movsbw", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
|Data16
, { Reg8
|Mem
, Reg16
, 0} },
52 {"movswl", 2, 0x0fbf, _
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
54 /* move with zero extend */
55 {"movzb", 2, 0x0fb6, _
, ReverseRegRegmem
|Modrm
, { Reg8
|Mem
, Reg16
|Reg32
, 0} },
56 {"movzwl", 2, 0x0fb7, _
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
58 /* push instructions */
59 {"push", 1, 0x50, _
, ShortForm
, { WordReg
,0,0 } },
60 {"push", 1, 0xff, 0x6, Modrm
, { WordReg
|WordMem
, 0, 0 } },
61 {"push", 1, 0x6a, _
, NoModrm
, { Imm8S
, 0, 0} },
62 {"push", 1, 0x68, _
, NoModrm
, { Imm16
|Imm32
, 0, 0} },
63 {"push", 1, 0x06, _
, Seg2ShortForm
, { SReg2
,0,0 } },
64 {"push", 1, 0x0fa0, _
, Seg3ShortForm
, { SReg3
,0,0 } },
66 {"pusha", 0, 0x60, _
, NoModrm
, { 0, 0, 0 } },
68 /* pop instructions */
69 {"pop", 1, 0x58, _
, ShortForm
, { WordReg
,0,0 } },
70 {"pop", 1, 0x8f, 0x0, Modrm
, { WordReg
|WordMem
, 0, 0 } },
71 #define POP_SEG_SHORT 0x7
72 {"pop", 1, 0x07, _
, Seg2ShortForm
, { SReg2
,0,0 } },
73 {"pop", 1, 0x0fa1, _
, Seg3ShortForm
, { SReg3
,0,0 } },
75 {"popa", 0, 0x61, _
, NoModrm
, { 0, 0, 0 } },
77 /* xchg exchange instructions
78 xchg commutes: we allow both operand orders */
79 {"xchg", 2, 0x90, _
, ShortForm
, { WordReg
, Acc
, 0 } },
80 {"xchg", 2, 0x90, _
, ShortForm
, { Acc
, WordReg
, 0 } },
81 {"xchg", 2, 0x86, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
82 {"xchg", 2, 0x86, _
, W
|Modrm
, { Reg
|Mem
, Reg
, 0 } },
84 /* in/out from ports */
85 {"in", 2, 0xe4, _
, W
|NoModrm
, { Imm8
, Acc
, 0 } },
86 {"in", 2, 0xec, _
, W
|NoModrm
, { InOutPortReg
, Acc
, 0 } },
87 {"in", 1, 0xe4, _
, W
|NoModrm
, { Imm8
, 0, 0 } },
88 {"in", 1, 0xec, _
, W
|NoModrm
, { InOutPortReg
, 0, 0 } },
89 {"out", 2, 0xe6, _
, W
|NoModrm
, { Acc
, Imm8
, 0 } },
90 {"out", 2, 0xee, _
, W
|NoModrm
, { Acc
, InOutPortReg
, 0 } },
91 {"out", 1, 0xe6, _
, W
|NoModrm
, { Imm8
, 0, 0 } },
92 {"out", 1, 0xee, _
, W
|NoModrm
, { InOutPortReg
, 0, 0 } },
94 /* load effective address */
95 {"lea", 2, 0x8d, _
, Modrm
, { WordMem
, WordReg
, 0 } },
97 /* load segment registers from memory */
98 {"lds", 2, 0xc5, _
, Modrm
, { Mem
, Reg32
, 0} },
99 {"les", 2, 0xc4, _
, Modrm
, { Mem
, Reg32
, 0} },
100 {"lfs", 2, 0x0fb4, _
, Modrm
, { Mem
, Reg32
, 0} },
101 {"lgs", 2, 0x0fb5, _
, Modrm
, { Mem
, Reg32
, 0} },
102 {"lss", 2, 0x0fb2, _
, Modrm
, { Mem
, Reg32
, 0} },
104 /* flags register instructions */
105 {"clc", 0, 0xf8, _
, NoModrm
, { 0, 0, 0} },
106 {"cld", 0, 0xfc, _
, NoModrm
, { 0, 0, 0} },
107 {"cli", 0, 0xfa, _
, NoModrm
, { 0, 0, 0} },
108 {"clts", 0, 0x0f06, _
, NoModrm
, { 0, 0, 0} },
109 {"cmc", 0, 0xf5, _
, NoModrm
, { 0, 0, 0} },
110 {"lahf", 0, 0x9f, _
, NoModrm
, { 0, 0, 0} },
111 {"sahf", 0, 0x9e, _
, NoModrm
, { 0, 0, 0} },
112 {"pushfl", 0, 0x9c, _
, NoModrm
|Data32
, { 0, 0, 0} },
113 {"popfl", 0, 0x9d, _
, NoModrm
|Data32
, { 0, 0, 0} },
114 {"pushfw", 0, 0x9c, _
, NoModrm
|Data16
, { 0, 0, 0} },
115 {"popfw", 0, 0x9d, _
, NoModrm
|Data16
, { 0, 0, 0} },
116 {"pushf", 0, 0x9c, _
, NoModrm
, { 0, 0, 0} },
117 {"popf", 0, 0x9d, _
, NoModrm
, { 0, 0, 0} },
118 {"stc", 0, 0xf9, _
, NoModrm
, { 0, 0, 0} },
119 {"std", 0, 0xfd, _
, NoModrm
, { 0, 0, 0} },
120 {"sti", 0, 0xfb, _
, NoModrm
, { 0, 0, 0} },
122 {"add", 2, 0x0, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
123 {"add", 2, 0x83, 0, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
124 {"add", 2, 0x4, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
125 {"add", 2, 0x80, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
127 {"inc", 1, 0x40, _
, ShortForm
, { WordReg
, 0, 0} },
128 {"inc", 1, 0xfe, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
130 {"sub", 2, 0x28, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
131 {"sub", 2, 0x83, 5, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
132 {"sub", 2, 0x2c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
133 {"sub", 2, 0x80, 5, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
135 {"dec", 1, 0x48, _
, ShortForm
, { WordReg
, 0, 0} },
136 {"dec", 1, 0xfe, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
138 {"sbb", 2, 0x18, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
139 {"sbb", 2, 0x83, 3, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
140 {"sbb", 2, 0x1c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
141 {"sbb", 2, 0x80, 3, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
143 {"cmp", 2, 0x38, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
144 {"cmp", 2, 0x83, 7, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
145 {"cmp", 2, 0x3c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
146 {"cmp", 2, 0x80, 7, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
148 {"test", 2, 0x84, _
, W
|Modrm
, { Reg
|Mem
, Reg
, 0} },
149 {"test", 2, 0x84, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0} },
150 {"test", 2, 0xa8, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
151 {"test", 2, 0xf6, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
153 {"and", 2, 0x20, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
154 {"and", 2, 0x83, 4, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
155 {"and", 2, 0x24, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
156 {"and", 2, 0x80, 4, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
158 {"or", 2, 0x08, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
159 {"or", 2, 0x83, 1, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
160 {"or", 2, 0x0c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
161 {"or", 2, 0x80, 1, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
163 {"xor", 2, 0x30, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
164 {"xor", 2, 0x83, 6, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
165 {"xor", 2, 0x34, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
166 {"xor", 2, 0x80, 6, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
168 /* iclr with 1 operand is really xor with 2 operands. */
169 {"clr", 1, 0x30, _
, W
|Modrm
|iclrKludge
, { Reg
} },
171 {"adc", 2, 0x10, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
172 {"adc", 2, 0x83, 2, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
173 {"adc", 2, 0x14, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
174 {"adc", 2, 0x80, 2, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
176 {"neg", 1, 0xf6, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
177 {"not", 1, 0xf6, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
179 {"aaa", 0, 0x37, _
, NoModrm
, { 0, 0, 0} },
180 {"aas", 0, 0x3f, _
, NoModrm
, { 0, 0, 0} },
181 {"daa", 0, 0x27, _
, NoModrm
, { 0, 0, 0} },
182 {"das", 0, 0x2f, _
, NoModrm
, { 0, 0, 0} },
183 {"aad", 0, 0xd50a, _
, NoModrm
, { 0, 0, 0} },
184 {"aam", 0, 0xd40a, _
, NoModrm
, { 0, 0, 0} },
186 /* conversion insns */
187 /* conversion: intel naming */
188 {"cbw", 0, 0x98, _
, NoModrm
|Data16
, { 0, 0, 0} },
189 {"cwd", 0, 0x99, _
, NoModrm
|Data16
, { 0, 0, 0} },
190 {"cwde", 0, 0x98, _
, NoModrm
|Data32
, { 0, 0, 0} },
191 {"cdq", 0, 0x99, _
, NoModrm
|Data32
, { 0, 0, 0} },
193 {"cbtw", 0, 0x98, _
, NoModrm
|Data16
, { 0, 0, 0} },
194 {"cwtl", 0, 0x98, _
, NoModrm
|Data32
, { 0, 0, 0} },
195 {"cwtd", 0, 0x99, _
, NoModrm
|Data16
, { 0, 0, 0} },
196 {"cltd", 0, 0x99, _
, NoModrm
|Data32
, { 0, 0, 0} },
198 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
199 expanding 64-bit multiplies, and *cannot* be selected to accomplish
200 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
201 These multiplies can only be selected with single operand forms. */
202 {"mul", 1, 0xf6, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
203 {"imul", 1, 0xf6, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
208 /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
209 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
210 '%eax' in the reg field and '%ecx' in the regmem field if we did not
212 {"imul", 2, 0x0faf, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
213 {"imul", 3, 0x6b, _
, Modrm
|ReverseRegRegmem
, { Imm8S
, WordReg
|Mem
, WordReg
} },
214 {"imul", 3, 0x69, _
, Modrm
|ReverseRegRegmem
, { Imm16
|Imm32
, WordReg
|Mem
, WordReg
} },
216 imul with 2 operands mimicks imul with 3 by puting register both
217 in i.rm.reg & i.rm.regmem fields
219 {"imul", 2, 0x6b, _
, Modrm
|imulKludge
, { Imm8S
, WordReg
, 0} },
220 {"imul", 2, 0x69, _
, Modrm
|imulKludge
, { Imm16
|Imm32
, WordReg
, 0} },
221 {"div", 1, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, 0, 0} },
222 {"div", 2, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
223 {"idiv", 1, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
224 {"idiv", 2, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
226 {"rol", 2, 0xd0, 0, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
227 {"rol", 2, 0xc0, 0, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
228 {"rol", 2, 0xd2, 0, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
229 {"rol", 1, 0xd0, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
231 {"ror", 2, 0xd0, 1, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
232 {"ror", 2, 0xc0, 1, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
233 {"ror", 2, 0xd2, 1, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
234 {"ror", 1, 0xd0, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
236 {"rcl", 2, 0xd0, 2, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
237 {"rcl", 2, 0xc0, 2, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
238 {"rcl", 2, 0xd2, 2, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
239 {"rcl", 1, 0xd0, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
241 {"rcr", 2, 0xd0, 3, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
242 {"rcr", 2, 0xc0, 3, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
243 {"rcr", 2, 0xd2, 3, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
244 {"rcr", 1, 0xd0, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
246 {"sal", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
247 {"sal", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
248 {"sal", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
249 {"sal", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
250 {"shl", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
251 {"shl", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
252 {"shl", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
253 {"shl", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
255 {"shld", 3, 0x0fa4, _
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
256 {"shld", 3, 0x0fa5, _
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
257 {"shld", 2, 0x0fa5, _
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
259 {"shr", 2, 0xd0, 5, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
260 {"shr", 2, 0xc0, 5, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
261 {"shr", 2, 0xd2, 5, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
262 {"shr", 1, 0xd0, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
264 {"shrd", 3, 0x0fac, _
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
265 {"shrd", 3, 0x0fad, _
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
266 {"shrd", 2, 0x0fad, _
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
268 {"sar", 2, 0xd0, 7, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
269 {"sar", 2, 0xc0, 7, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
270 {"sar", 2, 0xd2, 7, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
271 {"sar", 1, 0xd0, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
273 /* control transfer instructions */
274 #define CALL_PC_RELATIVE 0xe8
275 {"call", 1, 0xe8, _
, JumpDword
, { Disp32
, 0, 0} },
276 {"call", 1, 0xff, 2, Modrm
|Data32
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
277 {"callw", 1, 0xff, 2, Modrm
|Data16
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
278 #define CALL_FAR_IMMEDIATE 0x9a
279 {"lcall", 2, 0x9a, _
, JumpInterSegment
, { Imm16
, Imm32
, 0} },
280 {"lcall", 1, 0xff, 3, Modrm
|Data32
, { Mem
, 0, 0} },
281 {"lcallw", 1, 0xff, 3, Modrm
|Data16
, { Mem
, 0, 0} },
283 #define JUMP_PC_RELATIVE 0xeb
284 {"jmp", 1, 0xeb, _
, Jump
, { Disp
, 0, 0} },
285 {"jmp", 1, 0xff, 4, Modrm
, { Reg32
|Mem
|JumpAbsolute
, 0, 0} },
286 #define JUMP_FAR_IMMEDIATE 0xea
287 {"ljmp", 2, 0xea, _
, JumpInterSegment
, { Imm16
, Imm32
, 0} },
288 {"ljmp", 1, 0xff, 5, Modrm
|Data32
, { Mem
, 0, 0} },
290 {"ret", 0, 0xc3, _
, NoModrm
|Data32
, { 0, 0, 0} },
291 {"ret", 1, 0xc2, _
, NoModrm
|Data32
, { Imm16
, 0, 0} },
292 {"retw", 0, 0xc3, _
, NoModrm
|Data16
, { 0, 0, 0} },
293 {"retw", 1, 0xc2, _
, NoModrm
|Data16
, { Imm16
, 0, 0} },
294 {"lret", 0, 0xcb, _
, NoModrm
|Data32
, { 0, 0, 0} },
295 {"lret", 1, 0xca, _
, NoModrm
|Data32
, { Imm16
, 0, 0} },
296 {"lretw", 0, 0xcb, _
, NoModrm
|Data16
, { 0, 0, 0} },
297 {"lretw", 1, 0xca, _
, NoModrm
|Data16
, { Imm16
, 0, 0} },
298 {"enter", 2, 0xc8, _
, NoModrm
|Data32
, { Imm16
, Imm8
, 0} },
299 {"leave", 0, 0xc9, _
, NoModrm
|Data32
, { 0, 0, 0} },
300 {"enterw", 2, 0xc8, _
, NoModrm
|Data16
, { Imm16
, Imm8
, 0} },
301 {"leavew", 0, 0xc9, _
, NoModrm
|Data16
, { 0, 0, 0} },
303 /* conditional jumps */
304 {"jo", 1, 0x70, _
, Jump
, { Disp
, 0, 0} },
306 {"jno", 1, 0x71, _
, Jump
, { Disp
, 0, 0} },
308 {"jb", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
309 {"jc", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
310 {"jnae", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
312 {"jnb", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
313 {"jnc", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
314 {"jae", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
316 {"je", 1, 0x74, _
, Jump
, { Disp
, 0, 0} },
317 {"jz", 1, 0x74, _
, Jump
, { Disp
, 0, 0} },
319 {"jne", 1, 0x75, _
, Jump
, { Disp
, 0, 0} },
320 {"jnz", 1, 0x75, _
, Jump
, { Disp
, 0, 0} },
322 {"jbe", 1, 0x76, _
, Jump
, { Disp
, 0, 0} },
323 {"jna", 1, 0x76, _
, Jump
, { Disp
, 0, 0} },
325 {"jnbe", 1, 0x77, _
, Jump
, { Disp
, 0, 0} },
326 {"ja", 1, 0x77, _
, Jump
, { Disp
, 0, 0} },
328 {"js", 1, 0x78, _
, Jump
, { Disp
, 0, 0} },
330 {"jns", 1, 0x79, _
, Jump
, { Disp
, 0, 0} },
332 {"jp", 1, 0x7a, _
, Jump
, { Disp
, 0, 0} },
333 {"jpe", 1, 0x7a, _
, Jump
, { Disp
, 0, 0} },
335 {"jnp", 1, 0x7b, _
, Jump
, { Disp
, 0, 0} },
336 {"jpo", 1, 0x7b, _
, Jump
, { Disp
, 0, 0} },
338 {"jl", 1, 0x7c, _
, Jump
, { Disp
, 0, 0} },
339 {"jnge", 1, 0x7c, _
, Jump
, { Disp
, 0, 0} },
341 {"jnl", 1, 0x7d, _
, Jump
, { Disp
, 0, 0} },
342 {"jge", 1, 0x7d, _
, Jump
, { Disp
, 0, 0} },
344 {"jle", 1, 0x7e, _
, Jump
, { Disp
, 0, 0} },
345 {"jng", 1, 0x7e, _
, Jump
, { Disp
, 0, 0} },
347 {"jnle", 1, 0x7f, _
, Jump
, { Disp
, 0, 0} },
348 {"jg", 1, 0x7f, _
, Jump
, { Disp
, 0, 0} },
350 #define IS_JUMP_ON_CX_ZERO(o) \
353 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
354 {"jcxz", 1, 0xe3, _
, JumpByte
|Data16
, { Disp
, 0, 0} },
355 {"jecxz", 1, 0xe3, _
, JumpByte
|Data32
, { Disp
, 0, 0} },
357 #define IS_LOOP_ECX_TIMES(o) \
358 (o == 0xe2 || o == 0xe1 || o == 0xe0)
360 {"loop", 1, 0xe2, _
, JumpByte
, { Disp
, 0, 0} },
362 {"loopz", 1, 0xe1, _
, JumpByte
, { Disp
, 0, 0} },
363 {"loope", 1, 0xe1, _
, JumpByte
, { Disp
, 0, 0} },
365 {"loopnz", 1, 0xe0, _
, JumpByte
, { Disp
, 0, 0} },
366 {"loopne", 1, 0xe0, _
, JumpByte
, { Disp
, 0, 0} },
368 /* set byte on flag instructions */
369 {"seto", 1, 0x0f90, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
371 {"setno", 1, 0x0f91, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
373 {"setb", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
374 {"setc", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
375 {"setnae", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
377 {"setnb", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
378 {"setnc", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
379 {"setae", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
381 {"sete", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
382 {"setz", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
384 {"setne", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
385 {"setnz", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
387 {"setbe", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
388 {"setna", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
390 {"setnbe", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
391 {"seta", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
393 {"sets", 1, 0x0f98, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
395 {"setns", 1, 0x0f99, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
397 {"setp", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
398 {"setpe", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
400 {"setnp", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
401 {"setpo", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
403 {"setl", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
404 {"setnge", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
406 {"setnl", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
407 {"setge", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
409 {"setle", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
410 {"setng", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
412 {"setnle", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
413 {"setg", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
415 #define IS_STRING_INSTRUCTION(o) \
416 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
417 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
420 /* string manipulation */
421 {"cmps", 0, 0xa6, _
, W
|NoModrm
, { 0, 0, 0} },
422 {"scmp", 0, 0xa6, _
, W
|NoModrm
, { 0, 0, 0} },
423 {"ins", 0, 0x6c, _
, W
|NoModrm
, { 0, 0, 0} },
424 {"outs", 0, 0x6e, _
, W
|NoModrm
, { 0, 0, 0} },
425 {"lods", 0, 0xac, _
, W
|NoModrm
, { 0, 0, 0} },
426 {"slod", 0, 0xac, _
, W
|NoModrm
, { 0, 0, 0} },
427 {"movs", 0, 0xa4, _
, W
|NoModrm
, { 0, 0, 0} },
428 {"smov", 0, 0xa4, _
, W
|NoModrm
, { 0, 0, 0} },
429 {"scas", 0, 0xae, _
, W
|NoModrm
, { 0, 0, 0} },
430 {"ssca", 0, 0xae, _
, W
|NoModrm
, { 0, 0, 0} },
431 {"stos", 0, 0xaa, _
, W
|NoModrm
, { 0, 0, 0} },
432 {"ssto", 0, 0xaa, _
, W
|NoModrm
, { 0, 0, 0} },
433 {"xlat", 0, 0xd7, _
, NoModrm
, { 0, 0, 0} },
435 /* bit manipulation */
436 {"bsf", 2, 0x0fbc, _
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
437 {"bsr", 2, 0x0fbd, _
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
438 {"bt", 2, 0x0fa3, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
439 {"bt", 2, 0x0fba, 4, Modrm
, { Imm8
, Reg
|Mem
, 0} },
440 {"btc", 2, 0x0fbb, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
441 {"btc", 2, 0x0fba, 7, Modrm
, { Imm8
, Reg
|Mem
, 0} },
442 {"btr", 2, 0x0fb3, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
443 {"btr", 2, 0x0fba, 6, Modrm
, { Imm8
, Reg
|Mem
, 0} },
444 {"bts", 2, 0x0fab, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
445 {"bts", 2, 0x0fba, 5, Modrm
, { Imm8
, Reg
|Mem
, 0} },
447 /* interrupts & op. sys insns */
448 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
450 #define INT_OPCODE 0xcd
451 #define INT3_OPCODE 0xcc
452 {"int", 1, 0xcd, _
, NoModrm
, { Imm8
, 0, 0} },
453 {"int3", 0, 0xcc, _
, NoModrm
, { 0, 0, 0} },
454 {"into", 0, 0xce, _
, NoModrm
, { 0, 0, 0} },
455 {"iret", 0, 0xcf, _
, NoModrm
|Data32
, { 0, 0, 0} },
456 {"iretw", 0, 0xcf, _
, NoModrm
|Data16
, { 0, 0, 0} },
457 /* i386sl, i486sl, later 486, and Pentium */
458 {"rsm", 0, 0x0faa, _
, NoModrm
,{ 0, 0, 0} },
460 {"boundl", 2, 0x62, _
, Modrm
|Data32
, { Reg32
, Mem
, 0} },
461 {"boundw", 2, 0x62, _
, Modrm
|Data16
, { Reg16
, Mem
, 0} },
463 {"hlt", 0, 0xf4, _
, NoModrm
, { 0, 0, 0} },
464 {"wait", 0, 0x9b, _
, NoModrm
, { 0, 0, 0} },
465 /* nop is actually 'xchgl %eax, %eax' */
466 {"nop", 0, 0x90, _
, NoModrm
, { 0, 0, 0} },
468 /* protection control */
469 {"arpl", 2, 0x63, _
, Modrm
, { Reg16
, Reg16
|Mem
, 0} },
470 {"lar", 2, 0x0f02, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
471 {"lgdt", 1, 0x0f01, 2, Modrm
|LinearAddress
, { Mem
, 0, 0} },
472 {"lidt", 1, 0x0f01, 3, Modrm
|LinearAddress
, { Mem
, 0, 0} },
473 {"lldt", 1, 0x0f00, 2, Modrm
, { WordReg
|Mem
, 0, 0} },
474 {"lmsw", 1, 0x0f01, 6, Modrm
, { WordReg
|Mem
, 0, 0} },
475 {"lsl", 2, 0x0f03, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
476 {"ltr", 1, 0x0f00, 3, Modrm
, { WordReg
|Mem
, 0, 0} },
478 {"sgdt", 1, 0x0f01, 0, Modrm
, { Mem
, 0, 0} },
479 {"sidt", 1, 0x0f01, 1, Modrm
, { Mem
, 0, 0} },
480 {"sldt", 1, 0x0f00, 0, Modrm
, { WordReg
|Mem
, 0, 0} },
481 {"smsw", 1, 0x0f01, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
482 {"str", 1, 0x0f00, 1, Modrm
, { Reg16
|Mem
, 0, 0} },
484 {"verr", 1, 0x0f00, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
485 {"verw", 1, 0x0f00, 5, Modrm
, { WordReg
|Mem
, 0, 0} },
487 /* floating point instructions */
490 {"fld", 1, 0xd9c0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
491 {"flds", 1, 0xd9, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem float */
492 {"fldl", 1, 0xdd, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem double */
493 {"fldl", 1, 0xd9c0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
494 {"fild", 1, 0xdf, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem word (16) */
495 {"fildl", 1, 0xdb, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem dword (32) */
496 {"fildq",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
497 {"fildll",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
498 {"fldt", 1, 0xdb, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem efloat */
499 {"fbld", 1, 0xdf, 4, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem bcd */
502 {"fst", 1, 0xddd0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
503 {"fsts", 1, 0xd9, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
504 {"fstl", 1, 0xdd, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
505 {"fstl", 1, 0xddd0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
506 {"fist", 1, 0xdf, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
507 {"fistl", 1, 0xdb, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
509 /* store (with pop) */
510 {"fstp", 1, 0xddd8, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
511 {"fstps", 1, 0xd9, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
512 {"fstpl", 1, 0xdd, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
513 {"fstpl", 1, 0xddd8, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
514 {"fistp", 1, 0xdf, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
515 {"fistpl",1, 0xdb, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
516 {"fistpq",1, 0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
517 {"fistpll",1,0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
518 {"fstpt", 1, 0xdb, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem efloat */
519 {"fbstp", 1, 0xdf, 6, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem bcd */
521 /* exchange %st<n> with %st0 */
522 {"fxch", 1, 0xd9c8, _
, ShortForm
, { FloatReg
, 0, 0} },
523 {"fxch", 0, 0xd9c9, _
, NoModrm
, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
525 /* comparison (without pop) */
526 {"fcom", 1, 0xd8d0, _
, ShortForm
, { FloatReg
, 0, 0} },
527 {"fcoms", 1, 0xd8, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
528 {"ficoml", 1, 0xda, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
529 {"fcoml", 1, 0xdc, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
530 {"fcoml", 1, 0xd8d0, _
, ShortForm
, { FloatReg
, 0, 0} },
531 {"ficoms", 1, 0xde, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
533 /* comparison (with pop) */
534 {"fcomp", 1, 0xd8d8, _
, ShortForm
, { FloatReg
, 0, 0} },
535 {"fcomp", 0, 0xd8d9, _
, NoModrm
, {0, 0, 0} }, /* fcomp %st, %st(1) */
536 {"fcomps", 1, 0xd8, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
537 {"ficompl", 1, 0xda, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
538 {"fcompl", 1, 0xdc, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
539 {"fcompl", 1, 0xd8d8, _
, ShortForm
, { FloatReg
, 0, 0} },
540 {"ficomps", 1, 0xde, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
541 {"fcompp", 0, 0xded9, _
, NoModrm
, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
543 /* unordered comparison (with pop) */
544 {"fucom", 1, 0xdde0, _
, ShortForm
, { FloatReg
, 0, 0} },
545 {"fucomp", 1, 0xdde8, _
, ShortForm
, { FloatReg
, 0, 0} },
546 {"fucompp", 0, 0xdae9, _
, NoModrm
, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
548 {"ftst", 0, 0xd9e4, _
, NoModrm
, { 0, 0, 0} }, /* test %st0 */
549 {"fxam", 0, 0xd9e5, _
, NoModrm
, { 0, 0, 0} }, /* examine %st0 */
551 /* load constants into %st0 */
552 {"fld1", 0, 0xd9e8, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- 1.0 */
553 {"fldl2t", 0, 0xd9e9, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- log2(10) */
554 {"fldl2e", 0, 0xd9ea, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- log2(e) */
555 {"fldpi", 0, 0xd9eb, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- pi */
556 {"fldlg2", 0, 0xd9ec, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- log10(2) */
557 {"fldln2", 0, 0xd9ed, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- ln(2) */
558 {"fldz", 0, 0xd9ee, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- 0.0 */
563 {"fadd", 1, 0xd8c0, _
, ShortForm
, { FloatReg
, 0, 0} },
564 {"fadd", 2, 0xd8c0, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
565 {"fadd", 0, 0xdcc1, _
, NoModrm
, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
566 {"faddp", 1, 0xdec0, _
, ShortForm
, { FloatReg
, 0, 0} },
567 {"faddp", 2, 0xdec0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
568 {"faddp", 2, 0xdec0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
569 {"faddp", 0, 0xdec1, _
, NoModrm
, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
570 {"fadds", 1, 0xd8, 0, Modrm
, { Mem
, 0, 0} },
571 {"fiaddl", 1, 0xda, 0, Modrm
, { Mem
, 0, 0} },
572 {"faddl", 1, 0xdc, 0, Modrm
, { Mem
, 0, 0} },
573 {"fiadds", 1, 0xde, 0, Modrm
, { Mem
, 0, 0} },
576 /* Note: intel has decided that certain of these operations are reversed
577 in assembler syntax. */
578 {"fsub", 1, 0xd8e0, _
, ShortForm
, { FloatReg
, 0, 0} },
579 {"fsub", 2, 0xd8e0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
580 #ifdef NON_BROKEN_OPCODES
581 {"fsub", 2, 0xdce8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
583 {"fsub", 2, 0xdce0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
585 {"fsub", 0, 0xdce1, _
, NoModrm
, { 0, 0, 0} },
586 {"fsubp", 1, 0xdee8, _
, ShortForm
, { FloatReg
, 0, 0} },
587 {"fsubp", 2, 0xdee8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
588 #ifdef NON_BROKEN_OPCODES
589 {"fsubp", 2, 0xdee8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
590 {"fsubp", 0, 0xdee9, _
, NoModrm
, { 0, 0, 0} },
592 {"fsubp", 2, 0xdee0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
593 {"fsubp", 0, 0xdee1, _
, NoModrm
, { 0, 0, 0} },
595 {"fsubs", 1, 0xd8, 4, Modrm
, { Mem
, 0, 0} },
596 {"fisubl", 1, 0xda, 4, Modrm
, { Mem
, 0, 0} },
597 {"fsubl", 1, 0xdc, 4, Modrm
, { Mem
, 0, 0} },
598 {"fisubs", 1, 0xde, 4, Modrm
, { Mem
, 0, 0} },
601 {"fsubr", 1, 0xd8e8, _
, ShortForm
, { FloatReg
, 0, 0} },
602 {"fsubr", 2, 0xd8e8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
603 #ifdef NON_BROKEN_OPCODES
604 {"fsubr", 2, 0xdce0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
606 {"fsubr", 2, 0xdce8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
608 {"fsubr", 0, 0xdce9, _
, NoModrm
, { 0, 0, 0} },
609 {"fsubrp", 1, 0xdee0, _
, ShortForm
, { FloatReg
, 0, 0} },
610 {"fsubrp", 2, 0xdee0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
611 #ifdef NON_BROKEN_OPCODES
612 {"fsubrp", 2, 0xdee0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
613 {"fsubrp", 0, 0xdee1, _
, NoModrm
, { 0, 0, 0} },
615 {"fsubrp", 2, 0xdee8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
616 {"fsubrp", 0, 0xdee9, _
, NoModrm
, { 0, 0, 0} },
618 {"fsubrs", 1, 0xd8, 5, Modrm
, { Mem
, 0, 0} },
619 {"fisubrl", 1, 0xda, 5, Modrm
, { Mem
, 0, 0} },
620 {"fsubrl", 1, 0xdc, 5, Modrm
, { Mem
, 0, 0} },
621 {"fisubrs", 1, 0xde, 5, Modrm
, { Mem
, 0, 0} },
624 {"fmul", 1, 0xd8c8, _
, ShortForm
, { FloatReg
, 0, 0} },
625 {"fmul", 2, 0xd8c8, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
626 {"fmul", 0, 0xdcc9, _
, NoModrm
, { 0, 0, 0} },
627 {"fmulp", 1, 0xdec8, _
, ShortForm
, { FloatReg
, 0, 0} },
628 {"fmulp", 2, 0xdec8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
629 {"fmulp", 2, 0xdec8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
630 {"fmulp", 0, 0xdec9, _
, NoModrm
, { 0, 0, 0} },
631 {"fmuls", 1, 0xd8, 1, Modrm
, { Mem
, 0, 0} },
632 {"fimull", 1, 0xda, 1, Modrm
, { Mem
, 0, 0} },
633 {"fmull", 1, 0xdc, 1, Modrm
, { Mem
, 0, 0} },
634 {"fimuls", 1, 0xde, 1, Modrm
, { Mem
, 0, 0} },
637 /* Note: intel has decided that certain of these operations are reversed
638 in assembler syntax. */
639 {"fdiv", 1, 0xd8f0, _
, ShortForm
, { FloatReg
, 0, 0} },
640 {"fdiv", 2, 0xd8f0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
641 #ifdef NON_BROKEN_OPCODES
642 {"fdiv", 2, 0xdcf8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
644 {"fdiv", 2, 0xdcf0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
646 {"fdiv", 0, 0xdcf1, _
, NoModrm
, { 0, 0, 0} },
647 {"fdivp", 1, 0xdef8, _
, ShortForm
, { FloatReg
, 0, 0} },
648 {"fdivp", 2, 0xdef8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
649 #ifdef NON_BROKEN_OPCODES
650 {"fdivp", 2, 0xdef8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
651 {"fdivp", 0, 0xdef9, _
, NoModrm
, { 0, 0, 0} },
653 {"fdivp", 2, 0xdef0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
654 {"fdivp", 0, 0xdef1, _
, NoModrm
, { 0, 0, 0} },
656 {"fdivs", 1, 0xd8, 6, Modrm
, { Mem
, 0, 0} },
657 {"fidivl", 1, 0xda, 6, Modrm
, { Mem
, 0, 0} },
658 {"fdivl", 1, 0xdc, 6, Modrm
, { Mem
, 0, 0} },
659 {"fidivs", 1, 0xde, 6, Modrm
, { Mem
, 0, 0} },
662 {"fdivr", 1, 0xd8f8, _
, ShortForm
, { FloatReg
, 0, 0} },
663 {"fdivr", 2, 0xd8f8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
664 #ifdef NON_BROKEN_OPCODES
665 {"fdivr", 2, 0xdcf0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
667 {"fdivr", 2, 0xdcf8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
669 {"fdivr", 0, 0xdcf9, _
, NoModrm
, { 0, 0, 0} },
670 {"fdivrp", 1, 0xdef0, _
, ShortForm
, { FloatReg
, 0, 0} },
671 {"fdivrp", 2, 0xdef0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
672 #ifdef NON_BROKEN_OPCODES
673 {"fdivrp", 2, 0xdef0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
674 {"fdivrp", 0, 0xdef1, _
, NoModrm
, { 0, 0, 0} },
676 {"fdivrp", 2, 0xdef8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
677 {"fdivrp", 0, 0xdef9, _
, NoModrm
, { 0, 0, 0} },
679 {"fdivrs", 1, 0xd8, 7, Modrm
, { Mem
, 0, 0} },
680 {"fidivrl", 1, 0xda, 7, Modrm
, { Mem
, 0, 0} },
681 {"fdivrl", 1, 0xdc, 7, Modrm
, { Mem
, 0, 0} },
682 {"fidivrs", 1, 0xde, 7, Modrm
, { Mem
, 0, 0} },
684 {"f2xm1", 0, 0xd9f0, _
, NoModrm
, { 0, 0, 0} },
685 {"fyl2x", 0, 0xd9f1, _
, NoModrm
, { 0, 0, 0} },
686 {"fptan", 0, 0xd9f2, _
, NoModrm
, { 0, 0, 0} },
687 {"fpatan", 0, 0xd9f3, _
, NoModrm
, { 0, 0, 0} },
688 {"fxtract", 0, 0xd9f4, _
, NoModrm
, { 0, 0, 0} },
689 {"fprem1", 0, 0xd9f5, _
, NoModrm
, { 0, 0, 0} },
690 {"fdecstp", 0, 0xd9f6, _
, NoModrm
, { 0, 0, 0} },
691 {"fincstp", 0, 0xd9f7, _
, NoModrm
, { 0, 0, 0} },
692 {"fprem", 0, 0xd9f8, _
, NoModrm
, { 0, 0, 0} },
693 {"fyl2xp1", 0, 0xd9f9, _
, NoModrm
, { 0, 0, 0} },
694 {"fsqrt", 0, 0xd9fa, _
, NoModrm
, { 0, 0, 0} },
695 {"fsincos", 0, 0xd9fb, _
, NoModrm
, { 0, 0, 0} },
696 {"frndint", 0, 0xd9fc, _
, NoModrm
, { 0, 0, 0} },
697 {"fscale", 0, 0xd9fd, _
, NoModrm
, { 0, 0, 0} },
698 {"fsin", 0, 0xd9fe, _
, NoModrm
, { 0, 0, 0} },
699 {"fcos", 0, 0xd9ff, _
, NoModrm
, { 0, 0, 0} },
701 {"fchs", 0, 0xd9e0, _
, NoModrm
, { 0, 0, 0} },
702 {"fabs", 0, 0xd9e1, _
, NoModrm
, { 0, 0, 0} },
704 /* processor control */
705 {"fninit", 0, 0xdbe3, _
, NoModrm
, { 0, 0, 0} },
706 {"finit", 0, 0x9bdbe3, _
, NoModrm
, { 0, 0, 0} },
707 {"fldcw", 1, 0xd9, 5, Modrm
, { Mem
, 0, 0} },
708 {"fnstcw", 1, 0xd9, 7, Modrm
, { Mem
, 0, 0} },
709 {"fstcw", 1, 0x9bd9, 7, Modrm
, { Mem
, 0, 0} },
710 {"fnstsw", 1, 0xdfe0, _
, NoModrm
, { Acc
, 0, 0} },
711 {"fnstsw", 1, 0xdd, 7, Modrm
, { Mem
, 0, 0} },
712 {"fnstsw", 0, 0xdfe0, _
, NoModrm
, { 0, 0, 0} },
713 {"fstsw", 1, 0x9bdfe0, _
, NoModrm
, { Acc
, 0, 0} },
714 {"fstsw", 1, 0x9bdd, 7, Modrm
, { Mem
, 0, 0} },
715 {"fstsw", 0, 0x9bdfe0, _
, NoModrm
, { 0, 0, 0} },
716 {"fnclex", 0, 0xdbe2, _
, NoModrm
, { 0, 0, 0} },
717 {"fclex", 0, 0x9bdbe2, _
, NoModrm
, { 0, 0, 0} },
719 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
720 instructions; i'm not sure how to add them or how they are different.
721 My 386/387 book offers no details about this.
723 {"fnstenv", 1, 0xd9, 6, Modrm
, { Mem
, 0, 0} },
724 {"fstenv", 1, 0x9bd9, 6, Modrm
, { Mem
, 0, 0} },
725 {"fldenv", 1, 0xd9, 4, Modrm
, { Mem
, 0, 0} },
726 {"fnsave", 1, 0xdd, 6, Modrm
, { Mem
, 0, 0} },
727 {"fsave", 1, 0x9bdd, 6, Modrm
, { Mem
, 0, 0} },
728 {"frstor", 1, 0xdd, 4, Modrm
, { Mem
, 0, 0} },
730 {"ffree", 1, 0xddc0, _
, ShortForm
, { FloatReg
, 0, 0} },
731 /* P6:free st(i), pop st */
732 {"ffreep", 1, 0xdfc0, _
, ShortForm
, { FloatReg
, 0, 0} },
733 {"fnop", 0, 0xd9d0, _
, NoModrm
, { 0, 0, 0} },
734 {"fwait", 0, 0x9b, _
, NoModrm
, { 0, 0, 0} },
737 opcode prefixes; we allow them as seperate insns too
738 (see prefix table below)
740 {"aword", 0, 0x67, _
, NoModrm
, { 0, 0, 0} },
741 {"addr16", 0, 0x67, _
, NoModrm
, { 0, 0, 0} },
742 {"word", 0, 0x66, _
, NoModrm
, { 0, 0, 0} },
743 {"data16", 0, 0x66, _
, NoModrm
, { 0, 0, 0} },
744 {"lock", 0, 0xf0, _
, NoModrm
, { 0, 0, 0} },
745 {"cs", 0, 0x2e, _
, NoModrm
, { 0, 0, 0} },
746 {"ds", 0, 0x3e, _
, NoModrm
, { 0, 0, 0} },
747 {"es", 0, 0x26, _
, NoModrm
, { 0, 0, 0} },
748 {"fs", 0, 0x64, _
, NoModrm
, { 0, 0, 0} },
749 {"gs", 0, 0x65, _
, NoModrm
, { 0, 0, 0} },
750 {"ss", 0, 0x36, _
, NoModrm
, { 0, 0, 0} },
751 {"rep", 0, 0xf3, _
, NoModrm
, { 0, 0, 0} },
752 {"repe", 0, 0xf3, _
, NoModrm
, { 0, 0, 0} },
753 {"repz", 0, 0xf3, _
, NoModrm
, { 0, 0, 0} },
754 {"repne", 0, 0xf2, _
, NoModrm
, { 0, 0, 0} },
755 {"repnz", 0, 0xf2, _
, NoModrm
, { 0, 0, 0} },
759 {"bswap", 1, 0x0fc8, _
, ShortForm
, { Reg32
,0,0 } },
760 {"xadd", 2, 0x0fc0, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
761 {"cmpxchg", 2, 0x0fb0, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
762 {"invd", 0, 0x0f08, _
, NoModrm
, { 0, 0, 0} },
763 {"wbinvd", 0, 0x0f09, _
, NoModrm
, { 0, 0, 0} },
764 {"invlpg", 1, 0x0f01, 7, Modrm
, { Mem
, 0, 0} },
766 /* 586 and late 486 extensions */
767 {"cpuid", 0, 0x0fa2, _
, NoModrm
, { 0, 0, 0} },
769 /* Pentium extensions */
770 {"wrmsr", 0, 0x0f30, _
, NoModrm
, { 0, 0, 0} },
771 {"rdtsc", 0, 0x0f31, _
, NoModrm
, { 0, 0, 0} },
772 {"rdmsr", 0, 0x0f32, _
, NoModrm
, { 0, 0, 0} },
773 {"cmpxchg8b", 1, 0x0fc7, 1, Modrm
, { Mem
, 0, 0} },
775 /* Pentium Pro extensions */
776 {"rdpmc", 0, 0x0f33, _
, NoModrm
, { 0, 0, 0} },
778 {"ud2", 0, 0x0f0b, _
, NoModrm
, {0, 0, 0} }, /* official undefined instr. */
780 {"cmovo", 2, 0x0f40, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
781 {"cmovno", 2, 0x0f41, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
782 {"cmovb", 2, 0x0f42, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
783 {"cmovae", 2, 0x0f43, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
784 {"cmove", 2, 0x0f44, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
785 {"cmovne", 2, 0x0f45, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
786 {"cmovbe", 2, 0x0f46, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
787 {"cmova", 2, 0x0f47, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
788 {"cmovs", 2, 0x0f48, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
789 {"cmovns", 2, 0x0f49, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
790 {"cmovp", 2, 0x0f4a, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
791 {"cmovnp", 2, 0x0f4b, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
792 {"cmovl", 2, 0x0f4c, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
793 {"cmovge", 2, 0x0f4d, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
794 {"cmovle", 2, 0x0f4e, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
795 {"cmovg", 2, 0x0f4f, _
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
797 {"fcmovb", 2, 0xdac0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
798 {"fcmove", 2, 0xdac8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
799 {"fcmovbe",2, 0xdad0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
800 {"fcmovu", 2, 0xdad8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
801 {"fcmovnb", 2, 0xdbc0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
802 {"fcmovne", 2, 0xdbc8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
803 {"fcmovnbe",2, 0xdbd0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
804 {"fcmovnu", 2, 0xdbd8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
806 {"fcomi", 2, 0xdbf0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
807 {"fucomi", 2, 0xdbe8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
808 {"fcomip", 2, 0xdff0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
809 {"fucomip",2, 0xdfe8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
811 /* MMX instructions. */
813 {"emms", 0, 0x0f77, _
, NoModrm
, { 0, 0, 0 } },
814 {"movd", 2, 0x0f6e, _
, Modrm
, { Reg32
|WordMem
, RegMMX
, 0 } },
815 {"movd", 2, 0x0f7e, _
, Modrm
, { RegMMX
, Reg32
|WordMem
, 0 } },
816 {"movq", 2, 0x0f6f, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
817 {"movq", 2, 0x0f7f, _
, Modrm
, { RegMMX
, RegMMX
|WordMem
, 0 } },
818 {"packssdw", 2, 0x0f6b, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
819 {"packsswb", 2, 0x0f63, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
820 {"packuswb", 2, 0x0f67, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
821 {"paddb", 2, 0x0ffc, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
822 {"paddw", 2, 0x0ffd, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
823 {"paddd", 2, 0x0ffe, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
824 {"paddsb", 2, 0x0fec, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
825 {"paddsw", 2, 0x0fed, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
826 {"paddusb", 2, 0x0fdc, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
827 {"paddusw", 2, 0x0fdd, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
828 {"pand", 2, 0x0fdb, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
829 {"pandn", 2, 0x0fdf, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
830 {"pcmpeqb", 2, 0x0f74, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
831 {"pcmpeqw", 2, 0x0f75, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
832 {"pcmpeqd", 2, 0x0f76, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
833 {"pcmpgtb", 2, 0x0f64, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
834 {"pcmpgtw", 2, 0x0f65, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
835 {"pcmpgtd", 2, 0x0f66, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
836 {"pmaddwd", 2, 0x0ff5, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
837 {"pmulhw", 2, 0x0fe5, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
838 {"pmullw", 2, 0x0fd5, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
839 {"por", 2, 0x0feb, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
840 {"psllw", 2, 0x0ff1, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
841 {"psllw", 2, 0x0f71, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
842 {"pslld", 2, 0x0ff2, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
843 {"pslld", 2, 0x0f72, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
844 {"psllq", 2, 0x0ff3, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
845 {"psllq", 2, 0x0f73, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
846 {"psraw", 2, 0x0fe1, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
847 {"psraw", 2, 0x0f71, 4, Modrm
, { Imm8
, RegMMX
, 0 } },
848 {"psrad", 2, 0x0fe2, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
849 {"psrad", 2, 0x0f72, 4, Modrm
, { Imm8
, RegMMX
, 0 } },
850 {"psrlw", 2, 0x0fd1, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
851 {"psrlw", 2, 0x0f71, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
852 {"psrld", 2, 0x0fd2, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
853 {"psrld", 2, 0x0f72, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
854 {"psrlq", 2, 0x0fd3, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
855 {"psrlq", 2, 0x0f73, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
856 {"psubb", 2, 0x0ff8, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
857 {"psubw", 2, 0x0ff9, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
858 {"psubd", 2, 0x0ffa, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
859 {"psubsb", 2, 0x0fe8, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
860 {"psubsw", 2, 0x0fe9, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
861 {"psubusb", 2, 0x0fd8, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
862 {"psubusw", 2, 0x0fd9, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
863 {"punpckhbw", 2, 0x0f68, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
864 {"punpckhwd", 2, 0x0f69, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
865 {"punpckhdq", 2, 0x0f6a, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
866 {"punpcklbw", 2, 0x0f60, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
867 {"punpcklwd", 2, 0x0f61, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
868 {"punpckldq", 2, 0x0f62, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
869 {"pxor", 2, 0x0fef, _
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
871 {"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
875 static const template *const i386_optab_end
876 = i386_optab
+ sizeof (i386_optab
)/sizeof(i386_optab
[0]);
878 /* 386 register table */
880 static const reg_entry i386_regtab
[] = {
882 {"al", Reg8
|Acc
, 0}, {"cl", Reg8
|ShiftCount
, 1}, {"dl", Reg8
, 2},
884 {"ah", Reg8
, 4}, {"ch", Reg8
, 5}, {"dh", Reg8
, 6}, {"bh", Reg8
, 7},
886 {"ax", Reg16
|Acc
, 0}, {"cx", Reg16
, 1}, {"dx", Reg16
|InOutPortReg
, 2}, {"bx", Reg16
, 3},
887 {"sp", Reg16
, 4}, {"bp", Reg16
, 5}, {"si", Reg16
, 6}, {"di", Reg16
, 7},
889 {"eax", Reg32
|Acc
, 0}, {"ecx", Reg32
, 1}, {"edx", Reg32
, 2}, {"ebx", Reg32
, 3},
890 {"esp", Reg32
, 4}, {"ebp", Reg32
, 5}, {"esi", Reg32
, 6}, {"edi", Reg32
, 7},
891 /* segment registers */
892 {"es", SReg2
, 0}, {"cs", SReg2
, 1}, {"ss", SReg2
, 2},
893 {"ds", SReg2
, 3}, {"fs", SReg3
, 4}, {"gs", SReg3
, 5},
894 /* control registers */
895 {"cr0", Control
, 0}, {"cr2", Control
, 2}, {"cr3", Control
, 3},
897 /* debug registers */
898 {"db0", Debug
, 0}, {"db1", Debug
, 1}, {"db2", Debug
, 2},
899 {"db3", Debug
, 3}, {"db6", Debug
, 6}, {"db7", Debug
, 7},
900 {"dr0", Debug
, 0}, {"dr1", Debug
, 1}, {"dr2", Debug
, 2},
901 {"dr3", Debug
, 3}, {"dr6", Debug
, 6}, {"dr7", Debug
, 7},
903 {"tr3", Test
, 3}, {"tr4", Test
, 4}, {"tr5", Test
, 5},
904 {"tr6", Test
, 6}, {"tr7", Test
, 7},
905 /* float registers */
906 {"st(0)", FloatReg
|FloatAcc
, 0},
907 {"st", FloatReg
|FloatAcc
, 0},
908 {"st(1)", FloatReg
, 1}, {"st(2)", FloatReg
, 2},
909 {"st(3)", FloatReg
, 3}, {"st(4)", FloatReg
, 4}, {"st(5)", FloatReg
, 5},
910 {"st(6)", FloatReg
, 6}, {"st(7)", FloatReg
, 7},
911 {"mm0", RegMMX
, 0}, {"mm1", RegMMX
, 1}, {"mm2", RegMMX
, 2},
912 {"mm3", RegMMX
, 3}, {"mm4", RegMMX
, 4}, {"mm5", RegMMX
, 5},
913 {"mm6", RegMMX
, 6}, {"mm7", RegMMX
, 7}
916 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
918 static const reg_entry
*const i386_regtab_end
919 = i386_regtab
+ sizeof(i386_regtab
)/sizeof(i386_regtab
[0]);
922 static const seg_entry cs
= { "cs", 0x2e };
923 static const seg_entry ds
= { "ds", 0x3e };
924 static const seg_entry ss
= { "ss", 0x36 };
925 static const seg_entry es
= { "es", 0x26 };
926 static const seg_entry fs
= { "fs", 0x64 };
927 static const seg_entry gs
= { "gs", 0x65 };
928 static const seg_entry null
= { "", 0x0 };
931 This table is used to store the default segment register implied by all
932 possible memory addressing modes.
933 It is indexed by the mode & modrm entries of the modrm byte as follows:
934 index = (mode<<3) | modrm;
936 static const seg_entry
*const one_byte_segment_defaults
[] = {
938 &ds
, &ds
, &ds
, &ds
, &null
, &ds
, &ds
, &ds
,
940 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
942 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
943 /* mode 3 --- not a memory reference; never referenced */
946 static const seg_entry
*const two_byte_segment_defaults
[] = {
948 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
950 &ds
, &ds
, &ds
, &ds
, &ss
, &ss
, &ds
, &ds
,
952 &ds
, &ds
, &ds
, &ds
, &ss
, &ss
, &ds
, &ds
,
953 /* mode 3 --- not a memory reference; never referenced */
956 static const prefix_entry i386_prefixtab
[] = {
957 #define ADDR_PREFIX_OPCODE 0x67
958 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
959 * (How is this useful?) */
960 #define WORD_PREFIX_OPCODE 0x66
961 { "data16", 0x66 }, /* operand size prefix */
962 { "lock", 0xf0 }, /* bus lock prefix */
963 { "wait", 0x9b }, /* wait for coprocessor */
964 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
965 { "es", 0x26 }, { "fs", 0x64 },
966 { "gs", 0x65 }, { "ss", 0x36 },
967 /* REPE & REPNE used to detect rep/repne with a non-string instruction */
970 { "rep", 0xf3 }, /* repeat string instructions */
971 { "repe", 0xf3 }, { "repz", 0xf3 },
972 { "repne", 0xf2 }, { "repnz", 0xf2 }
975 static const prefix_entry
*const i386_prefixtab_end
976 = i386_prefixtab
+ sizeof(i386_prefixtab
)/sizeof(i386_prefixtab
[0]);
978 /* end of i386-opcode.h */