1 /* i386-opcode.h -- Intel 80386 opcode table
2 Copyright 1989, 1991, 1992 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 static const template i386_optab
[] = {
23 /* move instructions */
24 #define MOV_AX_DISP32 0xa0
25 { "mov", 2, 0xa0, _
, DW
|NoModrm
, { Disp32
, Acc
, 0 } },
26 { "mov", 2, 0x88, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
27 { "mov", 2, 0xb0, _
, ShortFormW
, { Imm
, Reg
, 0 } },
28 { "mov", 2, 0xc6, _
, W
|Modrm
, { Imm
, Reg
|Mem
, 0 } },
29 { "mov", 2, 0x8c, _
, D
|Modrm
, { SReg3
|SReg2
, Reg16
|Mem
, 0 } },
30 /* move to/from control debug registers */
31 { "mov", 2, 0x0f20, _
, D
|Modrm
, { Control
, Reg32
, 0} },
32 { "mov", 2, 0x0f21, _
, D
|Modrm
, { Debug
, Reg32
, 0} },
33 { "mov", 2, 0x0f24, _
, D
|Modrm
, { Test
, Reg32
, 0} },
35 /* move with sign extend */
36 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
37 conflict with the "movs" string move instruction. Thus,
38 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
39 is not kosher; we must seperate the two instructions. */
40 {"movsbl", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
|Data32
, { Reg8
|Mem
, Reg32
, 0} },
41 {"movsbw", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
|Data16
, { Reg8
|Mem
, Reg16
, 0} },
42 {"movswl", 2, 0x0fbf, _
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
44 /* move with zero extend */
45 {"movzb", 2, 0x0fb6, _
, ReverseRegRegmem
|Modrm
, { Reg8
|Mem
, Reg16
|Reg32
, 0} },
46 {"movzwl", 2, 0x0fb7, _
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
48 /* push instructions */
49 {"push", 1, 0x50, _
, ShortForm
, { WordReg
,0,0 } },
50 {"push", 1, 0xff, 0x6, Modrm
, { WordReg
|WordMem
, 0, 0 } },
51 {"push", 1, 0x6a, _
, NoModrm
, { Imm8S
, 0, 0} },
52 {"push", 1, 0x68, _
, NoModrm
, { Imm16
|Imm32
, 0, 0} },
53 {"push", 1, 0x06, _
, Seg2ShortForm
, { SReg2
,0,0 } },
54 {"push", 1, 0x0fa0, _
, Seg3ShortForm
, { SReg3
,0,0 } },
56 {"pusha", 0, 0x60, _
, NoModrm
, { 0, 0, 0 } },
58 /* pop instructions */
59 {"pop", 1, 0x58, _
, ShortForm
, { WordReg
,0,0 } },
60 {"pop", 1, 0x8f, 0x0, Modrm
, { WordReg
|WordMem
, 0, 0 } },
61 #define POP_SEG_SHORT 0x7
62 {"pop", 1, 0x07, _
, Seg2ShortForm
, { SReg2
,0,0 } },
63 {"pop", 1, 0x0fa1, _
, Seg3ShortForm
, { SReg3
,0,0 } },
65 {"popa", 0, 0x61, _
, NoModrm
, { 0, 0, 0 } },
67 /* xchg exchange instructions
68 xchg commutes: we allow both operand orders */
69 {"xchg", 2, 0x90, _
, ShortForm
, { WordReg
, Acc
, 0 } },
70 {"xchg", 2, 0x90, _
, ShortForm
, { Acc
, WordReg
, 0 } },
71 {"xchg", 2, 0x86, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
72 {"xchg", 2, 0x86, _
, W
|Modrm
, { Reg
|Mem
, Reg
, 0 } },
74 /* in/out from ports */
75 {"in", 2, 0xe4, _
, W
|NoModrm
, { Imm8
, Acc
, 0 } },
76 {"in", 2, 0xec, _
, W
|NoModrm
, { InOutPortReg
, Acc
, 0 } },
77 {"in", 1, 0xe4, _
, W
|NoModrm
, { Imm8
, 0, 0 } },
78 {"in", 1, 0xec, _
, W
|NoModrm
, { InOutPortReg
, 0, 0 } },
79 {"out", 2, 0xe6, _
, W
|NoModrm
, { Acc
, Imm8
, 0 } },
80 {"out", 2, 0xee, _
, W
|NoModrm
, { Acc
, InOutPortReg
, 0 } },
81 {"out", 1, 0xe6, _
, W
|NoModrm
, { Imm8
, 0, 0 } },
82 {"out", 1, 0xee, _
, W
|NoModrm
, { InOutPortReg
, 0, 0 } },
84 /* load effective address */
85 {"lea", 2, 0x8d, _
, Modrm
, { WordMem
, WordReg
, 0 } },
87 /* load segment registers from memory */
88 {"lds", 2, 0xc5, _
, Modrm
, { Mem
, Reg32
, 0} },
89 {"les", 2, 0xc4, _
, Modrm
, { Mem
, Reg32
, 0} },
90 {"lfs", 2, 0x0fb4, _
, Modrm
, { Mem
, Reg32
, 0} },
91 {"lgs", 2, 0x0fb5, _
, Modrm
, { Mem
, Reg32
, 0} },
92 {"lss", 2, 0x0fb2, _
, Modrm
, { Mem
, Reg32
, 0} },
94 /* flags register instructions */
95 {"clc", 0, 0xf8, _
, NoModrm
, { 0, 0, 0} },
96 {"cld", 0, 0xfc, _
, NoModrm
, { 0, 0, 0} },
97 {"cli", 0, 0xfa, _
, NoModrm
, { 0, 0, 0} },
98 {"clts", 0, 0x0f06, _
, NoModrm
, { 0, 0, 0} },
99 {"cmc", 0, 0xf5, _
, NoModrm
, { 0, 0, 0} },
100 {"lahf", 0, 0x9f, _
, NoModrm
, { 0, 0, 0} },
101 {"sahf", 0, 0x9e, _
, NoModrm
, { 0, 0, 0} },
102 {"pushf", 0, 0x9c, _
, NoModrm
|Data32
, { 0, 0, 0} },
103 {"popf", 0, 0x9d, _
, NoModrm
|Data32
, { 0, 0, 0} },
104 {"pushfw", 0, 0x9c, _
, NoModrm
|Data16
, { 0, 0, 0} },
105 {"popfw", 0, 0x9d, _
, NoModrm
|Data16
, { 0, 0, 0} },
106 {"stc", 0, 0xf9, _
, NoModrm
, { 0, 0, 0} },
107 {"std", 0, 0xfd, _
, NoModrm
, { 0, 0, 0} },
108 {"sti", 0, 0xfb, _
, NoModrm
, { 0, 0, 0} },
110 {"add", 2, 0x0, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
111 {"add", 2, 0x83, 0, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
112 {"add", 2, 0x4, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
113 {"add", 2, 0x80, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
115 {"inc", 1, 0x40, _
, ShortForm
, { WordReg
, 0, 0} },
116 {"inc", 1, 0xfe, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
118 {"sub", 2, 0x28, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
119 {"sub", 2, 0x83, 5, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
120 {"sub", 2, 0x2c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
121 {"sub", 2, 0x80, 5, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
123 {"dec", 1, 0x48, _
, ShortForm
, { WordReg
, 0, 0} },
124 {"dec", 1, 0xfe, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
126 {"sbb", 2, 0x18, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
127 {"sbb", 2, 0x83, 3, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
128 {"sbb", 2, 0x1c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
129 {"sbb", 2, 0x80, 3, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
131 {"cmp", 2, 0x38, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
132 {"cmp", 2, 0x83, 7, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
133 {"cmp", 2, 0x3c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
134 {"cmp", 2, 0x80, 7, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
136 {"test", 2, 0x84, _
, W
|Modrm
, { Reg
|Mem
, Reg
, 0} },
137 {"test", 2, 0x84, _
, W
|Modrm
, { Reg
, Reg
|Mem
, 0} },
138 {"test", 2, 0xa8, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
139 {"test", 2, 0xf6, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
141 {"and", 2, 0x20, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
142 {"and", 2, 0x83, 4, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
143 {"and", 2, 0x24, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
144 {"and", 2, 0x80, 4, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
146 {"or", 2, 0x08, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
147 {"or", 2, 0x83, 1, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
148 {"or", 2, 0x0c, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
149 {"or", 2, 0x80, 1, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
151 {"xor", 2, 0x30, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
152 {"xor", 2, 0x83, 6, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
153 {"xor", 2, 0x34, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
154 {"xor", 2, 0x80, 6, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
156 {"adc", 2, 0x10, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
157 {"adc", 2, 0x83, 2, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
158 {"adc", 2, 0x14, _
, W
|NoModrm
, { Imm
, Acc
, 0} },
159 {"adc", 2, 0x80, 2, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
161 {"neg", 1, 0xf6, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
162 {"not", 1, 0xf6, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
164 {"aaa", 0, 0x37, _
, NoModrm
, { 0, 0, 0} },
165 {"aas", 0, 0x3f, _
, NoModrm
, { 0, 0, 0} },
166 {"daa", 0, 0x27, _
, NoModrm
, { 0, 0, 0} },
167 {"das", 0, 0x2f, _
, NoModrm
, { 0, 0, 0} },
168 {"aad", 0, 0xd50a, _
, NoModrm
, { 0, 0, 0} },
169 {"aam", 0, 0xd40a, _
, NoModrm
, { 0, 0, 0} },
171 /* conversion insns */
172 /* conversion: intel naming */
173 {"cbw", 0, 0x98, _
, NoModrm
|Data16
, { 0, 0, 0} },
174 {"cwd", 0, 0x99, _
, NoModrm
|Data16
, { 0, 0, 0} },
175 {"cwde", 0, 0x98, _
, NoModrm
|Data32
, { 0, 0, 0} },
176 {"cdq", 0, 0x99, _
, NoModrm
|Data32
, { 0, 0, 0} },
178 {"cbtw", 0, 0x98, _
, NoModrm
|Data16
, { 0, 0, 0} },
179 {"cwtl", 0, 0x98, _
, NoModrm
|Data32
, { 0, 0, 0} },
180 {"cwtd", 0, 0x99, _
, NoModrm
|Data16
, { 0, 0, 0} },
181 {"cltd", 0, 0x99, _
, NoModrm
|Data32
, { 0, 0, 0} },
183 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
184 expanding 64-bit multiplies, and *cannot* be selected to accomplish
185 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
186 These multiplies can only be selected with single operand forms. */
187 {"mul", 1, 0xf6, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
188 {"imul", 1, 0xf6, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
193 /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
194 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
195 '%eax' in the reg field and '%ecx' in the regmem field if we did not
197 {"imul", 2, 0x0faf, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
198 {"imul", 3, 0x6b, _
, Modrm
|ReverseRegRegmem
, { Imm8S
, WordReg
|Mem
, WordReg
} },
199 {"imul", 3, 0x69, _
, Modrm
|ReverseRegRegmem
, { Imm16
|Imm32
, WordReg
|Mem
, WordReg
} },
201 imul with 2 operands mimicks imul with 3 by puting register both
202 in i.rm.reg & i.rm.regmem fields
204 {"imul", 2, 0x6b, _
, Modrm
|imulKludge
, { Imm8S
, WordReg
, 0} },
205 {"imul", 2, 0x69, _
, Modrm
|imulKludge
, { Imm16
|Imm32
, WordReg
, 0} },
206 {"div", 1, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, 0, 0} },
207 {"div", 2, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
208 {"idiv", 1, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
209 {"idiv", 2, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
211 {"rol", 2, 0xd0, 0, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
212 {"rol", 2, 0xc0, 0, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
213 {"rol", 2, 0xd2, 0, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
214 {"rol", 1, 0xd0, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
216 {"ror", 2, 0xd0, 1, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
217 {"ror", 2, 0xc0, 1, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
218 {"ror", 2, 0xd2, 1, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
219 {"ror", 1, 0xd0, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
221 {"rcl", 2, 0xd0, 2, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
222 {"rcl", 2, 0xc0, 2, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
223 {"rcl", 2, 0xd2, 2, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
224 {"rcl", 1, 0xd0, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
226 {"rcr", 2, 0xd0, 3, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
227 {"rcr", 2, 0xc0, 3, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
228 {"rcr", 2, 0xd2, 3, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
229 {"rcr", 1, 0xd0, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
231 {"sal", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
232 {"sal", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
233 {"sal", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
234 {"sal", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
235 {"shl", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
236 {"shl", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
237 {"shl", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
238 {"shl", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
240 {"shld", 3, 0x0fa4, _
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
241 {"shld", 3, 0x0fa5, _
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
242 {"shld", 2, 0x0fa5, _
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
244 {"shr", 2, 0xd0, 5, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
245 {"shr", 2, 0xc0, 5, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
246 {"shr", 2, 0xd2, 5, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
247 {"shr", 1, 0xd0, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
249 {"shrd", 3, 0x0fac, _
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
250 {"shrd", 3, 0x0fad, _
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
251 {"shrd", 2, 0x0fad, _
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
253 {"sar", 2, 0xd0, 7, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
254 {"sar", 2, 0xc0, 7, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
255 {"sar", 2, 0xd2, 7, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
256 {"sar", 1, 0xd0, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
258 /* control transfer instructions */
259 #define CALL_PC_RELATIVE 0xe8
260 {"call", 1, 0xe8, _
, JumpDword
, { Disp32
, 0, 0} },
261 {"call", 1, 0xff, 2, Modrm
|Data32
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
262 {"callw", 1, 0xff, 2, Modrm
|Data16
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
263 #define CALL_FAR_IMMEDIATE 0x9a
264 {"lcall", 2, 0x9a, _
, JumpInterSegment
, { Imm16
, Abs32
|Imm32
, 0} },
265 {"lcall", 1, 0xff, 3, Modrm
|Data32
, { Mem
, 0, 0} },
266 {"lcallw", 1, 0xff, 3, Modrm
|Data16
, { Mem
, 0, 0} },
268 #define JUMP_PC_RELATIVE 0xeb
269 {"jmp", 1, 0xeb, _
, Jump
, { Disp
, 0, 0} },
270 {"jmp", 1, 0xff, 4, Modrm
, { Reg32
|Mem
|JumpAbsolute
, 0, 0} },
271 #define JUMP_FAR_IMMEDIATE 0xea
272 {"ljmp", 2, 0xea, _
, JumpInterSegment
, { Imm16
, Imm32
, 0} },
273 {"ljmp", 1, 0xff, 5, Modrm
|Data32
, { Mem
, 0, 0} },
275 {"ret", 0, 0xc3, _
, NoModrm
|Data32
, { 0, 0, 0} },
276 {"ret", 1, 0xc2, _
, NoModrm
|Data32
, { Imm16
, 0, 0} },
277 {"retw", 0, 0xc3, _
, NoModrm
|Data16
, { 0, 0, 0} },
278 {"retw", 1, 0xc2, _
, NoModrm
|Data16
, { Imm16
, 0, 0} },
279 {"lret", 0, 0xcb, _
, NoModrm
|Data32
, { 0, 0, 0} },
280 {"lret", 1, 0xca, _
, NoModrm
|Data32
, { Imm16
, 0, 0} },
281 {"lretw", 0, 0xcb, _
, NoModrm
|Data16
, { 0, 0, 0} },
282 {"lretw", 1, 0xca, _
, NoModrm
|Data16
, { Imm16
, 0, 0} },
283 {"enter", 2, 0xc8, _
, NoModrm
, { Imm16
, Imm8
, 0} },
284 {"leave", 0, 0xc9, _
, NoModrm
, { 0, 0, 0} },
286 /* conditional jumps */
287 {"jo", 1, 0x70, _
, Jump
, { Disp
, 0, 0} },
289 {"jno", 1, 0x71, _
, Jump
, { Disp
, 0, 0} },
291 {"jb", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
292 {"jc", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
293 {"jnae", 1, 0x72, _
, Jump
, { Disp
, 0, 0} },
295 {"jnb", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
296 {"jnc", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
297 {"jae", 1, 0x73, _
, Jump
, { Disp
, 0, 0} },
299 {"je", 1, 0x74, _
, Jump
, { Disp
, 0, 0} },
300 {"jz", 1, 0x74, _
, Jump
, { Disp
, 0, 0} },
302 {"jne", 1, 0x75, _
, Jump
, { Disp
, 0, 0} },
303 {"jnz", 1, 0x75, _
, Jump
, { Disp
, 0, 0} },
305 {"jbe", 1, 0x76, _
, Jump
, { Disp
, 0, 0} },
306 {"jna", 1, 0x76, _
, Jump
, { Disp
, 0, 0} },
308 {"jnbe", 1, 0x77, _
, Jump
, { Disp
, 0, 0} },
309 {"ja", 1, 0x77, _
, Jump
, { Disp
, 0, 0} },
311 {"js", 1, 0x78, _
, Jump
, { Disp
, 0, 0} },
313 {"jns", 1, 0x79, _
, Jump
, { Disp
, 0, 0} },
315 {"jp", 1, 0x7a, _
, Jump
, { Disp
, 0, 0} },
316 {"jpe", 1, 0x7a, _
, Jump
, { Disp
, 0, 0} },
318 {"jnp", 1, 0x7b, _
, Jump
, { Disp
, 0, 0} },
319 {"jpo", 1, 0x7b, _
, Jump
, { Disp
, 0, 0} },
321 {"jl", 1, 0x7c, _
, Jump
, { Disp
, 0, 0} },
322 {"jnge", 1, 0x7c, _
, Jump
, { Disp
, 0, 0} },
324 {"jnl", 1, 0x7d, _
, Jump
, { Disp
, 0, 0} },
325 {"jge", 1, 0x7d, _
, Jump
, { Disp
, 0, 0} },
327 {"jle", 1, 0x7e, _
, Jump
, { Disp
, 0, 0} },
328 {"jng", 1, 0x7e, _
, Jump
, { Disp
, 0, 0} },
330 {"jnle", 1, 0x7f, _
, Jump
, { Disp
, 0, 0} },
331 {"jg", 1, 0x7f, _
, Jump
, { Disp
, 0, 0} },
333 #if 0 /* XXX where are these macros used?
334 To get them working again, they need to take
335 an entire template as the parameter,
336 and check for Data16/Data32 flags. */
337 /* these turn into pseudo operations when disp is larger than 8 bits */
338 #define IS_JUMP_ON_CX_ZERO(o) \
340 #define IS_JUMP_ON_ECX_ZERO(o) \
344 {"jcxz", 1, 0xe3, _
, JumpByte
|Data16
, { Disp
, 0, 0} },
345 {"jecxz", 1, 0xe3, _
, JumpByte
|Data32
, { Disp
, 0, 0} },
347 #define IS_LOOP_ECX_TIMES(o) \
348 (o == 0xe2 || o == 0xe1 || o == 0xe0)
350 {"loop", 1, 0xe2, _
, JumpByte
, { Disp
, 0, 0} },
352 {"loopz", 1, 0xe1, _
, JumpByte
, { Disp
, 0, 0} },
353 {"loope", 1, 0xe1, _
, JumpByte
, { Disp
, 0, 0} },
355 {"loopnz", 1, 0xe0, _
, JumpByte
, { Disp
, 0, 0} },
356 {"loopne", 1, 0xe0, _
, JumpByte
, { Disp
, 0, 0} },
358 /* set byte on flag instructions */
359 {"seto", 1, 0x0f90, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
361 {"setno", 1, 0x0f91, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
363 {"setb", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
364 {"setc", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
365 {"setnae", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
367 {"setnb", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
368 {"setnc", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
369 {"setae", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
371 {"sete", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
372 {"setz", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
374 {"setne", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
375 {"setnz", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
377 {"setbe", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
378 {"setna", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
380 {"setnbe", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
381 {"seta", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
383 {"sets", 1, 0x0f98, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
385 {"setns", 1, 0x0f99, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
387 {"setp", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
388 {"setpe", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
390 {"setnp", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
391 {"setpo", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
393 {"setl", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
394 {"setnge", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
396 {"setnl", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
397 {"setge", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
399 {"setle", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
400 {"setng", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
402 {"setnle", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
403 {"setg", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
405 #define IS_STRING_INSTRUCTION(o) \
406 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
407 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
410 /* string manipulation */
411 {"cmps", 0, 0xa6, _
, W
|NoModrm
, { 0, 0, 0} },
412 {"scmp", 0, 0xa6, _
, W
|NoModrm
, { 0, 0, 0} },
413 {"ins", 0, 0x6c, _
, W
|NoModrm
, { 0, 0, 0} },
414 {"outs", 0, 0x6e, _
, W
|NoModrm
, { 0, 0, 0} },
415 {"lods", 0, 0xac, _
, W
|NoModrm
, { 0, 0, 0} },
416 {"slod", 0, 0xac, _
, W
|NoModrm
, { 0, 0, 0} },
417 {"movs", 0, 0xa4, _
, W
|NoModrm
, { 0, 0, 0} },
418 {"smov", 0, 0xa4, _
, W
|NoModrm
, { 0, 0, 0} },
419 {"scas", 0, 0xae, _
, W
|NoModrm
, { 0, 0, 0} },
420 {"ssca", 0, 0xae, _
, W
|NoModrm
, { 0, 0, 0} },
421 {"stos", 0, 0xaa, _
, W
|NoModrm
, { 0, 0, 0} },
422 {"ssto", 0, 0xaa, _
, W
|NoModrm
, { 0, 0, 0} },
423 {"xlat", 0, 0xd7, _
, NoModrm
, { 0, 0, 0} },
425 /* bit manipulation */
426 {"bsf", 2, 0x0fbc, _
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
427 {"bsr", 2, 0x0fbd, _
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
428 {"bt", 2, 0x0fa3, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
429 {"bt", 2, 0x0fba, 4, Modrm
, { Imm8
, Reg
|Mem
, 0} },
430 {"btc", 2, 0x0fbb, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
431 {"btc", 2, 0x0fba, 7, Modrm
, { Imm8
, Reg
|Mem
, 0} },
432 {"btr", 2, 0x0fb3, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
433 {"btr", 2, 0x0fba, 6, Modrm
, { Imm8
, Reg
|Mem
, 0} },
434 {"bts", 2, 0x0fab, _
, Modrm
, { Reg
, Reg
|Mem
, 0} },
435 {"bts", 2, 0x0fba, 5, Modrm
, { Imm8
, Reg
|Mem
, 0} },
437 /* interrupts & op. sys insns */
438 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
440 #define INT_OPCODE 0xcd
441 #define INT3_OPCODE 0xcc
442 {"int", 1, 0xcd, _
, NoModrm
, { Imm8
, 0, 0} },
443 {"int3", 0, 0xcc, _
, NoModrm
, { 0, 0, 0} },
444 {"into", 0, 0xce, _
, NoModrm
, { 0, 0, 0} },
445 {"iret", 0, 0xcf, _
, NoModrm
|Data32
, { 0, 0, 0} },
446 {"iretw", 0, 0xcf, _
, NoModrm
|Data16
, { 0, 0, 0} },
447 /* i386sl (and i486sl?) only */
448 {"rsm", 0, 0x0faa, _
, NoModrm
,{ 0, 0, 0} },
450 {"boundl", 2, 0x62, _
, Modrm
|Data32
, { Reg32
, Mem
, 0} },
451 {"boundw", 2, 0x62, _
, Modrm
|Data16
, { Reg16
, Mem
, 0} },
453 {"hlt", 0, 0xf4, _
, NoModrm
, { 0, 0, 0} },
454 {"wait", 0, 0x9b, _
, NoModrm
, { 0, 0, 0} },
455 /* nop is actually 'xchgl %eax, %eax' */
456 {"nop", 0, 0x90, _
, NoModrm
, { 0, 0, 0} },
458 /* protection control */
459 {"arpl", 2, 0x63, _
, Modrm
, { Reg16
, Reg16
|Mem
, 0} },
460 {"lar", 2, 0x0f02, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
461 {"lgdt", 1, 0x0f01, 2, Modrm
, { Mem
, 0, 0} },
462 {"lidt", 1, 0x0f01, 3, Modrm
, { Mem
, 0, 0} },
463 {"lldt", 1, 0x0f00, 2, Modrm
, { WordReg
|Mem
, 0, 0} },
464 {"lmsw", 1, 0x0f01, 6, Modrm
, { WordReg
|Mem
, 0, 0} },
465 {"lsl", 2, 0x0f03, _
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
466 {"ltr", 1, 0x0f00, 3, Modrm
, { WordReg
|Mem
, 0, 0} },
468 {"sgdt", 1, 0x0f01, 0, Modrm
, { Mem
, 0, 0} },
469 {"sidt", 1, 0x0f01, 1, Modrm
, { Mem
, 0, 0} },
470 {"sldt", 1, 0x0f00, 0, Modrm
, { WordReg
|Mem
, 0, 0} },
471 {"smsw", 1, 0x0f01, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
472 {"str", 1, 0x0f00, 1, Modrm
, { Reg16
|Mem
, 0, 0} },
474 {"verr", 1, 0x0f00, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
475 {"verw", 1, 0x0f00, 5, Modrm
, { WordReg
|Mem
, 0, 0} },
477 /* floating point instructions */
480 {"fld", 1, 0xd9c0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
481 {"flds", 1, 0xd9, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem float */
482 {"fldl", 1, 0xdd, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem double */
483 {"fldl", 1, 0xd9c0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
484 {"fild", 1, 0xdf, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem word (16) */
485 {"fildl", 1, 0xdb, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem dword (32) */
486 {"fildq",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
487 {"fildll",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
488 {"fldt", 1, 0xdb, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem efloat */
489 {"fbld", 1, 0xdf, 4, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem bcd */
492 {"fst", 1, 0xddd0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
493 {"fsts", 1, 0xd9, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
494 {"fstl", 1, 0xdd, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
495 {"fstl", 1, 0xddd0, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
496 {"fist", 1, 0xdf, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
497 {"fistl", 1, 0xdb, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
499 /* store (with pop) */
500 {"fstp", 1, 0xddd8, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
501 {"fstps", 1, 0xd9, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
502 {"fstpl", 1, 0xdd, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
503 {"fstpl", 1, 0xddd8, _
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
504 {"fistp", 1, 0xdf, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
505 {"fistpl",1, 0xdb, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
506 {"fistpq",1, 0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
507 {"fistpll",1,0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
508 {"fstpt", 1, 0xdb, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem efloat */
509 {"fbstp", 1, 0xdf, 6, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem bcd */
511 /* exchange %st<n> with %st0 */
512 {"fxch", 1, 0xd9c8, _
, ShortForm
, { FloatReg
, 0, 0} },
513 {"fxch", 0, 0xd9c9, _
, NoModrm
, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
515 /* comparison (without pop) */
516 {"fcom", 1, 0xd8d0, _
, ShortForm
, { FloatReg
, 0, 0} },
517 {"fcoms", 1, 0xd8, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
518 {"ficoml", 1, 0xda, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
519 {"fcoml", 1, 0xdc, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
520 {"fcoml", 1, 0xd8d0, _
, ShortForm
, { FloatReg
, 0, 0} },
521 {"ficoms", 1, 0xde, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
523 /* comparison (with pop) */
524 {"fcomp", 1, 0xd8d8, _
, ShortForm
, { FloatReg
, 0, 0} },
525 {"fcomps", 1, 0xd8, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
526 {"ficompl", 1, 0xda, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
527 {"fcompl", 1, 0xdc, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
528 {"fcompl", 1, 0xd8d8, _
, ShortForm
, { FloatReg
, 0, 0} },
529 {"ficomps", 1, 0xde, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
530 {"fcompp", 0, 0xded9, _
, NoModrm
, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
532 /* unordered comparison (with pop) */
533 {"fucom", 1, 0xdde0, _
, ShortForm
, { FloatReg
, 0, 0} },
534 {"fucomp", 1, 0xdde8, _
, ShortForm
, { FloatReg
, 0, 0} },
535 {"fucompp", 0, 0xdae9, _
, NoModrm
, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
537 {"ftst", 0, 0xd9e4, _
, NoModrm
, { 0, 0, 0} }, /* test %st0 */
538 {"fxam", 0, 0xd9e5, _
, NoModrm
, { 0, 0, 0} }, /* examine %st0 */
540 /* load constants into %st0 */
541 {"fld1", 0, 0xd9e8, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- 1.0 */
542 {"fldl2t", 0, 0xd9e9, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- log2(10) */
543 {"fldl2e", 0, 0xd9ea, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- log2(e) */
544 {"fldpi", 0, 0xd9eb, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- pi */
545 {"fldlg2", 0, 0xd9ec, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- log10(2) */
546 {"fldln2", 0, 0xd9ed, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- ln(2) */
547 {"fldz", 0, 0xd9ee, _
, NoModrm
, { 0, 0, 0} }, /* %st0 <-- 0.0 */
552 {"fadd", 1, 0xd8c0, _
, ShortForm
, { FloatReg
, 0, 0} },
553 {"fadd", 2, 0xd8c0, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
554 {"fadd", 0, 0xdcc1, _
, NoModrm
, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
555 {"faddp", 1, 0xdac0, _
, ShortForm
, { FloatReg
, 0, 0} },
556 {"faddp", 2, 0xdac0, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
557 {"faddp", 0, 0xdec1, _
, NoModrm
, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
558 {"fadds", 1, 0xd8, 0, Modrm
, { Mem
, 0, 0} },
559 {"fiaddl", 1, 0xda, 0, Modrm
, { Mem
, 0, 0} },
560 {"faddl", 1, 0xdc, 0, Modrm
, { Mem
, 0, 0} },
561 {"fiadds", 1, 0xde, 0, Modrm
, { Mem
, 0, 0} },
564 /* Note: intel has decided that certain of these operations are reversed
565 in assembler syntax. */
566 {"fsub", 1, 0xd8e0, _
, ShortForm
, { FloatReg
, 0, 0} },
567 {"fsub", 2, 0xd8e0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
568 #ifdef NON_BROKEN_OPCODES
569 {"fsub", 2, 0xdce8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
571 {"fsub", 2, 0xdce0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
573 {"fsub", 0, 0xdce1, _
, NoModrm
, { 0, 0, 0} },
574 {"fsubp", 1, 0xdae0, _
, ShortForm
, { FloatReg
, 0, 0} },
575 {"fsubp", 2, 0xdae0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
576 #ifdef NON_BROKEN_OPCODES
577 {"fsubp", 2, 0xdee8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
579 {"fsubp", 2, 0xdee0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
581 {"fsubp", 0, 0xdee1, _
, NoModrm
, { 0, 0, 0} },
582 {"fsubs", 1, 0xd8, 4, Modrm
, { Mem
, 0, 0} },
583 {"fisubl", 1, 0xda, 4, Modrm
, { Mem
, 0, 0} },
584 {"fsubl", 1, 0xdc, 4, Modrm
, { Mem
, 0, 0} },
585 {"fisubs", 1, 0xde, 4, Modrm
, { Mem
, 0, 0} },
588 {"fsubr", 1, 0xd8e8, _
, ShortForm
, { FloatReg
, 0, 0} },
589 {"fsubr", 2, 0xd8e8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
590 #ifdef NON_BROKEN_OPCODES
591 {"fsubr", 2, 0xdce0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
593 {"fsubr", 2, 0xdce8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
595 {"fsubr", 0, 0xdce9, _
, NoModrm
, { 0, 0, 0} },
596 {"fsubrp", 1, 0xdae8, _
, ShortForm
, { FloatReg
, 0, 0} },
597 {"fsubrp", 2, 0xdae8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
598 #ifdef NON_BROKEN_OPCODES
599 {"fsubrp", 2, 0xdee0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
601 {"fsubrp", 2, 0xdee8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
603 {"fsubrp", 0, 0xdee9, _
, NoModrm
, { 0, 0, 0} },
604 {"fsubrs", 1, 0xd8, 5, Modrm
, { Mem
, 0, 0} },
605 {"fisubrl", 1, 0xda, 5, Modrm
, { Mem
, 0, 0} },
606 {"fsubrl", 1, 0xdc, 5, Modrm
, { Mem
, 0, 0} },
607 {"fisubrs", 1, 0xde, 5, Modrm
, { Mem
, 0, 0} },
610 {"fmul", 1, 0xd8c8, _
, ShortForm
, { FloatReg
, 0, 0} },
611 {"fmul", 2, 0xd8c8, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
612 {"fmul", 0, 0xdcc9, _
, NoModrm
, { 0, 0, 0} },
613 {"fmulp", 1, 0xdac8, _
, ShortForm
, { FloatReg
, 0, 0} },
614 {"fmulp", 2, 0xdac8, _
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
615 {"fmulp", 0, 0xdec9, _
, NoModrm
, { 0, 0, 0} },
616 {"fmuls", 1, 0xd8, 1, Modrm
, { Mem
, 0, 0} },
617 {"fimull", 1, 0xda, 1, Modrm
, { Mem
, 0, 0} },
618 {"fmull", 1, 0xdc, 1, Modrm
, { Mem
, 0, 0} },
619 {"fimuls", 1, 0xde, 1, Modrm
, { Mem
, 0, 0} },
622 /* Note: intel has decided that certain of these operations are reversed
623 in assembler syntax. */
624 {"fdiv", 1, 0xd8f0, _
, ShortForm
, { FloatReg
, 0, 0} },
625 {"fdiv", 2, 0xd8f0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
626 #ifdef NON_BROKEN_OPCODES
627 {"fdiv", 2, 0xdcf8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
629 {"fdiv", 2, 0xdcf0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
631 {"fdiv", 0, 0xdcf1, _
, NoModrm
, { 0, 0, 0} },
632 {"fdivp", 1, 0xdaf0, _
, ShortForm
, { FloatReg
, 0, 0} },
633 {"fdivp", 2, 0xdaf0, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
634 #ifdef NON_BROKEN_OPCODES
635 {"fdivp", 2, 0xdef8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
637 {"fdivp", 2, 0xdef0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
639 {"fdivp", 0, 0xdef1, _
, NoModrm
, { 0, 0, 0} },
640 {"fdivs", 1, 0xd8, 6, Modrm
, { Mem
, 0, 0} },
641 {"fidivl", 1, 0xda, 6, Modrm
, { Mem
, 0, 0} },
642 {"fdivl", 1, 0xdc, 6, Modrm
, { Mem
, 0, 0} },
643 {"fidivs", 1, 0xde, 6, Modrm
, { Mem
, 0, 0} },
646 {"fdivr", 1, 0xd8f8, _
, ShortForm
, { FloatReg
, 0, 0} },
647 {"fdivr", 2, 0xd8f8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
648 #ifdef NON_BROKEN_OPCODES
649 {"fdivr", 2, 0xdcf0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
651 {"fdivr", 2, 0xdcf8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
653 {"fdivr", 0, 0xdcf9, _
, NoModrm
, { 0, 0, 0} },
654 {"fdivrp", 1, 0xdaf8, _
, ShortForm
, { FloatReg
, 0, 0} },
655 {"fdivrp", 2, 0xdaf8, _
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
656 #ifdef NON_BROKEN_OPCODES
657 {"fdivrp", 2, 0xdef0, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
659 {"fdivrp", 2, 0xdef8, _
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
661 {"fdivrp", 0, 0xdef9, _
, NoModrm
, { 0, 0, 0} },
662 {"fdivrs", 1, 0xd8, 7, Modrm
, { Mem
, 0, 0} },
663 {"fidivrl", 1, 0xda, 7, Modrm
, { Mem
, 0, 0} },
664 {"fdivrl", 1, 0xdc, 7, Modrm
, { Mem
, 0, 0} },
665 {"fidivrs", 1, 0xde, 7, Modrm
, { Mem
, 0, 0} },
667 {"f2xm1", 0, 0xd9f0, _
, NoModrm
, { 0, 0, 0} },
668 {"fyl2x", 0, 0xd9f1, _
, NoModrm
, { 0, 0, 0} },
669 {"fptan", 0, 0xd9f2, _
, NoModrm
, { 0, 0, 0} },
670 {"fpatan", 0, 0xd9f3, _
, NoModrm
, { 0, 0, 0} },
671 {"fxtract", 0, 0xd9f4, _
, NoModrm
, { 0, 0, 0} },
672 {"fprem1", 0, 0xd9f5, _
, NoModrm
, { 0, 0, 0} },
673 {"fdecstp", 0, 0xd9f6, _
, NoModrm
, { 0, 0, 0} },
674 {"fincstp", 0, 0xd9f7, _
, NoModrm
, { 0, 0, 0} },
675 {"fprem", 0, 0xd9f8, _
, NoModrm
, { 0, 0, 0} },
676 {"fyl2xp1", 0, 0xd9f9, _
, NoModrm
, { 0, 0, 0} },
677 {"fsqrt", 0, 0xd9fa, _
, NoModrm
, { 0, 0, 0} },
678 {"fsincos", 0, 0xd9fb, _
, NoModrm
, { 0, 0, 0} },
679 {"frndint", 0, 0xd9fc, _
, NoModrm
, { 0, 0, 0} },
680 {"fscale", 0, 0xd9fd, _
, NoModrm
, { 0, 0, 0} },
681 {"fsin", 0, 0xd9fe, _
, NoModrm
, { 0, 0, 0} },
682 {"fcos", 0, 0xd9ff, _
, NoModrm
, { 0, 0, 0} },
684 {"fchs", 0, 0xd9e0, _
, NoModrm
, { 0, 0, 0} },
685 {"fabs", 0, 0xd9e1, _
, NoModrm
, { 0, 0, 0} },
687 /* processor control */
688 {"fninit", 0, 0xdbe3, _
, NoModrm
, { 0, 0, 0} },
689 {"finit", 0, 0xdbe3, _
, NoModrm
, { 0, 0, 0} },
690 {"fldcw", 1, 0xd9, 5, Modrm
, { Mem
, 0, 0} },
691 {"fnstcw", 1, 0xd9, 7, Modrm
, { Mem
, 0, 0} },
692 {"fstcw", 1, 0xd9, 7, Modrm
, { Mem
, 0, 0} },
693 {"fnstsw", 1, 0xdfe0, _
, NoModrm
, { Acc
, 0, 0} },
694 {"fnstsw", 1, 0xdd, 7, Modrm
, { Mem
, 0, 0} },
695 {"fnstsw", 0, 0xdfe0, _
, NoModrm
, { 0, 0, 0} },
696 {"fstsw", 1, 0xdfe0, _
, NoModrm
, { Acc
, 0, 0} },
697 {"fstsw", 1, 0xdd, 7, Modrm
, { Mem
, 0, 0} },
698 {"fstsw", 0, 0xdfe0, _
, NoModrm
, { 0, 0, 0} },
699 {"fnclex", 0, 0xdbe2, _
, NoModrm
, { 0, 0, 0} },
700 {"fclex", 0, 0xdbe2, _
, NoModrm
, { 0, 0, 0} },
702 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
703 instructions; i'm not sure how to add them or how they are different.
704 My 386/387 book offers no details about this.
706 {"fnstenv", 1, 0xd9, 6, Modrm
, { Mem
, 0, 0} },
707 {"fstenv", 1, 0xd9, 6, Modrm
, { Mem
, 0, 0} },
708 {"fldenv", 1, 0xd9, 4, Modrm
, { Mem
, 0, 0} },
709 {"fnsave", 1, 0xdd, 6, Modrm
, { Mem
, 0, 0} },
710 {"fsave", 1, 0xdd, 6, Modrm
, { Mem
, 0, 0} },
711 {"frstor", 1, 0xdd, 4, Modrm
, { Mem
, 0, 0} },
713 {"ffree", 1, 0xddc0, _
, ShortForm
, { FloatReg
, 0, 0} },
714 {"fnop", 0, 0xd9d0, _
, NoModrm
, { 0, 0, 0} },
715 {"fwait", 0, 0x9b, _
, NoModrm
, { 0, 0, 0} },
718 opcode prefixes; we allow them as seperate insns too
719 (see prefix table below)
721 {"aword", 0, 0x67, _
, NoModrm
, { 0, 0, 0} },
722 {"addr16", 0, 0x67, _
, NoModrm
, { 0, 0, 0} },
723 {"word", 0, 0x66, _
, NoModrm
, { 0, 0, 0} },
724 {"data16", 0, 0x66, _
, NoModrm
, { 0, 0, 0} },
725 {"lock", 0, 0xf0, _
, NoModrm
, { 0, 0, 0} },
726 {"cs", 0, 0x2e, _
, NoModrm
, { 0, 0, 0} },
727 {"ds", 0, 0x3e, _
, NoModrm
, { 0, 0, 0} },
728 {"es", 0, 0x26, _
, NoModrm
, { 0, 0, 0} },
729 {"fs", 0, 0x64, _
, NoModrm
, { 0, 0, 0} },
730 {"gs", 0, 0x65, _
, NoModrm
, { 0, 0, 0} },
731 {"ss", 0, 0x36, _
, NoModrm
, { 0, 0, 0} },
732 {"rep", 0, 0xf3, _
, NoModrm
, { 0, 0, 0} },
733 {"repe", 0, 0xf3, _
, NoModrm
, { 0, 0, 0} },
734 {"repz", 0, 0xf3, _
, NoModrm
, { 0, 0, 0} },
735 {"repne", 0, 0xf2, _
, NoModrm
, { 0, 0, 0} },
736 {"repnz", 0, 0xf2, _
, NoModrm
, { 0, 0, 0} },
740 {"bswap", 1, 0x0fc8, _
, ShortForm
, { Reg32
,0,0 } },
741 {"xadd", 2, 0x0fc0, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
742 {"cmpxchg", 2, 0x0fb0, _
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
743 {"invd", 0, 0x0f08, _
, NoModrm
, { 0, 0, 0} },
744 {"wbinvd", 0, 0x0f09, _
, NoModrm
, { 0, 0, 0} },
745 {"invlpg", 1, 0x0f01, 7, Modrm
, { Mem
, 0, 0} },
747 {"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
751 static const template *const i386_optab_end
752 = i386_optab
+ sizeof (i386_optab
)/sizeof(i386_optab
[0]);
754 /* 386 register table */
756 static const reg_entry i386_regtab
[] = {
758 {"al", Reg8
|Acc
, 0}, {"cl", Reg8
|ShiftCount
, 1}, {"dl", Reg8
, 2},
760 {"ah", Reg8
, 4}, {"ch", Reg8
, 5}, {"dh", Reg8
, 6}, {"bh", Reg8
, 7},
762 {"ax", Reg16
|Acc
, 0}, {"cx", Reg16
, 1}, {"dx", Reg16
|InOutPortReg
, 2}, {"bx", Reg16
, 3},
763 {"sp", Reg16
, 4}, {"bp", Reg16
, 5}, {"si", Reg16
, 6}, {"di", Reg16
, 7},
765 {"eax", Reg32
|Acc
, 0}, {"ecx", Reg32
, 1}, {"edx", Reg32
, 2}, {"ebx", Reg32
, 3},
766 {"esp", Reg32
, 4}, {"ebp", Reg32
, 5}, {"esi", Reg32
, 6}, {"edi", Reg32
, 7},
767 /* segment registers */
768 {"es", SReg2
, 0}, {"cs", SReg2
, 1}, {"ss", SReg2
, 2},
769 {"ds", SReg2
, 3}, {"fs", SReg3
, 4}, {"gs", SReg3
, 5},
770 /* control registers */
771 {"cr0", Control
, 0}, {"cr2", Control
, 2}, {"cr3", Control
, 3},
772 /* debug registers */
773 {"db0", Debug
, 0}, {"db1", Debug
, 1}, {"db2", Debug
, 2},
774 {"db3", Debug
, 3}, {"db6", Debug
, 6}, {"db7", Debug
, 7},
776 {"tr6", Test
, 6}, {"tr7", Test
, 7},
777 /* float registers */
778 {"st(0)", FloatReg
|FloatAcc
, 0},
779 {"st", FloatReg
|FloatAcc
, 0},
780 {"st(1)", FloatReg
, 1}, {"st(2)", FloatReg
, 2},
781 {"st(3)", FloatReg
, 3}, {"st(4)", FloatReg
, 4}, {"st(5)", FloatReg
, 5},
782 {"st(6)", FloatReg
, 6}, {"st(7)", FloatReg
, 7}
785 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
787 static const reg_entry
*const i386_regtab_end
788 = i386_regtab
+ sizeof(i386_regtab
)/sizeof(i386_regtab
[0]);
791 static const seg_entry cs
= { "cs", 0x2e };
792 static const seg_entry ds
= { "ds", 0x3e };
793 static const seg_entry ss
= { "ss", 0x36 };
794 static const seg_entry es
= { "es", 0x26 };
795 static const seg_entry fs
= { "fs", 0x64 };
796 static const seg_entry gs
= { "gs", 0x65 };
797 static const seg_entry null
= { "", 0x0 };
800 This table is used to store the default segment register implied by all
801 possible memory addressing modes.
802 It is indexed by the mode & modrm entries of the modrm byte as follows:
803 index = (mode<<3) | modrm;
805 static const seg_entry
*const one_byte_segment_defaults
[] = {
807 &ds
, &ds
, &ds
, &ds
, &null
, &ds
, &ds
, &ds
,
809 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
811 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
812 /* mode 3 --- not a memory reference; never referenced */
815 static const seg_entry
*const two_byte_segment_defaults
[] = {
817 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
819 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
821 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
822 /* mode 3 --- not a memory reference; never referenced */
825 static const prefix_entry i386_prefixtab
[] = {
826 #define ADDR_PREFIX_OPCODE 0x67
827 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
828 * (How is this useful?) */
829 #define WORD_PREFIX_OPCODE 0x66
830 { "data16", 0x66 }, /* operand size prefix */
831 { "lock", 0xf0 }, /* bus lock prefix */
832 { "wait", 0x9b }, /* wait for coprocessor */
833 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
834 { "es", 0x26 }, { "fs", 0x64 },
835 { "gs", 0x65 }, { "ss", 0x36 },
836 /* REPE & REPNE used to detect rep/repne with a non-string instruction */
839 { "rep", 0xf3 }, /* repeat string instructions */
840 { "repe", 0xf3 }, { "repz", 0xf3 },
841 { "repne", 0xf2 }, { "repnz", 0xf2 }
844 static const prefix_entry
*const i386_prefixtab_end
845 = i386_prefixtab
+ sizeof(i386_prefixtab
)/sizeof(i386_prefixtab
[0]);
847 /* end of i386-opcode.h */