1 /* i386-opcode.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /* The NON_BROKEN_OPCODES cases use the operands in the reverse order
21 from that documented in the Intel manuals. The opcode values are
22 such that they actually generate different instructions. These
23 values must not be changed, as they are the values generated by the
24 UnixWare assembler, and possibly other ix86 assemblers. */
26 static const template i386_optab
[] = {
30 /* move instructions */
31 #define MOV_AX_DISP32 0xa0
32 { "mov", 2, 0xa0, X
, DW
, { Disp32
, Acc
, 0 } },
33 { "mov", 2, 0x88, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
34 { "mov", 2, 0xb0, X
, ShortFormW
, { Imm
, Reg
, 0 } },
35 { "mov", 2, 0xc6, X
, W
|Modrm
, { Imm
, Reg
|Mem
, 0 } },
36 /* The next instruction accepts WordReg so that `movl %gs,%esi' can be
37 used to move a segment register to a 32 bit register without using
38 a size prefix. This will set the upper 16 bits of the 32 bit
39 register to an implementation defined value (on the Pentium Pro,
40 the implementation defined value is zero). */
41 { "mov", 2, 0x8c, X
, D
|Modrm
, { SReg3
|SReg2
, WordReg
|WordMem
, 0 } },
42 /* move to/from control debug registers */
43 { "mov", 2, 0x0f20, X
, D
|Modrm
, { Control
, Reg32
, 0} },
44 { "mov", 2, 0x0f21, X
, D
|Modrm
, { Debug
, Reg32
, 0} },
45 { "mov", 2, 0x0f24, X
, D
|Modrm
, { Test
, Reg32
, 0} },
47 /* move with sign extend */
48 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
49 conflict with the "movs" string move instruction. Thus,
50 {"movsb", 2, 0x0fbe, X, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
51 is not kosher; we must seperate the two instructions. */
52 {"movsbl", 2, 0x0fbe, X
, ReverseRegRegmem
|Modrm
|Data32
, { Reg8
|Mem
, Reg32
, 0} },
53 {"movsbw", 2, 0x0fbe, X
, ReverseRegRegmem
|Modrm
|Data16
, { Reg8
|Mem
, Reg16
, 0} },
54 {"movswl", 2, 0x0fbf, X
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
56 /* move with zero extend */
57 {"movzb", 2, 0x0fb6, X
, ReverseRegRegmem
|Modrm
, { Reg8
|Mem
, Reg16
|Reg32
, 0} },
58 {"movzwl", 2, 0x0fb7, X
, ReverseRegRegmem
|Modrm
, { Reg16
|Mem
, Reg32
, 0} },
60 /* push instructions */
61 {"push", 1, 0x50, X
, ShortForm
, { WordReg
,0,0 } },
62 {"push", 1, 0xff, 0x6, Modrm
, { WordReg
|WordMem
, 0, 0 } },
63 {"push", 1, 0x6a, X
, 0, { Imm8S
, 0, 0} },
64 {"push", 1, 0x68, X
, 0, { Imm16
|Imm32
, 0, 0} },
65 {"push", 1, 0x06, X
, Seg2ShortForm
, { SReg2
,0,0 } },
66 {"push", 1, 0x0fa0, X
, Seg3ShortForm
, { SReg3
,0,0 } },
68 {"pusha", 0, 0x60, X
, 0, { 0, 0, 0 } },
70 /* pop instructions */
71 {"pop", 1, 0x58, X
, ShortForm
, { WordReg
,0,0 } },
72 {"pop", 1, 0x8f, 0x0, Modrm
, { WordReg
|WordMem
, 0, 0 } },
73 #define POP_SEG_SHORT 0x7
74 {"pop", 1, 0x07, X
, Seg2ShortForm
, { SReg2
,0,0 } },
75 {"pop", 1, 0x0fa1, X
, Seg3ShortForm
, { SReg3
,0,0 } },
77 {"popa", 0, 0x61, X
, 0, { 0, 0, 0 } },
79 /* xchg exchange instructions
80 xchg commutes: we allow both operand orders */
81 {"xchg", 2, 0x90, X
, ShortForm
, { WordReg
, Acc
, 0 } },
82 {"xchg", 2, 0x90, X
, ShortForm
, { Acc
, WordReg
, 0 } },
83 {"xchg", 2, 0x86, X
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
84 {"xchg", 2, 0x86, X
, W
|Modrm
, { Reg
|Mem
, Reg
, 0 } },
86 /* in/out from ports */
87 {"in", 2, 0xe4, X
, W
, { Imm8
, Acc
, 0 } },
88 {"in", 2, 0xec, X
, W
, { InOutPortReg
, Acc
, 0 } },
89 {"in", 1, 0xe4, X
, W
, { Imm8
, 0, 0 } },
90 {"in", 1, 0xec, X
, W
, { InOutPortReg
, 0, 0 } },
91 {"out", 2, 0xe6, X
, W
, { Acc
, Imm8
, 0 } },
92 {"out", 2, 0xee, X
, W
, { Acc
, InOutPortReg
, 0 } },
93 {"out", 1, 0xe6, X
, W
, { Imm8
, 0, 0 } },
94 {"out", 1, 0xee, X
, W
, { InOutPortReg
, 0, 0 } },
96 /* load effective address */
97 {"lea", 2, 0x8d, X
, Modrm
, { WordMem
, WordReg
, 0 } },
99 /* load segment registers from memory */
100 {"lds", 2, 0xc5, X
, Modrm
, { Mem
, Reg32
, 0} },
101 {"les", 2, 0xc4, X
, Modrm
, { Mem
, Reg32
, 0} },
102 {"lfs", 2, 0x0fb4, X
, Modrm
, { Mem
, Reg32
, 0} },
103 {"lgs", 2, 0x0fb5, X
, Modrm
, { Mem
, Reg32
, 0} },
104 {"lss", 2, 0x0fb2, X
, Modrm
, { Mem
, Reg32
, 0} },
106 /* flags register instructions */
107 {"clc", 0, 0xf8, X
, 0, { 0, 0, 0} },
108 {"cld", 0, 0xfc, X
, 0, { 0, 0, 0} },
109 {"cli", 0, 0xfa, X
, 0, { 0, 0, 0} },
110 {"clts", 0, 0x0f06, X
, 0, { 0, 0, 0} },
111 {"cmc", 0, 0xf5, X
, 0, { 0, 0, 0} },
112 {"lahf", 0, 0x9f, X
, 0, { 0, 0, 0} },
113 {"sahf", 0, 0x9e, X
, 0, { 0, 0, 0} },
114 {"pushfl", 0, 0x9c, X
, Data32
, { 0, 0, 0} },
115 {"popfl", 0, 0x9d, X
, Data32
, { 0, 0, 0} },
116 {"pushfw", 0, 0x9c, X
, Data16
, { 0, 0, 0} },
117 {"popfw", 0, 0x9d, X
, Data16
, { 0, 0, 0} },
118 {"pushf", 0, 0x9c, X
, 0, { 0, 0, 0} },
119 {"popf", 0, 0x9d, X
, 0, { 0, 0, 0} },
120 {"stc", 0, 0xf9, X
, 0, { 0, 0, 0} },
121 {"std", 0, 0xfd, X
, 0, { 0, 0, 0} },
122 {"sti", 0, 0xfb, X
, 0, { 0, 0, 0} },
124 {"add", 2, 0x0, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
125 {"add", 2, 0x83, 0, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
126 {"add", 2, 0x4, X
, W
, { Imm
, Acc
, 0} },
127 {"add", 2, 0x80, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
129 {"inc", 1, 0x40, X
, ShortForm
, { WordReg
, 0, 0} },
130 {"inc", 1, 0xfe, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
132 {"sub", 2, 0x28, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
133 {"sub", 2, 0x83, 5, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
134 {"sub", 2, 0x2c, X
, W
, { Imm
, Acc
, 0} },
135 {"sub", 2, 0x80, 5, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
137 {"dec", 1, 0x48, X
, ShortForm
, { WordReg
, 0, 0} },
138 {"dec", 1, 0xfe, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
140 {"sbb", 2, 0x18, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
141 {"sbb", 2, 0x83, 3, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
142 {"sbb", 2, 0x1c, X
, W
, { Imm
, Acc
, 0} },
143 {"sbb", 2, 0x80, 3, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
145 {"cmp", 2, 0x38, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
146 {"cmp", 2, 0x83, 7, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
147 {"cmp", 2, 0x3c, X
, W
, { Imm
, Acc
, 0} },
148 {"cmp", 2, 0x80, 7, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
150 {"test", 2, 0x84, X
, W
|Modrm
, { Reg
|Mem
, Reg
, 0} },
151 {"test", 2, 0x84, X
, W
|Modrm
, { Reg
, Reg
|Mem
, 0} },
152 {"test", 2, 0xa8, X
, W
, { Imm
, Acc
, 0} },
153 {"test", 2, 0xf6, 0, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
155 {"and", 2, 0x20, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
156 {"and", 2, 0x83, 4, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
157 {"and", 2, 0x24, X
, W
, { Imm
, Acc
, 0} },
158 {"and", 2, 0x80, 4, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
160 {"or", 2, 0x08, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
161 {"or", 2, 0x83, 1, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
162 {"or", 2, 0x0c, X
, W
, { Imm
, Acc
, 0} },
163 {"or", 2, 0x80, 1, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
165 {"xor", 2, 0x30, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
166 {"xor", 2, 0x83, 6, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
167 {"xor", 2, 0x34, X
, W
, { Imm
, Acc
, 0} },
168 {"xor", 2, 0x80, 6, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
170 /* iclr with 1 operand is really xor with 2 operands. */
171 {"clr", 1, 0x30, X
, W
|Modrm
|regKludge
, { Reg
} },
173 {"adc", 2, 0x10, X
, DW
|Modrm
, { Reg
, Reg
|Mem
, 0} },
174 {"adc", 2, 0x83, 2, Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
175 {"adc", 2, 0x14, X
, W
, { Imm
, Acc
, 0} },
176 {"adc", 2, 0x80, 2, W
|Modrm
, { Imm
, Reg
|Mem
, 0} },
178 {"neg", 1, 0xf6, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
179 {"not", 1, 0xf6, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
181 {"aaa", 0, 0x37, X
, 0, { 0, 0, 0} },
182 {"aas", 0, 0x3f, X
, 0, { 0, 0, 0} },
183 {"daa", 0, 0x27, X
, 0, { 0, 0, 0} },
184 {"das", 0, 0x2f, X
, 0, { 0, 0, 0} },
185 {"aad", 0, 0xd50a, X
, 0, { 0, 0, 0} },
186 {"aam", 0, 0xd40a, X
, 0, { 0, 0, 0} },
188 /* conversion insns */
189 /* conversion: intel naming */
190 {"cbw", 0, 0x98, X
, Data16
, { 0, 0, 0} },
191 {"cwd", 0, 0x99, X
, Data16
, { 0, 0, 0} },
192 {"cwde", 0, 0x98, X
, Data32
, { 0, 0, 0} },
193 {"cdq", 0, 0x99, X
, Data32
, { 0, 0, 0} },
195 {"cbtw", 0, 0x98, X
, Data16
, { 0, 0, 0} },
196 {"cwtl", 0, 0x98, X
, Data32
, { 0, 0, 0} },
197 {"cwtd", 0, 0x99, X
, Data16
, { 0, 0, 0} },
198 {"cltd", 0, 0x99, X
, Data32
, { 0, 0, 0} },
200 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
201 expanding 64-bit multiplies, and *cannot* be selected to accomplish
202 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
203 These multiplies can only be selected with single operand forms. */
204 {"mul", 1, 0xf6, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
205 {"imul", 1, 0xf6, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
206 {"imul", 2, 0x0faf, X
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
207 {"imul", 3, 0x6b, X
, Modrm
|ReverseRegRegmem
, { Imm8S
, WordReg
|Mem
, WordReg
} },
208 {"imul", 3, 0x69, X
, Modrm
|ReverseRegRegmem
, { Imm16
|Imm32
, WordReg
|Mem
, WordReg
} },
209 /* imul with 2 operands mimics imul with 3 by putting the register in
210 both i.rm.reg & i.rm.regmem fields. regKludge enables this
212 {"imul", 2, 0x6b, X
, Modrm
|regKludge
, { Imm8S
, WordReg
, 0} },
213 {"imul", 2, 0x69, X
, Modrm
|regKludge
, { Imm16
|Imm32
, WordReg
, 0} },
215 {"div", 1, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, 0, 0} },
216 {"div", 2, 0xf6, 6, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
217 {"idiv", 1, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
218 {"idiv", 2, 0xf6, 7, W
|Modrm
, { Reg
|Mem
, Acc
, 0} },
220 {"rol", 2, 0xd0, 0, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
221 {"rol", 2, 0xc0, 0, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
222 {"rol", 2, 0xd2, 0, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
223 {"rol", 1, 0xd0, 0, W
|Modrm
, { Reg
|Mem
, 0, 0} },
225 {"ror", 2, 0xd0, 1, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
226 {"ror", 2, 0xc0, 1, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
227 {"ror", 2, 0xd2, 1, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
228 {"ror", 1, 0xd0, 1, W
|Modrm
, { Reg
|Mem
, 0, 0} },
230 {"rcl", 2, 0xd0, 2, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
231 {"rcl", 2, 0xc0, 2, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
232 {"rcl", 2, 0xd2, 2, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
233 {"rcl", 1, 0xd0, 2, W
|Modrm
, { Reg
|Mem
, 0, 0} },
235 {"rcr", 2, 0xd0, 3, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
236 {"rcr", 2, 0xc0, 3, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
237 {"rcr", 2, 0xd2, 3, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
238 {"rcr", 1, 0xd0, 3, W
|Modrm
, { Reg
|Mem
, 0, 0} },
240 {"sal", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
241 {"sal", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
242 {"sal", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
243 {"sal", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
244 {"shl", 2, 0xd0, 4, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
245 {"shl", 2, 0xc0, 4, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
246 {"shl", 2, 0xd2, 4, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
247 {"shl", 1, 0xd0, 4, W
|Modrm
, { Reg
|Mem
, 0, 0} },
249 {"shld", 3, 0x0fa4, X
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
250 {"shld", 3, 0x0fa5, X
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
251 {"shld", 2, 0x0fa5, X
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
253 {"shr", 2, 0xd0, 5, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
254 {"shr", 2, 0xc0, 5, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
255 {"shr", 2, 0xd2, 5, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
256 {"shr", 1, 0xd0, 5, W
|Modrm
, { Reg
|Mem
, 0, 0} },
258 {"shrd", 3, 0x0fac, X
, Modrm
, { Imm8
, WordReg
, WordReg
|Mem
} },
259 {"shrd", 3, 0x0fad, X
, Modrm
, { ShiftCount
, WordReg
, WordReg
|Mem
} },
260 {"shrd", 2, 0x0fad, X
, Modrm
, { WordReg
, WordReg
|Mem
, 0} },
262 {"sar", 2, 0xd0, 7, W
|Modrm
, { Imm1
, Reg
|Mem
, 0} },
263 {"sar", 2, 0xc0, 7, W
|Modrm
, { Imm8
, Reg
|Mem
, 0} },
264 {"sar", 2, 0xd2, 7, W
|Modrm
, { ShiftCount
, Reg
|Mem
, 0} },
265 {"sar", 1, 0xd0, 7, W
|Modrm
, { Reg
|Mem
, 0, 0} },
267 /* control transfer instructions */
268 #define CALL_PC_RELATIVE 0xe8
269 {"call", 1, 0xe8, X
, JumpDword
, { Disp32
, 0, 0} },
270 {"call", 1, 0xff, 2, Modrm
|Data32
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
271 {"callw", 1, 0xff, 2, Modrm
|Data16
, { Reg
|Mem
|JumpAbsolute
, 0, 0} },
272 #define CALL_FAR_IMMEDIATE 0x9a
273 {"lcall", 2, 0x9a, X
, JumpInterSegment
, { Imm16
, Imm32
, 0} },
274 {"lcall", 1, 0xff, 3, Modrm
|Data32
, { Mem
, 0, 0} },
275 {"lcallw", 1, 0xff, 3, Modrm
|Data16
, { Mem
, 0, 0} },
277 #define JUMP_PC_RELATIVE 0xeb
278 {"jmp", 1, 0xeb, X
, Jump
, { Disp
, 0, 0} },
279 {"jmp", 1, 0xff, 4, Modrm
, { Reg32
|Mem
|JumpAbsolute
, 0, 0} },
280 #define JUMP_FAR_IMMEDIATE 0xea
281 {"ljmp", 2, 0xea, X
, JumpInterSegment
, { Imm16
, Imm32
, 0} },
282 {"ljmp", 1, 0xff, 5, Modrm
|Data32
, { Mem
, 0, 0} },
284 {"ret", 0, 0xc3, X
, Data32
, { 0, 0, 0} },
285 {"ret", 1, 0xc2, X
, Data32
, { Imm16
, 0, 0} },
286 {"retw", 0, 0xc3, X
, Data16
, { 0, 0, 0} },
287 {"retw", 1, 0xc2, X
, Data16
, { Imm16
, 0, 0} },
288 {"lret", 0, 0xcb, X
, Data32
, { 0, 0, 0} },
289 {"lret", 1, 0xca, X
, Data32
, { Imm16
, 0, 0} },
290 {"lretw", 0, 0xcb, X
, Data16
, { 0, 0, 0} },
291 {"lretw", 1, 0xca, X
, Data16
, { Imm16
, 0, 0} },
292 {"enter", 2, 0xc8, X
, Data32
, { Imm16
, Imm8
, 0} },
293 {"leave", 0, 0xc9, X
, Data32
, { 0, 0, 0} },
294 {"enterw", 2, 0xc8, X
, Data16
, { Imm16
, Imm8
, 0} },
295 {"leavew", 0, 0xc9, X
, Data16
, { 0, 0, 0} },
297 /* conditional jumps */
298 {"jo", 1, 0x70, X
, Jump
, { Disp
, 0, 0} },
300 {"jno", 1, 0x71, X
, Jump
, { Disp
, 0, 0} },
302 {"jb", 1, 0x72, X
, Jump
, { Disp
, 0, 0} },
303 {"jc", 1, 0x72, X
, Jump
, { Disp
, 0, 0} },
304 {"jnae", 1, 0x72, X
, Jump
, { Disp
, 0, 0} },
306 {"jnb", 1, 0x73, X
, Jump
, { Disp
, 0, 0} },
307 {"jnc", 1, 0x73, X
, Jump
, { Disp
, 0, 0} },
308 {"jae", 1, 0x73, X
, Jump
, { Disp
, 0, 0} },
310 {"je", 1, 0x74, X
, Jump
, { Disp
, 0, 0} },
311 {"jz", 1, 0x74, X
, Jump
, { Disp
, 0, 0} },
313 {"jne", 1, 0x75, X
, Jump
, { Disp
, 0, 0} },
314 {"jnz", 1, 0x75, X
, Jump
, { Disp
, 0, 0} },
316 {"jbe", 1, 0x76, X
, Jump
, { Disp
, 0, 0} },
317 {"jna", 1, 0x76, X
, Jump
, { Disp
, 0, 0} },
319 {"jnbe", 1, 0x77, X
, Jump
, { Disp
, 0, 0} },
320 {"ja", 1, 0x77, X
, Jump
, { Disp
, 0, 0} },
322 {"js", 1, 0x78, X
, Jump
, { Disp
, 0, 0} },
324 {"jns", 1, 0x79, X
, Jump
, { Disp
, 0, 0} },
326 {"jp", 1, 0x7a, X
, Jump
, { Disp
, 0, 0} },
327 {"jpe", 1, 0x7a, X
, Jump
, { Disp
, 0, 0} },
329 {"jnp", 1, 0x7b, X
, Jump
, { Disp
, 0, 0} },
330 {"jpo", 1, 0x7b, X
, Jump
, { Disp
, 0, 0} },
332 {"jl", 1, 0x7c, X
, Jump
, { Disp
, 0, 0} },
333 {"jnge", 1, 0x7c, X
, Jump
, { Disp
, 0, 0} },
335 {"jnl", 1, 0x7d, X
, Jump
, { Disp
, 0, 0} },
336 {"jge", 1, 0x7d, X
, Jump
, { Disp
, 0, 0} },
338 {"jle", 1, 0x7e, X
, Jump
, { Disp
, 0, 0} },
339 {"jng", 1, 0x7e, X
, Jump
, { Disp
, 0, 0} },
341 {"jnle", 1, 0x7f, X
, Jump
, { Disp
, 0, 0} },
342 {"jg", 1, 0x7f, X
, Jump
, { Disp
, 0, 0} },
344 #define IS_JUMP_ON_CX_ZERO(o) \
347 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
348 {"jcxz", 1, 0xe3, X
, JumpByte
|Data16
, { Disp
, 0, 0} },
349 {"jecxz", 1, 0xe3, X
, JumpByte
|Data32
, { Disp
, 0, 0} },
351 #define IS_LOOP_ECX_TIMES(o) \
352 (o == 0xe2 || o == 0xe1 || o == 0xe0)
354 {"loop", 1, 0xe2, X
, JumpByte
, { Disp
, 0, 0} },
356 {"loopz", 1, 0xe1, X
, JumpByte
, { Disp
, 0, 0} },
357 {"loope", 1, 0xe1, X
, JumpByte
, { Disp
, 0, 0} },
359 {"loopnz", 1, 0xe0, X
, JumpByte
, { Disp
, 0, 0} },
360 {"loopne", 1, 0xe0, X
, JumpByte
, { Disp
, 0, 0} },
362 /* set byte on flag instructions */
363 {"seto", 1, 0x0f90, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
365 {"setno", 1, 0x0f91, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
367 {"setb", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
368 {"setc", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
369 {"setnae", 1, 0x0f92, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
371 {"setnb", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
372 {"setnc", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
373 {"setae", 1, 0x0f93, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
375 {"sete", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
376 {"setz", 1, 0x0f94, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
378 {"setne", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
379 {"setnz", 1, 0x0f95, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
381 {"setbe", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
382 {"setna", 1, 0x0f96, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
384 {"setnbe", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
385 {"seta", 1, 0x0f97, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
387 {"sets", 1, 0x0f98, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
389 {"setns", 1, 0x0f99, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
391 {"setp", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
392 {"setpe", 1, 0x0f9a, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
394 {"setnp", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
395 {"setpo", 1, 0x0f9b, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
397 {"setl", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
398 {"setnge", 1, 0x0f9c, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
400 {"setnl", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
401 {"setge", 1, 0x0f9d, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
403 {"setle", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
404 {"setng", 1, 0x0f9e, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
406 {"setnle", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
407 {"setg", 1, 0x0f9f, 0, Modrm
, { Reg8
|Mem
, 0, 0} },
409 /* string manipulation */
410 {"cmps", 0, 0xa6, X
, W
|IsString
, { 0, 0, 0} },
411 {"cmps", 2, 0xa6, X
, W
|IsString
, { Mem
|EsSeg
, Mem
, 0} },
412 {"scmp", 0, 0xa6, X
, W
|IsString
, { 0, 0, 0} },
413 {"scmp", 2, 0xa6, X
, W
|IsString
, { Mem
|EsSeg
, Mem
, 0} },
414 {"ins", 0, 0x6c, X
, W
|IsString
, { 0, 0, 0} },
415 {"ins", 2, 0x6c, X
, W
|IsString
, { InOutPortReg
, Mem
|EsSeg
, 0} },
416 {"outs", 0, 0x6e, X
, W
|IsString
, { 0, 0, 0} },
417 {"outs", 2, 0x6e, X
, W
|IsString
, { Mem
, InOutPortReg
, 0} },
418 {"lods", 0, 0xac, X
, W
|IsString
, { 0, 0, 0} },
419 {"lods", 1, 0xac, X
, W
|IsString
, { Mem
, 0, 0} },
420 {"lods", 2, 0xac, X
, W
|IsString
, { Mem
, Acc
, 0} },
421 {"slod", 0, 0xac, X
, W
|IsString
, { 0, 0, 0} },
422 {"slod", 1, 0xac, X
, W
|IsString
, { Mem
, 0, 0} },
423 {"slod", 2, 0xac, X
, W
|IsString
, { Mem
, Acc
, 0} },
424 {"movs", 0, 0xa4, X
, W
|IsString
, { 0, 0, 0} },
425 {"movs", 2, 0xa4, X
, W
|IsString
, { Mem
, Mem
|EsSeg
, 0} },
426 {"smov", 0, 0xa4, X
, W
|IsString
, { 0, 0, 0} },
427 {"smov", 2, 0xa4, X
, W
|IsString
, { Mem
, Mem
|EsSeg
, 0} },
428 {"scas", 0, 0xae, X
, W
|IsString
, { 0, 0, 0} },
429 {"scas", 1, 0xae, X
, W
|IsString
, { Mem
|EsSeg
, 0, 0} },
430 {"scas", 2, 0xae, X
, W
|IsString
, { Mem
|EsSeg
, Acc
, 0} },
431 {"ssca", 0, 0xae, X
, W
|IsString
, { 0, 0, 0} },
432 {"ssca", 1, 0xae, X
, W
|IsString
, { Mem
|EsSeg
, 0, 0} },
433 {"ssca", 2, 0xae, X
, W
|IsString
, { Mem
|EsSeg
, Acc
, 0} },
434 {"stos", 0, 0xaa, X
, W
|IsString
, { 0, 0, 0} },
435 {"stos", 1, 0xaa, X
, W
|IsString
, { Mem
|EsSeg
, 0, 0} },
436 {"stos", 2, 0xaa, X
, W
|IsString
, { Acc
, Mem
|EsSeg
, 0} },
437 {"ssto", 0, 0xaa, X
, W
|IsString
, { 0, 0, 0} },
438 {"ssto", 1, 0xaa, X
, W
|IsString
, { Mem
|EsSeg
, 0, 0} },
439 {"ssto", 2, 0xaa, X
, W
|IsString
, { Acc
, Mem
|EsSeg
, 0} },
440 {"xlat", 0, 0xd7, X
, IsString
, { 0, 0, 0} },
441 {"xlat", 1, 0xd7, X
, IsString
, { Mem
, 0, 0} },
443 /* bit manipulation */
444 {"bsf", 2, 0x0fbc, X
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
445 {"bsr", 2, 0x0fbd, X
, Modrm
|ReverseRegRegmem
, { Reg
|Mem
, Reg
, 0} },
446 {"bt", 2, 0x0fa3, X
, Modrm
, { Reg
, Reg
|Mem
, 0} },
447 {"bt", 2, 0x0fba, 4, Modrm
, { Imm8
, Reg
|Mem
, 0} },
448 {"btc", 2, 0x0fbb, X
, Modrm
, { Reg
, Reg
|Mem
, 0} },
449 {"btc", 2, 0x0fba, 7, Modrm
, { Imm8
, Reg
|Mem
, 0} },
450 {"btr", 2, 0x0fb3, X
, Modrm
, { Reg
, Reg
|Mem
, 0} },
451 {"btr", 2, 0x0fba, 6, Modrm
, { Imm8
, Reg
|Mem
, 0} },
452 {"bts", 2, 0x0fab, X
, Modrm
, { Reg
, Reg
|Mem
, 0} },
453 {"bts", 2, 0x0fba, 5, Modrm
, { Imm8
, Reg
|Mem
, 0} },
455 /* interrupts & op. sys insns */
456 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
458 #define INT_OPCODE 0xcd
459 #define INT3_OPCODE 0xcc
460 {"int", 1, 0xcd, X
, 0, { Imm8
, 0, 0} },
461 {"int3", 0, 0xcc, X
, 0, { 0, 0, 0} },
462 {"into", 0, 0xce, X
, 0, { 0, 0, 0} },
463 {"iret", 0, 0xcf, X
, Data32
, { 0, 0, 0} },
464 {"iretw", 0, 0xcf, X
, Data16
, { 0, 0, 0} },
465 /* i386sl, i486sl, later 486, and Pentium */
466 {"rsm", 0, 0x0faa, X
, 0,{ 0, 0, 0} },
468 {"boundl", 2, 0x62, X
, Modrm
|Data32
, { Reg32
, Mem
, 0} },
469 {"boundw", 2, 0x62, X
, Modrm
|Data16
, { Reg16
, Mem
, 0} },
471 {"hlt", 0, 0xf4, X
, 0, { 0, 0, 0} },
472 {"wait", 0, 0x9b, X
, 0, { 0, 0, 0} },
473 /* nop is actually 'xchgl %eax, %eax' */
474 {"nop", 0, 0x90, X
, 0, { 0, 0, 0} },
476 /* protection control */
477 {"arpl", 2, 0x63, X
, Modrm
, { Reg16
, Reg16
|Mem
, 0} },
478 {"lar", 2, 0x0f02, X
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
479 {"lgdt", 1, 0x0f01, 2, Modrm
, { Mem
, 0, 0} },
480 {"lidt", 1, 0x0f01, 3, Modrm
, { Mem
, 0, 0} },
481 {"lldt", 1, 0x0f00, 2, Modrm
, { WordReg
|Mem
, 0, 0} },
482 {"lmsw", 1, 0x0f01, 6, Modrm
, { WordReg
|Mem
, 0, 0} },
483 {"lsl", 2, 0x0f03, X
, Modrm
|ReverseRegRegmem
, { WordReg
|Mem
, WordReg
, 0} },
484 {"ltr", 1, 0x0f00, 3, Modrm
, { WordReg
|Mem
, 0, 0} },
486 {"sgdt", 1, 0x0f01, 0, Modrm
, { Mem
, 0, 0} },
487 {"sidt", 1, 0x0f01, 1, Modrm
, { Mem
, 0, 0} },
488 {"sldt", 1, 0x0f00, 0, Modrm
, { WordReg
|Mem
, 0, 0} },
489 {"smsw", 1, 0x0f01, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
490 {"str", 1, 0x0f00, 1, Modrm
, { Reg16
|Mem
, 0, 0} },
492 {"verr", 1, 0x0f00, 4, Modrm
, { WordReg
|Mem
, 0, 0} },
493 {"verw", 1, 0x0f00, 5, Modrm
, { WordReg
|Mem
, 0, 0} },
495 /* floating point instructions */
498 {"fld", 1, 0xd9c0, X
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
499 {"flds", 1, 0xd9, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem float */
500 {"fldl", 1, 0xdd, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem double */
501 {"fldl", 1, 0xd9c0, X
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
502 {"fild", 1, 0xdf, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem word (16) */
503 {"fildl", 1, 0xdb, 0, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem dword (32) */
504 {"fildq",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
505 {"fildll",1, 0xdf, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem qword (64) */
506 {"fldt", 1, 0xdb, 5, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem efloat */
507 {"fbld", 1, 0xdf, 4, Modrm
, { Mem
, 0, 0} }, /* %st0 <-- mem bcd */
510 {"fst", 1, 0xddd0, X
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
511 {"fsts", 1, 0xd9, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
512 {"fstl", 1, 0xdd, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
513 {"fstl", 1, 0xddd0, X
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
514 {"fist", 1, 0xdf, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
515 {"fistl", 1, 0xdb, 2, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
517 /* store (with pop) */
518 {"fstp", 1, 0xddd8, X
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
519 {"fstps", 1, 0xd9, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem float */
520 {"fstpl", 1, 0xdd, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem double */
521 {"fstpl", 1, 0xddd8, X
, ShortForm
, { FloatReg
, 0, 0} }, /* register */
522 {"fistp", 1, 0xdf, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem word (16) */
523 {"fistpl",1, 0xdb, 3, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem dword (32) */
524 {"fistpq",1, 0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
525 {"fistpll",1,0xdf, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem qword (64) */
526 {"fstpt", 1, 0xdb, 7, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem efloat */
527 {"fbstp", 1, 0xdf, 6, Modrm
, { Mem
, 0, 0} }, /* %st0 --> mem bcd */
529 /* exchange %st<n> with %st0 */
530 {"fxch", 1, 0xd9c8, X
, ShortForm
, { FloatReg
, 0, 0} },
531 {"fxch", 0, 0xd9c9, X
, 0, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
533 /* comparison (without pop) */
534 {"fcom", 1, 0xd8d0, X
, ShortForm
, { FloatReg
, 0, 0} },
535 {"fcoms", 1, 0xd8, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
536 {"ficoml", 1, 0xda, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
537 {"fcoml", 1, 0xdc, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
538 {"fcoml", 1, 0xd8d0, X
, ShortForm
, { FloatReg
, 0, 0} },
539 {"ficoms", 1, 0xde, 2, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
541 /* comparison (with pop) */
542 {"fcomp", 1, 0xd8d8, X
, ShortForm
, { FloatReg
, 0, 0} },
543 {"fcomp", 0, 0xd8d9, X
, 0, {0, 0, 0} }, /* fcomp %st, %st(1) */
544 {"fcomps", 1, 0xd8, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem float */
545 {"ficompl", 1, 0xda, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem dword */
546 {"fcompl", 1, 0xdc, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem double */
547 {"fcompl", 1, 0xd8d8, X
, ShortForm
, { FloatReg
, 0, 0} },
548 {"ficomps", 1, 0xde, 3, Modrm
, { Mem
, 0, 0} }, /* compare %st0, mem word */
549 {"fcompp", 0, 0xded9, X
, 0, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
551 /* unordered comparison (with pop) */
552 {"fucom", 1, 0xdde0, X
, ShortForm
, { FloatReg
, 0, 0} },
553 {"fucomp", 1, 0xdde8, X
, ShortForm
, { FloatReg
, 0, 0} },
554 {"fucompp", 0, 0xdae9, X
, 0, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
556 {"ftst", 0, 0xd9e4, X
, 0, { 0, 0, 0} }, /* test %st0 */
557 {"fxam", 0, 0xd9e5, X
, 0, { 0, 0, 0} }, /* examine %st0 */
559 /* load constants into %st0 */
560 {"fld1", 0, 0xd9e8, X
, 0, { 0, 0, 0} }, /* %st0 <-- 1.0 */
561 {"fldl2t", 0, 0xd9e9, X
, 0, { 0, 0, 0} }, /* %st0 <-- log2(10) */
562 {"fldl2e", 0, 0xd9ea, X
, 0, { 0, 0, 0} }, /* %st0 <-- log2(e) */
563 {"fldpi", 0, 0xd9eb, X
, 0, { 0, 0, 0} }, /* %st0 <-- pi */
564 {"fldlg2", 0, 0xd9ec, X
, 0, { 0, 0, 0} }, /* %st0 <-- log10(2) */
565 {"fldln2", 0, 0xd9ed, X
, 0, { 0, 0, 0} }, /* %st0 <-- ln(2) */
566 {"fldz", 0, 0xd9ee, X
, 0, { 0, 0, 0} }, /* %st0 <-- 0.0 */
571 {"fadd", 1, 0xd8c0, X
, ShortForm
, { FloatReg
, 0, 0} },
572 {"fadd", 2, 0xd8c0, X
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
573 {"fadd", 0, 0xdcc1, X
, 0, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
574 {"faddp", 1, 0xdec0, X
, ShortForm
, { FloatReg
, 0, 0} },
575 {"faddp", 2, 0xdec0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
576 {"faddp", 2, 0xdec0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
577 {"faddp", 0, 0xdec1, X
, 0, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
578 {"fadds", 1, 0xd8, 0, Modrm
, { Mem
, 0, 0} },
579 {"fiaddl", 1, 0xda, 0, Modrm
, { Mem
, 0, 0} },
580 {"faddl", 1, 0xdc, 0, Modrm
, { Mem
, 0, 0} },
581 {"fiadds", 1, 0xde, 0, Modrm
, { Mem
, 0, 0} },
584 /* Note: intel has decided that certain of these operations are reversed
585 in assembler syntax. */
586 {"fsub", 1, 0xd8e0, X
, ShortForm
, { FloatReg
, 0, 0} },
587 {"fsub", 2, 0xd8e0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
588 #ifdef NON_BROKEN_OPCODES
589 {"fsub", 2, 0xdce8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
591 {"fsub", 2, 0xdce0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
593 {"fsub", 0, 0xdce1, X
, 0, { 0, 0, 0} },
594 {"fsubp", 1, 0xdee8, X
, ShortForm
, { FloatReg
, 0, 0} },
595 {"fsubp", 2, 0xdee8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
596 #ifdef NON_BROKEN_OPCODES
597 {"fsubp", 2, 0xdee8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
598 {"fsubp", 0, 0xdee9, X
, 0, { 0, 0, 0} },
600 {"fsubp", 2, 0xdee0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
601 {"fsubp", 0, 0xdee1, X
, 0, { 0, 0, 0} },
603 {"fsubs", 1, 0xd8, 4, Modrm
, { Mem
, 0, 0} },
604 {"fisubl", 1, 0xda, 4, Modrm
, { Mem
, 0, 0} },
605 {"fsubl", 1, 0xdc, 4, Modrm
, { Mem
, 0, 0} },
606 {"fisubs", 1, 0xde, 4, Modrm
, { Mem
, 0, 0} },
609 {"fsubr", 1, 0xd8e8, X
, ShortForm
, { FloatReg
, 0, 0} },
610 {"fsubr", 2, 0xd8e8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
611 #ifdef NON_BROKEN_OPCODES
612 {"fsubr", 2, 0xdce0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
614 {"fsubr", 2, 0xdce8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
616 {"fsubr", 0, 0xdce9, X
, 0, { 0, 0, 0} },
617 {"fsubrp", 1, 0xdee0, X
, ShortForm
, { FloatReg
, 0, 0} },
618 {"fsubrp", 2, 0xdee0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
619 #ifdef NON_BROKEN_OPCODES
620 {"fsubrp", 2, 0xdee0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
621 {"fsubrp", 0, 0xdee1, X
, 0, { 0, 0, 0} },
623 {"fsubrp", 2, 0xdee8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
624 {"fsubrp", 0, 0xdee9, X
, 0, { 0, 0, 0} },
626 {"fsubrs", 1, 0xd8, 5, Modrm
, { Mem
, 0, 0} },
627 {"fisubrl", 1, 0xda, 5, Modrm
, { Mem
, 0, 0} },
628 {"fsubrl", 1, 0xdc, 5, Modrm
, { Mem
, 0, 0} },
629 {"fisubrs", 1, 0xde, 5, Modrm
, { Mem
, 0, 0} },
632 {"fmul", 1, 0xd8c8, X
, ShortForm
, { FloatReg
, 0, 0} },
633 {"fmul", 2, 0xd8c8, X
, ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
634 {"fmul", 0, 0xdcc9, X
, 0, { 0, 0, 0} },
635 {"fmulp", 1, 0xdec8, X
, ShortForm
, { FloatReg
, 0, 0} },
636 {"fmulp", 2, 0xdec8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
637 {"fmulp", 2, 0xdec8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
638 {"fmulp", 0, 0xdec9, X
, 0, { 0, 0, 0} },
639 {"fmuls", 1, 0xd8, 1, Modrm
, { Mem
, 0, 0} },
640 {"fimull", 1, 0xda, 1, Modrm
, { Mem
, 0, 0} },
641 {"fmull", 1, 0xdc, 1, Modrm
, { Mem
, 0, 0} },
642 {"fimuls", 1, 0xde, 1, Modrm
, { Mem
, 0, 0} },
645 /* Note: intel has decided that certain of these operations are reversed
646 in assembler syntax. */
647 {"fdiv", 1, 0xd8f0, X
, ShortForm
, { FloatReg
, 0, 0} },
648 {"fdiv", 2, 0xd8f0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
649 #ifdef NON_BROKEN_OPCODES
650 {"fdiv", 2, 0xdcf8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
652 {"fdiv", 2, 0xdcf0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
654 {"fdiv", 0, 0xdcf1, X
, 0, { 0, 0, 0} },
655 {"fdivp", 1, 0xdef8, X
, ShortForm
, { FloatReg
, 0, 0} },
656 {"fdivp", 2, 0xdef8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
657 #ifdef NON_BROKEN_OPCODES
658 {"fdivp", 2, 0xdef8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
659 {"fdivp", 0, 0xdef9, X
, 0, { 0, 0, 0} },
661 {"fdivp", 2, 0xdef0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
662 {"fdivp", 0, 0xdef1, X
, 0, { 0, 0, 0} },
664 {"fdivs", 1, 0xd8, 6, Modrm
, { Mem
, 0, 0} },
665 {"fidivl", 1, 0xda, 6, Modrm
, { Mem
, 0, 0} },
666 {"fdivl", 1, 0xdc, 6, Modrm
, { Mem
, 0, 0} },
667 {"fidivs", 1, 0xde, 6, Modrm
, { Mem
, 0, 0} },
670 {"fdivr", 1, 0xd8f8, X
, ShortForm
, { FloatReg
, 0, 0} },
671 {"fdivr", 2, 0xd8f8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
672 #ifdef NON_BROKEN_OPCODES
673 {"fdivr", 2, 0xdcf0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
675 {"fdivr", 2, 0xdcf8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
677 {"fdivr", 0, 0xdcf9, X
, 0, { 0, 0, 0} },
678 {"fdivrp", 1, 0xdef0, X
, ShortForm
, { FloatReg
, 0, 0} },
679 {"fdivrp", 2, 0xdef0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
680 #ifdef NON_BROKEN_OPCODES
681 {"fdivrp", 2, 0xdef0, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
682 {"fdivrp", 0, 0xdef1, X
, 0, { 0, 0, 0} },
684 {"fdivrp", 2, 0xdef8, X
, ShortForm
, { FloatAcc
, FloatReg
, 0} },
685 {"fdivrp", 0, 0xdef9, X
, 0, { 0, 0, 0} },
687 {"fdivrs", 1, 0xd8, 7, Modrm
, { Mem
, 0, 0} },
688 {"fidivrl", 1, 0xda, 7, Modrm
, { Mem
, 0, 0} },
689 {"fdivrl", 1, 0xdc, 7, Modrm
, { Mem
, 0, 0} },
690 {"fidivrs", 1, 0xde, 7, Modrm
, { Mem
, 0, 0} },
692 {"f2xm1", 0, 0xd9f0, X
, 0, { 0, 0, 0} },
693 {"fyl2x", 0, 0xd9f1, X
, 0, { 0, 0, 0} },
694 {"fptan", 0, 0xd9f2, X
, 0, { 0, 0, 0} },
695 {"fpatan", 0, 0xd9f3, X
, 0, { 0, 0, 0} },
696 {"fxtract", 0, 0xd9f4, X
, 0, { 0, 0, 0} },
697 {"fprem1", 0, 0xd9f5, X
, 0, { 0, 0, 0} },
698 {"fdecstp", 0, 0xd9f6, X
, 0, { 0, 0, 0} },
699 {"fincstp", 0, 0xd9f7, X
, 0, { 0, 0, 0} },
700 {"fprem", 0, 0xd9f8, X
, 0, { 0, 0, 0} },
701 {"fyl2xp1", 0, 0xd9f9, X
, 0, { 0, 0, 0} },
702 {"fsqrt", 0, 0xd9fa, X
, 0, { 0, 0, 0} },
703 {"fsincos", 0, 0xd9fb, X
, 0, { 0, 0, 0} },
704 {"frndint", 0, 0xd9fc, X
, 0, { 0, 0, 0} },
705 {"fscale", 0, 0xd9fd, X
, 0, { 0, 0, 0} },
706 {"fsin", 0, 0xd9fe, X
, 0, { 0, 0, 0} },
707 {"fcos", 0, 0xd9ff, X
, 0, { 0, 0, 0} },
709 {"fchs", 0, 0xd9e0, X
, 0, { 0, 0, 0} },
710 {"fabs", 0, 0xd9e1, X
, 0, { 0, 0, 0} },
712 /* processor control */
713 {"fninit", 0, 0xdbe3, X
, 0, { 0, 0, 0} },
714 {"finit", 0, 0xdbe3, X
, FWait
, { 0, 0, 0} },
715 {"fldcw", 1, 0xd9, 5, Modrm
, { Mem
, 0, 0} },
716 {"fnstcw", 1, 0xd9, 7, Modrm
, { Mem
, 0, 0} },
717 {"fstcw", 1, 0xd9, 7, FWait
|Modrm
, { Mem
, 0, 0} },
718 {"fnstsw", 1, 0xdfe0, X
, 0, { Acc
, 0, 0} },
719 {"fnstsw", 1, 0xdd, 7, Modrm
, { Mem
, 0, 0} },
720 {"fnstsw", 0, 0xdfe0, X
, 0, { 0, 0, 0} },
721 {"fstsw", 1, 0xdfe0, X
, FWait
, { Acc
, 0, 0} },
722 {"fstsw", 1, 0xdd, 7, FWait
|Modrm
, { Mem
, 0, 0} },
723 {"fstsw", 0, 0xdfe0, X
, FWait
, { 0, 0, 0} },
724 {"fnclex", 0, 0xdbe2, X
, 0, { 0, 0, 0} },
725 {"fclex", 0, 0xdbe2, X
, FWait
, { 0, 0, 0} },
726 {"fnstenv",1, 0xd9, 6, Modrm
, { Mem
, 0, 0} },
727 {"fstenv", 1, 0xd9, 6, FWait
|Modrm
, { Mem
, 0, 0} },
728 {"fldenv", 1, 0xd9, 4, Modrm
, { Mem
, 0, 0} },
729 {"fnsave", 1, 0xdd, 6, Modrm
, { Mem
, 0, 0} },
730 {"fsave", 1, 0xdd, 6, FWait
|Modrm
, { Mem
, 0, 0} },
731 {"frstor", 1, 0xdd, 4, Modrm
, { Mem
, 0, 0} },
732 /* Short forms of fldenv, fstenv use data size prefix. (At least I
733 think so. The PentPro prog ref I have says address size in one
734 place, operand size elsewhere). FIXME: Are these the right names? */
735 {"fnstenvs",1, 0xd9, 6, Modrm
|Data16
, { Mem
, 0, 0} },
736 {"fstenvs", 1, 0xd9, 6, FWait
|Modrm
|Data16
, { Mem
, 0, 0} },
737 {"fldenvs", 1, 0xd9, 4, Modrm
|Data16
, { Mem
, 0, 0} },
739 {"ffree", 1, 0xddc0, X
, ShortForm
, { FloatReg
, 0, 0} },
740 /* P6:free st(i), pop st */
741 {"ffreep", 1, 0xdfc0, X
, ShortForm
, { FloatReg
, 0, 0} },
742 {"fnop", 0, 0xd9d0, X
, 0, { 0, 0, 0} },
743 #define FWAIT_OPCODE 0x9b
744 {"fwait", 0, 0x9b, X
, 0, { 0, 0, 0} },
747 opcode prefixes; we allow them as seperate insns too
748 (see prefix table below)
750 {"aword", 0, 0x67, X
, 0, { 0, 0, 0} },
751 {"addr16", 0, 0x67, X
, 0, { 0, 0, 0} },
752 {"word", 0, 0x66, X
, 0, { 0, 0, 0} },
753 {"data16", 0, 0x66, X
, 0, { 0, 0, 0} },
754 {"lock", 0, 0xf0, X
, 0, { 0, 0, 0} },
755 {"cs", 0, 0x2e, X
, 0, { 0, 0, 0} },
756 {"ds", 0, 0x3e, X
, 0, { 0, 0, 0} },
757 {"es", 0, 0x26, X
, 0, { 0, 0, 0} },
758 {"fs", 0, 0x64, X
, 0, { 0, 0, 0} },
759 {"gs", 0, 0x65, X
, 0, { 0, 0, 0} },
760 {"ss", 0, 0x36, X
, 0, { 0, 0, 0} },
761 {"rep", 0, 0xf3, X
, 0, { 0, 0, 0} },
762 {"repe", 0, 0xf3, X
, 0, { 0, 0, 0} },
763 {"repz", 0, 0xf3, X
, 0, { 0, 0, 0} },
764 {"repne", 0, 0xf2, X
, 0, { 0, 0, 0} },
765 {"repnz", 0, 0xf2, X
, 0, { 0, 0, 0} },
769 {"bswap", 1, 0x0fc8, X
, ShortForm
, { Reg32
,0,0 } },
770 {"xadd", 2, 0x0fc0, X
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
771 {"cmpxchg", 2, 0x0fb0, X
, W
|Modrm
, { Reg
, Reg
|Mem
, 0 } },
772 {"invd", 0, 0x0f08, X
, 0, { 0, 0, 0} },
773 {"wbinvd", 0, 0x0f09, X
, 0, { 0, 0, 0} },
774 {"invlpg", 1, 0x0f01, 7, Modrm
, { Mem
, 0, 0} },
776 /* 586 and late 486 extensions */
777 {"cpuid", 0, 0x0fa2, X
, 0, { 0, 0, 0} },
779 /* Pentium extensions */
780 {"wrmsr", 0, 0x0f30, X
, 0, { 0, 0, 0} },
781 {"rdtsc", 0, 0x0f31, X
, 0, { 0, 0, 0} },
782 {"rdmsr", 0, 0x0f32, X
, 0, { 0, 0, 0} },
783 {"cmpxchg8b", 1, 0x0fc7, 1, Modrm
, { Mem
, 0, 0} },
785 /* Pentium Pro extensions */
786 {"rdpmc", 0, 0x0f33, X
, 0, { 0, 0, 0} },
788 {"ud2", 0, 0x0f0b, X
, 0, {0, 0, 0} }, /* official undefined instr. */
790 {"cmovo", 2, 0x0f40, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
791 {"cmovno", 2, 0x0f41, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
792 {"cmovb", 2, 0x0f42, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
793 {"cmovae", 2, 0x0f43, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
794 {"cmove", 2, 0x0f44, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
795 {"cmovne", 2, 0x0f45, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
796 {"cmovbe", 2, 0x0f46, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
797 {"cmova", 2, 0x0f47, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
798 {"cmovs", 2, 0x0f48, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
799 {"cmovns", 2, 0x0f49, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
800 {"cmovp", 2, 0x0f4a, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
801 {"cmovnp", 2, 0x0f4b, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
802 {"cmovl", 2, 0x0f4c, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
803 {"cmovge", 2, 0x0f4d, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
804 {"cmovle", 2, 0x0f4e, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
805 {"cmovg", 2, 0x0f4f, X
, Modrm
|ReverseRegRegmem
, { WordReg
|WordMem
, WordReg
, 0} },
807 {"fcmovb", 2, 0xdac0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
808 {"fcmove", 2, 0xdac8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
809 {"fcmovbe",2, 0xdad0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
810 {"fcmovu", 2, 0xdad8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
811 {"fcmovnb", 2, 0xdbc0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
812 {"fcmovne", 2, 0xdbc8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
813 {"fcmovnbe",2, 0xdbd0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
814 {"fcmovnu", 2, 0xdbd8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
816 {"fcomi", 2, 0xdbf0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
817 {"fucomi", 2, 0xdbe8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
818 {"fcomip", 2, 0xdff0, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
819 {"fucomip",2, 0xdfe8, X
, ShortForm
, { FloatReg
, FloatAcc
, 0} },
821 /* MMX instructions. */
823 {"emms", 0, 0x0f77, X
, 0, { 0, 0, 0 } },
824 {"movd", 2, 0x0f6e, X
, Modrm
, { Reg32
|WordMem
, RegMMX
, 0 } },
825 {"movd", 2, 0x0f7e, X
, Modrm
, { RegMMX
, Reg32
|WordMem
, 0 } },
826 {"movq", 2, 0x0f6f, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
827 {"movq", 2, 0x0f7f, X
, Modrm
, { RegMMX
, RegMMX
|WordMem
, 0 } },
828 {"packssdw", 2, 0x0f6b, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
829 {"packsswb", 2, 0x0f63, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
830 {"packuswb", 2, 0x0f67, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
831 {"paddb", 2, 0x0ffc, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
832 {"paddw", 2, 0x0ffd, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
833 {"paddd", 2, 0x0ffe, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
834 {"paddsb", 2, 0x0fec, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
835 {"paddsw", 2, 0x0fed, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
836 {"paddusb", 2, 0x0fdc, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
837 {"paddusw", 2, 0x0fdd, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
838 {"pand", 2, 0x0fdb, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
839 {"pandn", 2, 0x0fdf, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
840 {"pcmpeqb", 2, 0x0f74, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
841 {"pcmpeqw", 2, 0x0f75, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
842 {"pcmpeqd", 2, 0x0f76, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
843 {"pcmpgtb", 2, 0x0f64, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
844 {"pcmpgtw", 2, 0x0f65, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
845 {"pcmpgtd", 2, 0x0f66, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
846 {"pmaddwd", 2, 0x0ff5, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
847 {"pmulhw", 2, 0x0fe5, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
848 {"pmullw", 2, 0x0fd5, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
849 {"por", 2, 0x0feb, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
850 {"psllw", 2, 0x0ff1, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
851 {"psllw", 2, 0x0f71, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
852 {"pslld", 2, 0x0ff2, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
853 {"pslld", 2, 0x0f72, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
854 {"psllq", 2, 0x0ff3, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
855 {"psllq", 2, 0x0f73, 6, Modrm
, { Imm8
, RegMMX
, 0 } },
856 {"psraw", 2, 0x0fe1, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
857 {"psraw", 2, 0x0f71, 4, Modrm
, { Imm8
, RegMMX
, 0 } },
858 {"psrad", 2, 0x0fe2, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
859 {"psrad", 2, 0x0f72, 4, Modrm
, { Imm8
, RegMMX
, 0 } },
860 {"psrlw", 2, 0x0fd1, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
861 {"psrlw", 2, 0x0f71, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
862 {"psrld", 2, 0x0fd2, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
863 {"psrld", 2, 0x0f72, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
864 {"psrlq", 2, 0x0fd3, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
865 {"psrlq", 2, 0x0f73, 2, Modrm
, { Imm8
, RegMMX
, 0 } },
866 {"psubb", 2, 0x0ff8, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
867 {"psubw", 2, 0x0ff9, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
868 {"psubd", 2, 0x0ffa, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
869 {"psubsb", 2, 0x0fe8, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
870 {"psubsw", 2, 0x0fe9, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
871 {"psubusb", 2, 0x0fd8, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
872 {"psubusw", 2, 0x0fd9, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
873 {"punpckhbw", 2, 0x0f68, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
874 {"punpckhwd", 2, 0x0f69, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
875 {"punpckhdq", 2, 0x0f6a, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
876 {"punpcklbw", 2, 0x0f60, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
877 {"punpcklwd", 2, 0x0f61, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
878 {"punpckldq", 2, 0x0f62, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
879 {"pxor", 2, 0x0fef, X
, Modrm
, { RegMMX
|WordMem
, RegMMX
, 0 } },
881 {"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
885 static const template *const i386_optab_end
886 = i386_optab
+ sizeof (i386_optab
)/sizeof(i386_optab
[0]);
888 /* 386 register table */
890 static const reg_entry i386_regtab
[] = {
893 {"cl", Reg8
|ShiftCount
, 1},
901 {"ax", Reg16
|Acc
, 0},
903 {"dx", Reg16
|InOutPortReg
, 2},
910 {"eax", Reg32
|BaseIndex
|Acc
, 0},
911 {"ecx", Reg32
|BaseIndex
, 1},
912 {"edx", Reg32
|BaseIndex
, 2},
913 {"ebx", Reg32
|BaseIndex
, 3},
914 {"esp", Reg32
|BaseIndex
, 4},
915 {"ebp", Reg32
|BaseIndex
, 5},
916 {"esi", Reg32
|BaseIndex
, 6},
917 {"edi", Reg32
|BaseIndex
, 7},
918 /* segment registers */
925 /* control registers */
930 /* debug registers */
949 /* float registers */
950 {"st(0)", FloatReg
|FloatAcc
, 0},
951 {"st", FloatReg
|FloatAcc
, 0},
952 {"st(1)", FloatReg
, 1},
953 {"st(2)", FloatReg
, 2},
954 {"st(3)", FloatReg
, 3},
955 {"st(4)", FloatReg
, 4},
956 {"st(5)", FloatReg
, 5},
957 {"st(6)", FloatReg
, 6},
958 {"st(7)", FloatReg
, 7},
969 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
971 static const reg_entry
*const i386_regtab_end
972 = i386_regtab
+ sizeof(i386_regtab
)/sizeof(i386_regtab
[0]);
975 static const seg_entry cs
= { "cs", 0x2e };
976 static const seg_entry ds
= { "ds", 0x3e };
977 static const seg_entry ss
= { "ss", 0x36 };
978 static const seg_entry es
= { "es", 0x26 };
979 static const seg_entry fs
= { "fs", 0x64 };
980 static const seg_entry gs
= { "gs", 0x65 };
982 static const prefix_entry i386_prefixtab
[] = {
983 #define ADDR_PREFIX_OPCODE 0x67
984 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
985 useful when loop isns should use %cx. */
986 #define WORD_PREFIX_OPCODE 0x66
987 { "data16", 0x66 }, /* operand size prefix */
988 #define LOCK_PREFIX_OPCODE 0xf0
989 { "lock", 0xf0 }, /* bus lock prefix */
990 { "wait", FWAIT_OPCODE
}, /* wait for coprocessor, not really a prefix */
991 #define CS_PREFIX_OPCODE 0x2e
992 { "cs", 0x2e }, /* segment overrides ... */
993 #define DS_PREFIX_OPCODE 0x3e
995 #define ES_PREFIX_OPCODE 0x26
997 #define FS_PREFIX_OPCODE 0x64
999 #define GS_PREFIX_OPCODE 0x65
1001 #define SS_PREFIX_OPCODE 0x36
1003 /* REPE & REPNE used to detect rep/repne with a non-string instruction */
1006 { "rep", 0xf3 }, /* repeat string instructions */
1013 static const prefix_entry
*const i386_prefixtab_end
1014 = i386_prefixtab
+ sizeof(i386_prefixtab
)/sizeof(i386_prefixtab
[0]);
1016 /* end of i386-opcode.h */