1 /* i386-opcode.h -- Intel 80386 opcode table
2 Copyright 1989, 1991, 1992 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 static const template i386_optab
[] = {
23 /* move instructions */
24 { "mov", 2, 0xa0, _
, DW
|NoModrm
, Disp32
, Acc
, 0 },
25 { "mov", 2, 0x88, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0 },
26 { "mov", 2, 0xb0, _
, ShortFormW
, Imm
, Reg
, 0 },
27 { "mov", 2, 0xc6, _
, W
|Modrm
, Imm
, Reg
|Mem
, 0 },
28 { "mov", 2, 0x8c, _
, D
|Modrm
, SReg3
|SReg2
, Reg16
|Mem16
, 0 },
29 /* move to/from control debug registers */
30 { "mov", 2, 0x0f20, _
, D
|Modrm
, Control
, Reg32
, 0},
31 { "mov", 2, 0x0f21, _
, D
|Modrm
, Debug
, Reg32
, 0},
32 { "mov", 2, 0x0f24, _
, D
|Modrm
, Test
, Reg32
, 0},
34 /* move with sign extend */
35 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
36 conflict with the "movs" string move instruction. Thus,
37 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
38 is not kosher; we must seperate the two instructions. */
39 {"movsbl", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
, Reg8
|Mem
, Reg32
, 0},
40 {"movsbw", 2, 0x660fbe, _
, ReverseRegRegmem
|Modrm
, Reg8
|Mem
, Reg16
, 0},
41 {"movswl", 2, 0x0fbf, _
, ReverseRegRegmem
|Modrm
, Reg16
|Mem
, Reg32
, 0},
43 /* move with zero extend */
44 {"movzb", 2, 0x0fb6, _
, ReverseRegRegmem
|Modrm
, Reg8
|Mem
, Reg16
|Reg32
, 0},
45 {"movzwl", 2, 0x0fb7, _
, ReverseRegRegmem
|Modrm
, Reg16
|Mem
, Reg32
, 0},
47 /* push instructions */
48 {"push", 1, 0x50, _
, ShortForm
, WordReg
,0,0 },
49 {"push", 1, 0xff, 0x6, Modrm
, WordReg
|WordMem
, 0, 0 },
50 {"push", 1, 0x6a, _
, NoModrm
, Imm8S
, 0, 0},
51 {"push", 1, 0x68, _
, NoModrm
, Imm32
, 0, 0},
52 {"push", 1, 0x06, _
, Seg2ShortForm
, SReg2
,0,0 },
53 {"push", 1, 0x0fa0, _
, Seg3ShortForm
, SReg3
,0,0 },
55 {"pusha", 0, 0x60, _
, NoModrm
, 0, 0, 0 },
57 /* pop instructions */
58 {"pop", 1, 0x58, _
, ShortForm
, WordReg
,0,0 },
59 {"pop", 1, 0x8f, 0x0, Modrm
, WordReg
|WordMem
, 0, 0 },
60 #define POP_SEG_SHORT 0x7
61 {"pop", 1, 0x07, _
, Seg2ShortForm
, SReg2
,0,0 },
62 {"pop", 1, 0x0fa1, _
, Seg3ShortForm
, SReg3
,0,0 },
64 {"popa", 0, 0x61, _
, NoModrm
, 0, 0, 0 },
66 /* xchg exchange instructions
67 xchg commutes: we allow both operand orders */
68 {"xchg", 2, 0x90, _
, ShortForm
, WordReg
, Acc
, 0 },
69 {"xchg", 2, 0x90, _
, ShortForm
, Acc
, WordReg
, 0 },
70 {"xchg", 2, 0x86, _
, W
|Modrm
, Reg
, Reg
|Mem
, 0 },
71 {"xchg", 2, 0x86, _
, W
|Modrm
, Reg
|Mem
, Reg
, 0 },
73 /* in/out from ports */
74 {"in", 2, 0xe4, _
, W
|NoModrm
, Imm8
, Acc
, 0 },
75 {"in", 2, 0xec, _
, W
|NoModrm
, InOutPortReg
, Acc
, 0 },
76 {"out", 2, 0xe6, _
, W
|NoModrm
, Acc
, Imm8
, 0 },
77 {"out", 2, 0xee, _
, W
|NoModrm
, Acc
, InOutPortReg
, 0 },
79 {"inb", 1, 0xe4, _
, NoModrm
, Imm8
, 0, 0 },
80 {"inb", 1, 0xec, _
, NoModrm
, WordMem
, 0, 0 },
81 {"inw", 1, 0x66e5, _
, NoModrm
, Imm8
, 0, 0 },
82 {"inw", 1, 0x66ed, _
, NoModrm
, WordMem
, 0, 0 },
83 {"outb", 1, 0xe6, _
, NoModrm
, Imm8
, 0, 0 },
84 {"outb", 1, 0xee, _
, NoModrm
, WordMem
, 0, 0 },
85 {"outw", 1, 0x66e7, _
, NoModrm
, Imm8
, 0, 0 },
86 {"outw", 1, 0x66ef, _
, NoModrm
, WordMem
, 0, 0 },
88 /* load effective address */
89 {"lea", 2, 0x8d, _
, Modrm
, WordMem
, WordReg
, 0 },
91 /* load segment registers from memory */
92 {"lds", 2, 0xc5, _
, Modrm
, Mem
, Reg32
, 0},
93 {"les", 2, 0xc4, _
, Modrm
, Mem
, Reg32
, 0},
94 {"lfs", 2, 0x0fb4, _
, Modrm
, Mem
, Reg32
, 0},
95 {"lgs", 2, 0x0fb5, _
, Modrm
, Mem
, Reg32
, 0},
96 {"lss", 2, 0x0fb2, _
, Modrm
, Mem
, Reg32
, 0},
98 /* flags register instructions */
99 {"clc", 0, 0xf8, _
, NoModrm
, 0, 0, 0},
100 {"cld", 0, 0xfc, _
, NoModrm
, 0, 0, 0},
101 {"cli", 0, 0xfa, _
, NoModrm
, 0, 0, 0},
102 {"clts", 0, 0x0f06, _
, NoModrm
, 0, 0, 0},
103 {"cmc", 0, 0xf5, _
, NoModrm
, 0, 0, 0},
104 {"lahf", 0, 0x9f, _
, NoModrm
, 0, 0, 0},
105 {"sahf", 0, 0x9e, _
, NoModrm
, 0, 0, 0},
106 {"pushf", 0, 0x9c, _
, NoModrm
, 0, 0, 0},
107 {"popf", 0, 0x9d, _
, NoModrm
, 0, 0, 0},
108 {"stc", 0, 0xf9, _
, NoModrm
, 0, 0, 0},
109 {"std", 0, 0xfd, _
, NoModrm
, 0, 0, 0},
110 {"sti", 0, 0xfb, _
, NoModrm
, 0, 0, 0},
112 {"add", 2, 0x0, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
113 {"add", 2, 0x83, 0, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
114 {"add", 2, 0x4, _
, W
|NoModrm
, Imm
, Acc
, 0},
115 {"add", 2, 0x80, 0, W
|Modrm
, Imm
, Reg
|Mem
, 0},
117 {"inc", 1, 0x40, _
, ShortForm
, WordReg
, 0, 0},
118 {"inc", 1, 0xfe, 0, W
|Modrm
, Reg
|Mem
, 0, 0},
120 {"sub", 2, 0x28, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
121 {"sub", 2, 0x83, 5, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
122 {"sub", 2, 0x2c, _
, W
|NoModrm
, Imm
, Acc
, 0},
123 {"sub", 2, 0x80, 5, W
|Modrm
, Imm
, Reg
|Mem
, 0},
125 {"dec", 1, 0x48, _
, ShortForm
, WordReg
, 0, 0},
126 {"dec", 1, 0xfe, 1, W
|Modrm
, Reg
|Mem
, 0, 0},
128 {"sbb", 2, 0x18, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
129 {"sbb", 2, 0x83, 3, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
130 {"sbb", 2, 0x1c, _
, W
|NoModrm
, Imm
, Acc
, 0},
131 {"sbb", 2, 0x80, 3, W
|Modrm
, Imm
, Reg
|Mem
, 0},
133 {"cmp", 2, 0x38, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
134 {"cmp", 2, 0x83, 7, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
135 {"cmp", 2, 0x3c, _
, W
|NoModrm
, Imm
, Acc
, 0},
136 {"cmp", 2, 0x80, 7, W
|Modrm
, Imm
, Reg
|Mem
, 0},
138 {"test", 2, 0x84, _
, W
|Modrm
, Reg
|Mem
, Reg
, 0},
139 {"test", 2, 0x84, _
, W
|Modrm
, Reg
, Reg
|Mem
, 0},
140 {"test", 2, 0xa8, _
, W
|NoModrm
, Imm
, Acc
, 0},
141 {"test", 2, 0xf6, 0, W
|Modrm
, Imm
, Reg
|Mem
, 0},
143 {"and", 2, 0x20, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
144 {"and", 2, 0x83, 4, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
145 {"and", 2, 0x24, _
, W
|NoModrm
, Imm
, Acc
, 0},
146 {"and", 2, 0x80, 4, W
|Modrm
, Imm
, Reg
|Mem
, 0},
148 {"or", 2, 0x08, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
149 {"or", 2, 0x83, 1, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
150 {"or", 2, 0x0c, _
, W
|NoModrm
, Imm
, Acc
, 0},
151 {"or", 2, 0x80, 1, W
|Modrm
, Imm
, Reg
|Mem
, 0},
153 {"xor", 2, 0x30, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
154 {"xor", 2, 0x83, 6, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
155 {"xor", 2, 0x34, _
, W
|NoModrm
, Imm
, Acc
, 0},
156 {"xor", 2, 0x80, 6, W
|Modrm
, Imm
, Reg
|Mem
, 0},
158 {"adc", 2, 0x10, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
159 {"adc", 2, 0x83, 2, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
160 {"adc", 2, 0x14, _
, W
|NoModrm
, Imm
, Acc
, 0},
161 {"adc", 2, 0x80, 2, W
|Modrm
, Imm
, Reg
|Mem
, 0},
163 {"neg", 1, 0xf6, 3, W
|Modrm
, Reg
|Mem
, 0, 0},
164 {"not", 1, 0xf6, 2, W
|Modrm
, Reg
|Mem
, 0, 0},
166 {"aaa", 0, 0x37, _
, NoModrm
, 0, 0, 0},
167 {"aas", 0, 0x3f, _
, NoModrm
, 0, 0, 0},
168 {"daa", 0, 0x27, _
, NoModrm
, 0, 0, 0},
169 {"das", 0, 0x2f, _
, NoModrm
, 0, 0, 0},
170 {"aad", 0, 0xd50a, _
, NoModrm
, 0, 0, 0},
171 {"aam", 0, 0xd40a, _
, NoModrm
, 0, 0, 0},
173 /* conversion insns */
174 /* conversion: intel naming */
175 {"cbw", 0, 0x6698, _
, NoModrm
, 0, 0, 0},
176 {"cwd", 0, 0x6699, _
, NoModrm
, 0, 0, 0},
177 {"cwde", 0, 0x98, _
, NoModrm
, 0, 0, 0},
178 {"cdq", 0, 0x99, _
, NoModrm
, 0, 0, 0},
180 {"cbtw", 0, 0x6698, _
, NoModrm
, 0, 0, 0},
181 {"cwtl", 0, 0x98, _
, NoModrm
, 0, 0, 0},
182 {"cwtd", 0, 0x6699, _
, NoModrm
, 0, 0, 0},
183 {"cltd", 0, 0x99, _
, NoModrm
, 0, 0, 0},
185 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
186 expanding 64-bit multiplies, and *cannot* be selected to accomplish
187 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
188 These multiplies can only be selected with single opearnd forms. */
189 {"mul", 1, 0xf6, 4, W
|Modrm
, Reg
|Mem
, 0, 0},
190 {"imul", 1, 0xf6, 5, W
|Modrm
, Reg
|Mem
, 0, 0},
195 /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
196 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
197 '%eax' in the reg field and '%ecx' in the regmem field if we did not
199 {"imul", 2, 0x0faf, _
, Modrm
|ReverseRegRegmem
, WordReg
|Mem
, WordReg
, 0},
200 {"imul", 3, 0x6b, _
, Modrm
|ReverseRegRegmem
, Imm8S
, WordReg
|Mem
, WordReg
},
201 {"imul", 3, 0x69, _
, Modrm
|ReverseRegRegmem
, Imm16
|Imm32
, WordReg
|Mem
, WordReg
},
203 imul with 2 operands mimicks imul with 3 by puting register both
204 in i.rm.reg & i.rm.regmem fields
206 {"imul", 2, 0x6b, _
, Modrm
|imulKludge
, Imm8S
, WordReg
, 0},
207 {"imul", 2, 0x69, _
, Modrm
|imulKludge
, Imm16
|Imm32
, WordReg
, 0},
208 {"div", 1, 0xf6, 6, W
|Modrm
, Reg
|Mem
, 0, 0},
209 {"div", 2, 0xf6, 6, W
|Modrm
, Reg
|Mem
, Acc
, 0},
210 {"idiv", 1, 0xf6, 7, W
|Modrm
, Reg
|Mem
, 0, 0},
211 {"idiv", 2, 0xf6, 7, W
|Modrm
, Reg
|Mem
, Acc
, 0},
213 {"rol", 2, 0xd0, 0, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
214 {"rol", 2, 0xc0, 0, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
215 {"rol", 2, 0xd2, 0, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
216 {"rol", 1, 0xd0, 0, W
|Modrm
, Reg
|Mem
, 0, 0},
218 {"ror", 2, 0xd0, 1, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
219 {"ror", 2, 0xc0, 1, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
220 {"ror", 2, 0xd2, 1, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
221 {"ror", 1, 0xd0, 1, W
|Modrm
, Reg
|Mem
, 0, 0},
223 {"rcl", 2, 0xd0, 2, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
224 {"rcl", 2, 0xc0, 2, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
225 {"rcl", 2, 0xd2, 2, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
226 {"rcl", 1, 0xd0, 2, W
|Modrm
, Reg
|Mem
, 0, 0},
228 {"rcr", 2, 0xd0, 3, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
229 {"rcr", 2, 0xc0, 3, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
230 {"rcr", 2, 0xd2, 3, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
231 {"rcr", 1, 0xd0, 3, W
|Modrm
, Reg
|Mem
, 0, 0},
233 {"sal", 2, 0xd0, 4, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
234 {"sal", 2, 0xc0, 4, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
235 {"sal", 2, 0xd2, 4, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
236 {"sal", 1, 0xd0, 4, W
|Modrm
, Reg
|Mem
, 0, 0},
237 {"shl", 2, 0xd0, 4, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
238 {"shl", 2, 0xc0, 4, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
239 {"shl", 2, 0xd2, 4, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
240 {"shl", 1, 0xd0, 4, W
|Modrm
, Reg
|Mem
, 0, 0},
242 {"shld", 3, 0x0fa4, _
, Modrm
, Imm8
, WordReg
, WordReg
|Mem
},
243 {"shld", 3, 0x0fa5, _
, Modrm
, ShiftCount
, WordReg
, WordReg
|Mem
},
245 {"shr", 2, 0xd0, 5, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
246 {"shr", 2, 0xc0, 5, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
247 {"shr", 2, 0xd2, 5, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
248 {"shr", 1, 0xd0, 5, W
|Modrm
, Reg
|Mem
, 0, 0},
250 {"shrd", 3, 0x0fac, _
, Modrm
, Imm8
, WordReg
, WordReg
|Mem
},
251 {"shrd", 3, 0x0fad, _
, Modrm
, ShiftCount
, WordReg
, WordReg
|Mem
},
253 {"sar", 2, 0xd0, 7, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
254 {"sar", 2, 0xc0, 7, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
255 {"sar", 2, 0xd2, 7, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
256 {"sar", 1, 0xd0, 7, W
|Modrm
, Reg
|Mem
, 0, 0},
258 /* control transfer instructions */
259 #define CALL_PC_RELATIVE 0xe8
260 {"call", 1, 0xe8, _
, JumpDword
, Disp32
, 0, 0},
261 {"call", 1, 0xff, 2, Modrm
, Reg
|Mem
|JumpAbsolute
, 0, 0},
262 #define CALL_FAR_IMMEDIATE 0x9a
263 {"lcall", 2, 0x9a, _
, JumpInterSegment
, Imm16
, Abs32
, 0},
264 {"lcall", 1, 0xff, 3, Modrm
, Mem
, 0, 0},
266 #define JUMP_PC_RELATIVE 0xeb
267 {"jmp", 1, 0xeb, _
, Jump
, Disp
, 0, 0},
268 {"jmp", 1, 0xff, 4, Modrm
, Reg32
|Mem
|JumpAbsolute
, 0, 0},
269 #define JUMP_FAR_IMMEDIATE 0xea
270 {"ljmp", 2, 0xea, _
, JumpInterSegment
, Imm16
, Imm32
, 0},
271 {"ljmp", 1, 0xff, 5, Modrm
, Mem
, 0, 0},
273 {"ret", 0, 0xc3, _
, NoModrm
, 0, 0, 0},
274 {"ret", 1, 0xc2, _
, NoModrm
, Imm16
, 0, 0},
275 {"lret", 0, 0xcb, _
, NoModrm
, 0, 0, 0},
276 {"lret", 1, 0xca, _
, NoModrm
, Imm16
, 0, 0},
277 {"enter", 2, 0xc8, _
, NoModrm
, Imm16
, Imm8
, 0},
278 {"leave", 0, 0xc9, _
, NoModrm
, 0, 0, 0},
280 /* conditional jumps */
281 {"jo", 1, 0x70, _
, Jump
, Disp
, 0, 0},
283 {"jno", 1, 0x71, _
, Jump
, Disp
, 0, 0},
285 {"jb", 1, 0x72, _
, Jump
, Disp
, 0, 0},
286 {"jc", 1, 0x72, _
, Jump
, Disp
, 0, 0},
287 {"jnae", 1, 0x72, _
, Jump
, Disp
, 0, 0},
289 {"jnb", 1, 0x73, _
, Jump
, Disp
, 0, 0},
290 {"jnc", 1, 0x73, _
, Jump
, Disp
, 0, 0},
291 {"jae", 1, 0x73, _
, Jump
, Disp
, 0, 0},
293 {"je", 1, 0x74, _
, Jump
, Disp
, 0, 0},
294 {"jz", 1, 0x74, _
, Jump
, Disp
, 0, 0},
296 {"jne", 1, 0x75, _
, Jump
, Disp
, 0, 0},
297 {"jnz", 1, 0x75, _
, Jump
, Disp
, 0, 0},
299 {"jbe", 1, 0x76, _
, Jump
, Disp
, 0, 0},
300 {"jna", 1, 0x76, _
, Jump
, Disp
, 0, 0},
302 {"jnbe", 1, 0x77, _
, Jump
, Disp
, 0, 0},
303 {"ja", 1, 0x77, _
, Jump
, Disp
, 0, 0},
305 {"js", 1, 0x78, _
, Jump
, Disp
, 0, 0},
307 {"jns", 1, 0x79, _
, Jump
, Disp
, 0, 0},
309 {"jp", 1, 0x7a, _
, Jump
, Disp
, 0, 0},
310 {"jpe", 1, 0x7a, _
, Jump
, Disp
, 0, 0},
312 {"jnp", 1, 0x7b, _
, Jump
, Disp
, 0, 0},
313 {"jpo", 1, 0x7b, _
, Jump
, Disp
, 0, 0},
315 {"jl", 1, 0x7c, _
, Jump
, Disp
, 0, 0},
316 {"jnge", 1, 0x7c, _
, Jump
, Disp
, 0, 0},
318 {"jnl", 1, 0x7d, _
, Jump
, Disp
, 0, 0},
319 {"jge", 1, 0x7d, _
, Jump
, Disp
, 0, 0},
321 {"jle", 1, 0x7e, _
, Jump
, Disp
, 0, 0},
322 {"jng", 1, 0x7e, _
, Jump
, Disp
, 0, 0},
324 {"jnle", 1, 0x7f, _
, Jump
, Disp
, 0, 0},
325 {"jg", 1, 0x7f, _
, Jump
, Disp
, 0, 0},
327 /* these turn into pseudo operations when disp is larger than 8 bits */
328 #define IS_JUMP_ON_CX_ZERO(o) \
330 #define IS_JUMP_ON_ECX_ZERO(o) \
333 {"jcxz", 1, 0x67e3, _
, JumpByte
, Disp
, 0, 0},
334 {"jecxz", 1, 0xe3, _
, JumpByte
, Disp
, 0, 0},
336 #define IS_LOOP_ECX_TIMES(o) \
337 (o == 0xe2 || o == 0xe1 || o == 0xe0)
339 {"loop", 1, 0xe2, _
, JumpByte
, Disp
, 0, 0},
341 {"loopz", 1, 0xe1, _
, JumpByte
, Disp
, 0, 0},
342 {"loope", 1, 0xe1, _
, JumpByte
, Disp
, 0, 0},
344 {"loopnz", 1, 0xe0, _
, JumpByte
, Disp
, 0, 0},
345 {"loopne", 1, 0xe0, _
, JumpByte
, Disp
, 0, 0},
347 /* set byte on flag instructions */
348 {"seto", 1, 0x0f90, 0, Modrm
, Reg8
|Mem
, 0, 0},
350 {"setno", 1, 0x0f91, 0, Modrm
, Reg8
|Mem
, 0, 0},
352 {"setb", 1, 0x0f92, 0, Modrm
, Reg8
|Mem
, 0, 0},
353 {"setc", 1, 0x0f92, 0, Modrm
, Reg8
|Mem
, 0, 0},
354 {"setnae", 1, 0x0f92, 0, Modrm
, Reg8
|Mem
, 0, 0},
356 {"setnb", 1, 0x0f93, 0, Modrm
, Reg8
|Mem
, 0, 0},
357 {"setnc", 1, 0x0f93, 0, Modrm
, Reg8
|Mem
, 0, 0},
358 {"setae", 1, 0x0f93, 0, Modrm
, Reg8
|Mem
, 0, 0},
360 {"sete", 1, 0x0f94, 0, Modrm
, Reg8
|Mem
, 0, 0},
361 {"setz", 1, 0x0f94, 0, Modrm
, Reg8
|Mem
, 0, 0},
363 {"setne", 1, 0x0f95, 0, Modrm
, Reg8
|Mem
, 0, 0},
364 {"setnz", 1, 0x0f95, 0, Modrm
, Reg8
|Mem
, 0, 0},
366 {"setbe", 1, 0x0f96, 0, Modrm
, Reg8
|Mem
, 0, 0},
367 {"setna", 1, 0x0f96, 0, Modrm
, Reg8
|Mem
, 0, 0},
369 {"setnbe", 1, 0x0f97, 0, Modrm
, Reg8
|Mem
, 0, 0},
370 {"seta", 1, 0x0f97, 0, Modrm
, Reg8
|Mem
, 0, 0},
372 {"sets", 1, 0x0f98, 0, Modrm
, Reg8
|Mem
, 0, 0},
374 {"setns", 1, 0x0f99, 0, Modrm
, Reg8
|Mem
, 0, 0},
376 {"setp", 1, 0x0f9a, 0, Modrm
, Reg8
|Mem
, 0, 0},
377 {"setpe", 1, 0x0f9a, 0, Modrm
, Reg8
|Mem
, 0, 0},
379 {"setnp", 1, 0x0f9b, 0, Modrm
, Reg8
|Mem
, 0, 0},
380 {"setpo", 1, 0x0f9b, 0, Modrm
, Reg8
|Mem
, 0, 0},
382 {"setl", 1, 0x0f9c, 0, Modrm
, Reg8
|Mem
, 0, 0},
383 {"setnge", 1, 0x0f9c, 0, Modrm
, Reg8
|Mem
, 0, 0},
385 {"setnl", 1, 0x0f9d, 0, Modrm
, Reg8
|Mem
, 0, 0},
386 {"setge", 1, 0x0f9d, 0, Modrm
, Reg8
|Mem
, 0, 0},
388 {"setle", 1, 0x0f9e, 0, Modrm
, Reg8
|Mem
, 0, 0},
389 {"setng", 1, 0x0f9e, 0, Modrm
, Reg8
|Mem
, 0, 0},
391 {"setnle", 1, 0x0f9f, 0, Modrm
, Reg8
|Mem
, 0, 0},
392 {"setg", 1, 0x0f9f, 0, Modrm
, Reg8
|Mem
, 0, 0},
394 #define IS_STRING_INSTRUCTION(o) \
395 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
396 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
399 /* string manipulation */
400 {"cmps", 0, 0xa6, _
, W
|NoModrm
, 0, 0, 0},
401 {"scmp", 0, 0xa6, _
, W
|NoModrm
, 0, 0, 0},
402 {"ins", 0, 0x6c, _
, W
|NoModrm
, 0, 0, 0},
403 {"outs", 0, 0x6e, _
, W
|NoModrm
, 0, 0, 0},
404 {"lods", 0, 0xac, _
, W
|NoModrm
, 0, 0, 0},
405 {"slod", 0, 0xac, _
, W
|NoModrm
, 0, 0, 0},
406 {"movs", 0, 0xa4, _
, W
|NoModrm
, 0, 0, 0},
407 {"smov", 0, 0xa4, _
, W
|NoModrm
, 0, 0, 0},
408 {"scas", 0, 0xae, _
, W
|NoModrm
, 0, 0, 0},
409 {"ssca", 0, 0xae, _
, W
|NoModrm
, 0, 0, 0},
410 {"stos", 0, 0xaa, _
, W
|NoModrm
, 0, 0, 0},
411 {"ssto", 0, 0xaa, _
, W
|NoModrm
, 0, 0, 0},
412 {"xlat", 0, 0xd7, _
, NoModrm
, 0, 0, 0},
414 /* bit manipulation */
415 {"bsf", 2, 0x0fbc, _
, Modrm
|ReverseRegRegmem
, Reg
|Mem
, Reg
, 0},
416 {"bsr", 2, 0x0fbd, _
, Modrm
|ReverseRegRegmem
, Reg
|Mem
, Reg
, 0},
417 {"bt", 2, 0x0fa3, _
, Modrm
, Reg
, Reg
|Mem
, 0},
418 {"bt", 2, 0x0fba, 4, Modrm
, Imm8
, Reg
|Mem
, 0},
419 {"btc", 2, 0x0fbb, _
, Modrm
, Reg
, Reg
|Mem
, 0},
420 {"btc", 2, 0x0fba, 7, Modrm
, Imm8
, Reg
|Mem
, 0},
421 {"btr", 2, 0x0fb3, _
, Modrm
, Reg
, Reg
|Mem
, 0},
422 {"btr", 2, 0x0fba, 6, Modrm
, Imm8
, Reg
|Mem
, 0},
423 {"bts", 2, 0x0fab, _
, Modrm
, Reg
, Reg
|Mem
, 0},
424 {"bts", 2, 0x0fba, 5, Modrm
, Imm8
, Reg
|Mem
, 0},
426 /* interrupts & op. sys insns */
427 /* See i386.c for conversion of 'int $3' into the special int 3 insn. */
428 #define INT_OPCODE 0xcd
429 #define INT3_OPCODE 0xcc
430 {"int", 1, 0xcd, _
, NoModrm
, Imm8
, 0, 0},
431 {"int3", 0, 0xcc, _
, NoModrm
, 0, 0, 0},
432 {"into", 0, 0xce, _
, NoModrm
, 0, 0, 0},
433 {"iret", 0, 0xcf, _
, NoModrm
, 0, 0, 0},
435 {"boundl", 2, 0x62, _
, Modrm
, Reg32
, Mem
, 0},
436 {"boundw", 2, 0x6662, _
, Modrm
, Reg16
, Mem
, 0},
438 {"hlt", 0, 0xf4, _
, NoModrm
, 0, 0, 0},
439 {"wait", 0, 0x9b, _
, NoModrm
, 0, 0, 0},
440 /* nop is actually 'xchgl %eax, %eax' */
441 {"nop", 0, 0x90, _
, NoModrm
, 0, 0, 0},
443 /* protection control */
444 {"arpl", 2, 0x63, _
, Modrm
, Reg16
, Reg16
|Mem
, 0},
445 {"lar", 2, 0x0f02, _
, Modrm
|ReverseRegRegmem
, WordReg
|Mem
, WordReg
, 0},
446 {"lgdt", 1, 0x0f01, 2, Modrm
, Mem
, 0, 0},
447 {"lidt", 1, 0x0f01, 3, Modrm
, Mem
, 0, 0},
448 {"lldt", 1, 0x0f00, 2, Modrm
, WordReg
|Mem
, 0, 0},
449 {"lmsw", 1, 0x0f01, 6, Modrm
, WordReg
|Mem
, 0, 0},
450 {"lsl", 2, 0x0f03, _
, Modrm
|ReverseRegRegmem
, WordReg
|Mem
, WordReg
, 0},
451 {"ltr", 1, 0x0f00, 3, Modrm
, WordReg
|Mem
, 0, 0},
453 {"sgdt", 1, 0x0f01, 0, Modrm
, Mem
, 0, 0},
454 {"sidt", 1, 0x0f01, 1, Modrm
, Mem
, 0, 0},
455 {"sldt", 1, 0x0f00, 0, Modrm
, WordReg
|Mem
, 0, 0},
456 {"smsw", 1, 0x0f01, 4, Modrm
, WordReg
|Mem
, 0, 0},
457 {"str", 1, 0x0f00, 1, Modrm
, Reg16
|Mem
, 0, 0},
459 {"verr", 1, 0x0f00, 4, Modrm
, WordReg
|Mem
, 0, 0},
460 {"verw", 1, 0x0f00, 5, Modrm
, WordReg
|Mem
, 0, 0},
462 /* floating point instructions */
465 {"fld", 1, 0xd9c0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
466 {"flds", 1, 0xd9, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem float */
467 {"fldl", 1, 0xdd, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem double */
468 {"fldl", 1, 0xd9c0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
469 {"fild", 1, 0xdf, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem word (16) */
470 {"fildl", 1, 0xdb, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem dword (32) */
471 {"fildll",1, 0xdf, 5, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem qword (64) */
472 {"fldt", 1, 0xdb, 5, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem efloat */
473 {"fbld", 1, 0xdf, 4, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem bcd */
476 {"fst", 1, 0xddd0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
477 {"fsts", 1, 0xd9, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem float */
478 {"fstl", 1, 0xdd, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem double */
479 {"fstl", 1, 0xddd0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
480 {"fist", 1, 0xdf, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem word (16) */
481 {"fistl", 1, 0xdb, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem dword (32) */
483 /* store (with pop) */
484 {"fstp", 1, 0xddd8, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
485 {"fstps", 1, 0xd9, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem float */
486 {"fstpl", 1, 0xdd, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem double */
487 {"fstpl", 1, 0xddd8, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
488 {"fistp", 1, 0xdf, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem word (16) */
489 {"fistpl",1, 0xdb, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem dword (32) */
490 {"fistpll",1,0xdf, 7, Modrm
, Mem
, 0, 0}, /* %st0 --> mem qword (64) */
491 {"fstpt", 1, 0xdb, 7, Modrm
, Mem
, 0, 0}, /* %st0 --> mem efloat */
492 {"fbstp", 1, 0xdf, 6, Modrm
, Mem
, 0, 0}, /* %st0 --> mem bcd */
494 /* exchange %st<n> with %st0 */
495 {"fxch", 1, 0xd9c8, _
, ShortForm
, FloatReg
, 0, 0},
497 /* comparison (without pop) */
498 {"fcom", 1, 0xd8d0, _
, ShortForm
, FloatReg
, 0, 0},
499 {"fcoms", 1, 0xd8, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem float */
500 {"ficoml", 1, 0xda, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem word */
501 {"fcoml", 1, 0xdc, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem double */
502 {"fcoml", 1, 0xd8d0, _
, ShortForm
, FloatReg
, 0, 0},
503 {"ficoms", 1, 0xde, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem dword */
505 /* comparison (with pop) */
506 {"fcomp", 1, 0xd8d8, _
, ShortForm
, FloatReg
, 0, 0},
507 {"fcomps", 1, 0xd8, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem float */
508 {"ficompl", 1, 0xda, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem word */
509 {"fcompl", 1, 0xdc, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem double */
510 {"fcompl", 1, 0xd8d8, _
, ShortForm
, FloatReg
, 0, 0},
511 {"ficomps", 1, 0xde, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem dword */
512 {"fcompp", 0, 0xded9, _
, NoModrm
, 0, 0, 0}, /* compare %st0, %st1 & pop twice */
514 /* unordered comparison (with pop) */
515 {"fucom", 1, 0xdde0, _
, ShortForm
, FloatReg
, 0, 0},
516 {"fucomp", 1, 0xdde8, _
, ShortForm
, FloatReg
, 0, 0},
517 {"fucompp", 0, 0xdae9, _
, NoModrm
, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */
519 {"ftst", 0, 0xd9e4, _
, NoModrm
, 0, 0, 0}, /* test %st0 */
520 {"fxam", 0, 0xd9e5, _
, NoModrm
, 0, 0, 0}, /* examine %st0 */
522 /* load constants into %st0 */
523 {"fld1", 0, 0xd9e8, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- 1.0 */
524 {"fldl2t", 0, 0xd9e9, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- log2(10) */
525 {"fldl2e", 0, 0xd9ea, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- log2(e) */
526 {"fldpi", 0, 0xd9eb, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- pi */
527 {"fldlg2", 0, 0xd9ec, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- log10(2) */
528 {"fldln2", 0, 0xd9ed, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- ln(2) */
529 {"fldz", 0, 0xd9ee, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- 0.0 */
534 {"fadd", 1, 0xd8c0, _
, ShortForm
, FloatReg
, 0, 0},
535 {"fadd", 2, 0xd8c0, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
536 {"fadd", 0, 0xdcc1, _
, NoModrm
, 0, 0, 0}, /* alias for fadd %st, %st(1) */
537 {"faddp", 1, 0xdac0, _
, ShortForm
, FloatReg
, 0, 0},
538 {"faddp", 2, 0xdac0, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
539 {"faddp", 0, 0xdec1, _
, NoModrm
, 0, 0, 0}, /* alias for faddp %st, %st(1) */
540 {"fadds", 1, 0xd8, 0, Modrm
, Mem
, 0, 0},
541 {"fiaddl", 1, 0xda, 0, Modrm
, Mem
, 0, 0},
542 {"faddl", 1, 0xdc, 0, Modrm
, Mem
, 0, 0},
543 {"fiadds", 1, 0xde, 0, Modrm
, Mem
, 0, 0},
546 /* Note: intel has decided that certain of these operations are reversed
547 in assembler syntax. */
548 {"fsub", 1, 0xd8e0, _
, ShortForm
, FloatReg
, 0, 0},
549 {"fsub", 2, 0xd8e0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
550 #ifdef NON_BROKEN_OPCODES
551 {"fsub", 2, 0xdce8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
553 {"fsub", 2, 0xdce0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
555 {"fsub", 0, 0xdce1, _
, NoModrm
, 0, 0, 0},
556 {"fsubp", 1, 0xdae0, _
, ShortForm
, FloatReg
, 0, 0},
557 {"fsubp", 2, 0xdae0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
558 #ifdef NON_BROKEN_OPCODES
559 {"fsubp", 2, 0xdee8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
561 {"fsubp", 2, 0xdee0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
563 {"fsubp", 0, 0xdee1, _
, NoModrm
, 0, 0, 0},
564 {"fsubs", 1, 0xd8, 4, Modrm
, Mem
, 0, 0},
565 {"fisubl", 1, 0xda, 4, Modrm
, Mem
, 0, 0},
566 {"fsubl", 1, 0xdc, 4, Modrm
, Mem
, 0, 0},
567 {"fisubs", 1, 0xde, 4, Modrm
, Mem
, 0, 0},
570 {"fsubr", 1, 0xd8e8, _
, ShortForm
, FloatReg
, 0, 0},
571 {"fsubr", 2, 0xd8e8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
572 #ifdef NON_BROKEN_OPCODES
573 {"fsubr", 2, 0xdce0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
575 {"fsubr", 2, 0xdce8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
577 {"fsubr", 0, 0xdce9, _
, NoModrm
, 0, 0, 0},
578 {"fsubrp", 1, 0xdae8, _
, ShortForm
, FloatReg
, 0, 0},
579 {"fsubrp", 2, 0xdae8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
580 #ifdef NON_BROKEN_OPCODES
581 {"fsubrp", 2, 0xdee0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
583 {"fsubrp", 2, 0xdee8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
585 {"fsubrp", 0, 0xdee9, _
, NoModrm
, 0, 0, 0},
586 {"fsubrs", 1, 0xd8, 5, Modrm
, Mem
, 0, 0},
587 {"fisubrl", 1, 0xda, 5, Modrm
, Mem
, 0, 0},
588 {"fsubrl", 1, 0xdc, 5, Modrm
, Mem
, 0, 0},
589 {"fisubrs", 1, 0xde, 5, Modrm
, Mem
, 0, 0},
592 {"fmul", 1, 0xd8c8, _
, ShortForm
, FloatReg
, 0, 0},
593 {"fmul", 2, 0xd8c8, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
594 {"fmul", 0, 0xdcc9, _
, NoModrm
, 0, 0, 0},
595 {"fmulp", 1, 0xdac8, _
, ShortForm
, FloatReg
, 0, 0},
596 {"fmulp", 2, 0xdac8, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
597 {"fmulp", 0, 0xdec9, _
, NoModrm
, 0, 0, 0},
598 {"fmuls", 1, 0xd8, 1, Modrm
, Mem
, 0, 0},
599 {"fimull", 1, 0xda, 1, Modrm
, Mem
, 0, 0},
600 {"fmull", 1, 0xdc, 1, Modrm
, Mem
, 0, 0},
601 {"fimuls", 1, 0xde, 1, Modrm
, Mem
, 0, 0},
604 /* Note: intel has decided that certain of these operations are reversed
605 in assembler syntax. */
606 {"fdiv", 1, 0xd8f0, _
, ShortForm
, FloatReg
, 0, 0},
607 {"fdiv", 2, 0xd8f0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
608 #ifdef NON_BROKEN_OPCODES
609 {"fdiv", 2, 0xdcf8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
611 {"fdiv", 2, 0xdcf0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
613 {"fdiv", 0, 0xdcf1, _
, NoModrm
, 0, 0, 0},
614 {"fdivp", 1, 0xdaf0, _
, ShortForm
, FloatReg
, 0, 0},
615 {"fdivp", 2, 0xdaf0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
616 #ifdef NON_BROKEN_OPCODES
617 {"fdivp", 2, 0xdef8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
619 {"fdivp", 2, 0xdef0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
621 {"fdivp", 0, 0xdef1, _
, NoModrm
, 0, 0, 0},
622 {"fdivs", 1, 0xd8, 6, Modrm
, Mem
, 0, 0},
623 {"fidivl", 1, 0xda, 6, Modrm
, Mem
, 0, 0},
624 {"fdivl", 1, 0xdc, 6, Modrm
, Mem
, 0, 0},
625 {"fidivs", 1, 0xde, 6, Modrm
, Mem
, 0, 0},
628 {"fdivr", 1, 0xd8f8, _
, ShortForm
, FloatReg
, 0, 0},
629 {"fdivr", 2, 0xd8f8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
630 #ifdef NON_BROKEN_OPCODES
631 {"fdivr", 2, 0xdcf0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
633 {"fdivr", 2, 0xdcf8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
635 {"fdivr", 0, 0xdcf9, _
, NoModrm
, 0, 0, 0},
636 {"fdivrp", 1, 0xdaf8, _
, ShortForm
, FloatReg
, 0, 0},
637 {"fdivrp", 2, 0xdaf8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
638 #ifdef NON_BROKEN_OPCODES
639 {"fdivrp", 2, 0xdef0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
641 {"fdivrp", 2, 0xdef8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
643 {"fdivrp", 0, 0xdef9, _
, NoModrm
, 0, 0, 0},
644 {"fdivrs", 1, 0xd8, 7, Modrm
, Mem
, 0, 0},
645 {"fidivrl", 1, 0xda, 7, Modrm
, Mem
, 0, 0},
646 {"fdivrl", 1, 0xdc, 7, Modrm
, Mem
, 0, 0},
647 {"fidivrs", 1, 0xde, 7, Modrm
, Mem
, 0, 0},
649 {"f2xm1", 0, 0xd9f0, _
, NoModrm
, 0, 0, 0},
650 {"fyl2x", 0, 0xd9f1, _
, NoModrm
, 0, 0, 0},
651 {"fptan", 0, 0xd9f2, _
, NoModrm
, 0, 0, 0},
652 {"fpatan", 0, 0xd9f3, _
, NoModrm
, 0, 0, 0},
653 {"fxtract", 0, 0xd9f4, _
, NoModrm
, 0, 0, 0},
654 {"fprem1", 0, 0xd9f5, _
, NoModrm
, 0, 0, 0},
655 {"fdecstp", 0, 0xd9f6, _
, NoModrm
, 0, 0, 0},
656 {"fincstp", 0, 0xd9f7, _
, NoModrm
, 0, 0, 0},
657 {"fprem", 0, 0xd9f8, _
, NoModrm
, 0, 0, 0},
658 {"fyl2xp1", 0, 0xd9f9, _
, NoModrm
, 0, 0, 0},
659 {"fsqrt", 0, 0xd9fa, _
, NoModrm
, 0, 0, 0},
660 {"fsincos", 0, 0xd9fb, _
, NoModrm
, 0, 0, 0},
661 {"frndint", 0, 0xd9fc, _
, NoModrm
, 0, 0, 0},
662 {"fscale", 0, 0xd9fd, _
, NoModrm
, 0, 0, 0},
663 {"fsin", 0, 0xd9fe, _
, NoModrm
, 0, 0, 0},
664 {"fcos", 0, 0xd9ff, _
, NoModrm
, 0, 0, 0},
666 {"fchs", 0, 0xd9e0, _
, NoModrm
, 0, 0, 0},
667 {"fabs", 0, 0xd9e1, _
, NoModrm
, 0, 0, 0},
669 /* processor control */
670 {"fninit", 0, 0xdbe3, _
, NoModrm
, 0, 0, 0},
671 {"finit", 0, 0xdbe3, _
, NoModrm
, 0, 0, 0},
672 {"fldcw", 1, 0xd9, 5, Modrm
, Mem
, 0, 0},
673 {"fnstcw", 1, 0xd9, 7, Modrm
, Mem
, 0, 0},
674 {"fstcw", 1, 0xd9, 7, Modrm
, Mem
, 0, 0},
675 {"fnstsw", 1, 0xdfe0, _
, NoModrm
, Acc
, 0, 0},
676 {"fnstsw", 1, 0xdd, 7, Modrm
, Mem
, 0, 0},
677 {"fnstsw", 0, 0xdfe0, _
, NoModrm
, 0, 0, 0},
678 {"fstsw", 1, 0xdfe0, _
, NoModrm
, Acc
, 0, 0},
679 {"fstsw", 1, 0xdd, 7, Modrm
, Mem
, 0, 0},
680 {"fstsw", 0, 0xdfe0, _
, NoModrm
, 0, 0, 0},
681 {"fnclex", 0, 0xdbe2, _
, NoModrm
, 0, 0, 0},
682 {"fclex", 0, 0xdbe2, _
, NoModrm
, 0, 0, 0},
684 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
685 instructions; i'm not sure how to add them or how they are different.
686 My 386/387 book offers no details about this.
688 {"fnstenv", 1, 0xd9, 6, Modrm
, Mem
, 0, 0},
689 {"fstenv", 1, 0xd9, 6, Modrm
, Mem
, 0, 0},
690 {"fldenv", 1, 0xd9, 4, Modrm
, Mem
, 0, 0},
691 {"fnsave", 1, 0xdd, 6, Modrm
, Mem
, 0, 0},
692 {"fsave", 1, 0xdd, 6, Modrm
, Mem
, 0, 0},
693 {"frstor", 1, 0xdd, 4, Modrm
, Mem
, 0, 0},
695 {"ffree", 1, 0xddc0, _
, ShortForm
, FloatReg
, 0, 0},
696 {"fnop", 0, 0xd9d0, _
, NoModrm
, 0, 0, 0},
697 {"fwait", 0, 0x9b, _
, NoModrm
, 0, 0, 0},
700 opcode prefixes; we allow them as seperate insns too
701 (see prefix table below)
703 {"aword", 0, 0x67, _
, NoModrm
, 0, 0, 0},
704 {"addr16", 0, 0x67, _
, NoModrm
, 0, 0, 0},
705 {"word", 0, 0x66, _
, NoModrm
, 0, 0, 0},
706 {"data16", 0, 0x66, _
, NoModrm
, 0, 0, 0},
707 {"lock", 0, 0xf0, _
, NoModrm
, 0, 0, 0},
708 {"cs", 0, 0x2e, _
, NoModrm
, 0, 0, 0},
709 {"ds", 0, 0x3e, _
, NoModrm
, 0, 0, 0},
710 {"es", 0, 0x26, _
, NoModrm
, 0, 0, 0},
711 {"fs", 0, 0x64, _
, NoModrm
, 0, 0, 0},
712 {"gs", 0, 0x65, _
, NoModrm
, 0, 0, 0},
713 {"ss", 0, 0x36, _
, NoModrm
, 0, 0, 0},
714 {"rep", 0, 0xf3, _
, NoModrm
, 0, 0, 0},
715 {"repe", 0, 0xf3, _
, NoModrm
, 0, 0, 0},
716 {"repz", 0, 0xf3, _
, NoModrm
, 0, 0, 0},
717 {"repne", 0, 0xf2, _
, NoModrm
, 0, 0, 0},
718 {"repnz", 0, 0xf2, _
, NoModrm
, 0, 0, 0},
720 {"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */
724 static const template *i386_optab_end
725 = i386_optab
+ sizeof (i386_optab
)/sizeof(i386_optab
[0]);
727 /* 386 register table */
729 static const reg_entry i386_regtab
[] = {
731 {"al", Reg8
|Acc
, 0}, {"cl", Reg8
|ShiftCount
, 1}, {"dl", Reg8
, 2},
733 {"ah", Reg8
, 4}, {"ch", Reg8
, 5}, {"dh", Reg8
, 6}, {"bh", Reg8
, 7},
735 {"ax", Reg16
|Acc
, 0}, {"cx", Reg16
, 1}, {"dx", Reg16
|InOutPortReg
, 2}, {"bx", Reg16
, 3},
736 {"sp", Reg16
, 4}, {"bp", Reg16
, 5}, {"si", Reg16
, 6}, {"di", Reg16
, 7},
738 {"eax", Reg32
|Acc
, 0}, {"ecx", Reg32
, 1}, {"edx", Reg32
, 2}, {"ebx", Reg32
, 3},
739 {"esp", Reg32
, 4}, {"ebp", Reg32
, 5}, {"esi", Reg32
, 6}, {"edi", Reg32
, 7},
740 /* segment registers */
741 {"es", SReg2
, 0}, {"cs", SReg2
, 1}, {"ss", SReg2
, 2},
742 {"ds", SReg2
, 3}, {"fs", SReg3
, 4}, {"gs", SReg3
, 5},
743 /* control registers */
744 {"cr0", Control
, 0}, {"cr2", Control
, 2}, {"cr3", Control
, 3},
745 /* debug registers */
746 {"db0", Debug
, 0}, {"db1", Debug
, 1}, {"db2", Debug
, 2},
747 {"db3", Debug
, 3}, {"db6", Debug
, 6}, {"db7", Debug
, 7},
749 {"tr6", Test
, 6}, {"tr7", Test
, 7},
750 /* float registers */
751 {"st(0)", FloatReg
|FloatAcc
, 0},
752 {"st", FloatReg
|FloatAcc
, 0},
753 {"st(1)", FloatReg
, 1}, {"st(2)", FloatReg
, 2},
754 {"st(3)", FloatReg
, 3}, {"st(4)", FloatReg
, 4}, {"st(5)", FloatReg
, 5},
755 {"st(6)", FloatReg
, 6}, {"st(7)", FloatReg
, 7}
758 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
760 static const reg_entry
*i386_regtab_end
761 = i386_regtab
+ sizeof(i386_regtab
)/sizeof(i386_regtab
[0]);
764 static const seg_entry cs
= { "cs", 0x2e };
765 static const seg_entry ds
= { "ds", 0x3e };
766 static const seg_entry ss
= { "ss", 0x36 };
767 static const seg_entry es
= { "es", 0x26 };
768 static const seg_entry fs
= { "fs", 0x64 };
769 static const seg_entry gs
= { "gs", 0x65 };
770 static const seg_entry null
= { "", 0x0 };
773 This table is used to store the default segment register implied by all
774 possible memory addressing modes.
775 It is indexed by the mode & modrm entries of the modrm byte as follows:
776 index = (mode<<3) | modrm;
778 static const seg_entry
*one_byte_segment_defaults
[] = {
780 &ds
, &ds
, &ds
, &ds
, &null
, &ds
, &ds
, &ds
,
782 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
784 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
785 /* mode 3 --- not a memory reference; never referenced */
788 static const seg_entry
*two_byte_segment_defaults
[] = {
790 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
792 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
794 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
795 /* mode 3 --- not a memory reference; never referenced */
798 static const prefix_entry i386_prefixtab
[] = {
799 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
800 * (How is this useful?) */
801 #define WORD_PREFIX_OPCODE 0x66
802 { "data16", 0x66 }, /* operand size prefix */
803 { "lock", 0xf0 }, /* bus lock prefix */
804 { "wait", 0x9b }, /* wait for coprocessor */
805 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
806 { "es", 0x26 }, { "fs", 0x64 },
807 { "gs", 0x65 }, { "ss", 0x36 },
808 /* REPE & REPNE used to detect rep/repne with a non-string instruction */
811 { "rep", 0xf3 }, /* repeat string instructions */
812 { "repe", 0xf3 }, { "repz", 0xf3 },
813 { "repne", 0xf2 }, { "repnz", 0xf2 }
816 static const prefix_entry
*i386_prefixtab_end
817 = i386_prefixtab
+ sizeof(i386_prefixtab
)/sizeof(i386_prefixtab
[0]);
819 /* end of i386-opcode.h */