1 /* ia64.h -- Header file for ia64 opcode table
2 Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
4 See the file HP-COPYRIGHT for additional information. */
14 typedef BFD_HOST_U_64_BIT ia64_insn
;
18 IA64_TYPE_NIL
= 0, /* illegal type */
19 IA64_TYPE_A
, /* integer alu (I- or M-unit) */
20 IA64_TYPE_I
, /* non-alu integer (I-unit) */
21 IA64_TYPE_M
, /* memory (M-unit) */
22 IA64_TYPE_B
, /* branch (B-unit) */
23 IA64_TYPE_F
, /* floating-point (F-unit) */
24 IA64_TYPE_X
, /* long encoding (X-unit) */
25 IA64_TYPE_DYN
, /* Dynamic opcode */
31 IA64_UNIT_NIL
= 0, /* illegal unit */
32 IA64_UNIT_I
, /* integer unit */
33 IA64_UNIT_M
, /* memory unit */
34 IA64_UNIT_B
, /* branching unit */
35 IA64_UNIT_F
, /* floating-point unit */
36 IA64_UNIT_L
, /* long "unit" */
37 IA64_UNIT_X
, /* may be integer or branch unit */
41 /* Changes to this enumeration must be propagated to the operand table in
46 IA64_OPND_NIL
, /* no operand---MUST BE FIRST!*/
49 IA64_OPND_AR_CCV
, /* application register ccv (ar.ccv) */
50 IA64_OPND_AR_PFS
, /* application register pfs (ar.pfs) */
51 IA64_OPND_C1
, /* the constant 1 */
52 IA64_OPND_C8
, /* the constant 8 */
53 IA64_OPND_C16
, /* the constant 16 */
54 IA64_OPND_GR0
, /* gr0 */
55 IA64_OPND_IP
, /* instruction pointer (ip) */
56 IA64_OPND_PR
, /* predicate register (pr) */
57 IA64_OPND_PR_ROT
, /* rotating predicate register (pr.rot) */
58 IA64_OPND_PSR
, /* processor status register (psr) */
59 IA64_OPND_PSR_L
, /* processor status register L (psr.l) */
60 IA64_OPND_PSR_UM
, /* processor status register UM (psr.um) */
62 /* register operands: */
63 IA64_OPND_AR3
, /* third application register # (bits 20-26) */
64 IA64_OPND_B1
, /* branch register # (bits 6-8) */
65 IA64_OPND_B2
, /* branch register # (bits 13-15) */
66 IA64_OPND_CR3
, /* third control register # (bits 20-26) */
67 IA64_OPND_F1
, /* first floating-point register # */
68 IA64_OPND_F2
, /* second floating-point register # */
69 IA64_OPND_F3
, /* third floating-point register # */
70 IA64_OPND_F4
, /* fourth floating-point register # */
71 IA64_OPND_P1
, /* first predicate # */
72 IA64_OPND_P2
, /* second predicate # */
73 IA64_OPND_R1
, /* first register # */
74 IA64_OPND_R2
, /* second register # */
75 IA64_OPND_R3
, /* third register # */
76 IA64_OPND_R3_2
, /* third register # (limited to gr0-gr3) */
78 /* indirect operands: */
79 IA64_OPND_CPUID_R3
, /* cpuid[reg] */
80 IA64_OPND_DBR_R3
, /* dbr[reg] */
81 IA64_OPND_DTR_R3
, /* dtr[reg] */
82 IA64_OPND_ITR_R3
, /* itr[reg] */
83 IA64_OPND_IBR_R3
, /* ibr[reg] */
84 IA64_OPND_MR3
, /* memory at addr of third register # */
85 IA64_OPND_MSR_R3
, /* msr[reg] */
86 IA64_OPND_PKR_R3
, /* pkr[reg] */
87 IA64_OPND_PMC_R3
, /* pmc[reg] */
88 IA64_OPND_PMD_R3
, /* pmd[reg] */
89 IA64_OPND_RR_R3
, /* rr[reg] */
91 /* immediate operands: */
92 IA64_OPND_CCNT5
, /* 5-bit count (31 - bits 20-24) */
93 IA64_OPND_CNT2a
, /* 2-bit count (1 + bits 27-28) */
94 IA64_OPND_CNT2b
, /* 2-bit count (bits 27-28): 1, 2, 3 */
95 IA64_OPND_CNT2c
, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
96 IA64_OPND_CNT5
, /* 5-bit count (bits 14-18) */
97 IA64_OPND_CNT6
, /* 6-bit count (bits 27-32) */
98 IA64_OPND_CPOS6a
, /* 6-bit count (63 - bits 20-25) */
99 IA64_OPND_CPOS6b
, /* 6-bit count (63 - bits 14-19) */
100 IA64_OPND_CPOS6c
, /* 6-bit count (63 - bits 31-36) */
101 IA64_OPND_IMM1
, /* signed 1-bit immediate (bit 36) */
102 IA64_OPND_IMMU2
, /* unsigned 2-bit immediate (bits 13-14) */
103 IA64_OPND_IMMU7a
, /* unsigned 7-bit immediate (bits 13-19) */
104 IA64_OPND_IMMU7b
, /* unsigned 7-bit immediate (bits 20-26) */
105 IA64_OPND_SOF
, /* 8-bit stack frame size */
106 IA64_OPND_SOL
, /* 8-bit size of locals */
107 IA64_OPND_SOR
, /* 6-bit number of rotating registers (scaled by 8) */
108 IA64_OPND_IMM8
, /* signed 8-bit immediate (bits 13-19 & 36) */
109 IA64_OPND_IMM8U4
, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
110 IA64_OPND_IMM8M1
, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
111 IA64_OPND_IMM8M1U4
, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
112 IA64_OPND_IMM8M1U8
, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
113 IA64_OPND_IMMU9
, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
114 IA64_OPND_IMM9a
, /* signed 9-bit immediate (bits 6-12, 27, 36) */
115 IA64_OPND_IMM9b
, /* signed 9-bit immediate (bits 13-19, 27, 36) */
116 IA64_OPND_IMM14
, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
117 IA64_OPND_IMM17
, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
118 IA64_OPND_IMMU21
, /* unsigned 21-bit immediate (bits 6-25, 36) */
119 IA64_OPND_IMM22
, /* signed 22-bit immediate (bits 13-19, 22-36) */
120 IA64_OPND_IMMU24
, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
121 IA64_OPND_IMM44
, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
122 IA64_OPND_IMMU62
, /* unsigned 62-bit immediate */
123 IA64_OPND_IMMU64
, /* unsigned 64-bit immediate (lotsa bits...) */
124 IA64_OPND_INC3
, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
125 IA64_OPND_LEN4
, /* 4-bit count (bits 27-30 + 1) */
126 IA64_OPND_LEN6
, /* 6-bit count (bits 27-32 + 1) */
127 IA64_OPND_MBTYPE4
, /* 4-bit mux type (bits 20-23) */
128 IA64_OPND_MHTYPE8
, /* 8-bit mux type (bits 20-27) */
129 IA64_OPND_POS6
, /* 6-bit count (bits 14-19) */
130 IA64_OPND_TAG13
, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
131 IA64_OPND_TAG13b
, /* signed 13-bit tag (ip + 16*bits 24-32) */
132 IA64_OPND_TGT25
, /* signed 25-bit (ip + 16*bits 6-25, 36) */
133 IA64_OPND_TGT25b
, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
134 IA64_OPND_TGT25c
, /* signed 25-bit (ip + 16*bits 13-32, 36) */
135 IA64_OPND_TGT64
, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
137 IA64_OPND_COUNT
/* # of operand types (MUST BE LAST!) */
140 enum ia64_dependency_mode
147 enum ia64_dependency_semantics
158 enum ia64_resource_specifier
163 IA64_RS_AR
, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
164 IA64_RS_ARb
, /* 48-63, 112-127 */
170 IA64_RS_CR
, /* 3-7,10-15,18,26-63,75-79,82-127 */
177 IA64_RS_INSERVICE
, /* CR[EOI] or CR[IVR] */
186 IA64_RS_ARX
, /* ARs not in RS_AR or RS_ARb */
187 IA64_RS_CRX
, /* CRs not in RS_CR */
188 IA64_RS_PSR
, /* PSR bits */
189 IA64_RS_RSE
, /* implementation-specific RSE resources */
193 enum ia64_rse_resource
195 IA64_RSE_N_STACKED_PHYS
,
200 IA64_RSE_RNATBITINDEX
,
205 /* Information about a given resource dependency */
206 struct ia64_dependency
208 /* Name of the resource */
210 /* Does this dependency need further specification? */
211 enum ia64_resource_specifier specifier
;
212 /* Mode of dependency */
213 enum ia64_dependency_mode mode
;
214 /* Dependency semantics */
215 enum ia64_dependency_semantics semantics
;
216 /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
217 #define REG_NONE (-1)
219 /* Special info on semantics */
223 /* Two arrays of indexes into the ia64_dependency table.
224 chks are dependencies to check for conflicts when an opcode is
225 encountered; regs are dependencies to register (mark as used) when an
226 opcode is used. chks correspond to readers (RAW) or writers (WAW or
227 WAR) of a resource, while regs correspond to writers (RAW or WAW) and
228 readers (WAR) of a resource. */
229 struct ia64_opcode_dependency
232 const unsigned short *chks
;
234 const unsigned short *regs
;
237 /* encode/extract the note/index for a dependency */
238 #define RDEP(N,X) (((N)<<11)|(X))
239 #define NOTE(X) (((X)>>11)&0x1F)
240 #define DEP(X) ((X)&0x7FF)
242 /* A template descriptor describes the execution units that are active
243 for each of the three slots. It also specifies the location of
244 instruction group boundaries that may be present between two slots. */
245 struct ia64_templ_desc
247 int group_boundary
; /* 0=no boundary, 1=between slot 0 & 1, etc. */
248 enum ia64_unit exec_unit
[3];
252 /* The opcode table is an array of struct ia64_opcode. */
256 /* The opcode name. */
259 /* The type of the instruction: */
260 enum ia64_insn_type type
;
262 /* Number of output operands: */
265 /* The opcode itself. Those bits which will be filled in with
266 operands are zeroes. */
269 /* The opcode mask. This is used by the disassembler. This is a
270 mask containing ones indicating those bits which must match the
271 opcode field, and zeroes indicating those bits which need not
272 match (and are presumably filled in by operands). */
275 /* An array of operand codes. Each code is an index into the
276 operand table. They appear in the order which the operands must
277 appear in assembly code, and are terminated by a zero. */
278 enum ia64_opnd operands
[5];
280 /* One bit flags for the opcode. These are primarily used to
281 indicate specific processors and environments support the
282 instructions. The defined values are listed below. */
285 /* Used by ia64_find_next_opcode (). */
288 /* Opcode dependencies. */
289 const struct ia64_opcode_dependency
*dependencies
;
292 /* Values defined for the flags field of a struct ia64_opcode. */
294 #define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
295 #define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
296 #define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
297 #define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
298 #define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
299 #define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
300 #define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
301 #define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
302 #define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
303 #define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
304 #define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
306 /* A macro to extract the major opcode from an instruction. */
307 #define IA64_OP(i) (((i) >> 37) & 0xf)
309 enum ia64_operand_class
311 IA64_OPND_CLASS_CST
, /* constant */
312 IA64_OPND_CLASS_REG
, /* register */
313 IA64_OPND_CLASS_IND
, /* indirect register */
314 IA64_OPND_CLASS_ABS
, /* absolute value */
315 IA64_OPND_CLASS_REL
, /* IP-relative value */
318 /* The operands table is an array of struct ia64_operand. */
322 enum ia64_operand_class
class;
324 /* Set VALUE as the operand bits for the operand of type SELF in the
325 instruction pointed to by CODE. If an error occurs, *CODE is not
326 modified and the returned string describes the cause of the
327 error. If no error occurs, NULL is returned. */
328 const char *(*insert
) (const struct ia64_operand
*self
, ia64_insn value
,
331 /* Extract the operand bits for an operand of type SELF from
332 instruction CODE store them in *VALUE. If an error occurs, the
333 cause of the error is described by the string returned. If no
334 error occurs, NULL is returned. */
335 const char *(*extract
) (const struct ia64_operand
*self
, ia64_insn code
,
338 /* A string whose meaning depends on the operand class. */
344 /* The number of bits in the operand. */
347 /* How far the operand is left shifted in the instruction. */
350 field
[4]; /* no operand has more than this many bit-fields */
354 const char *desc
; /* brief description */
357 /* Values defined for the flags field of a struct ia64_operand. */
359 /* Disassemble as signed decimal (instead of hex): */
360 #define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
361 /* Disassemble as unsigned decimal (instead of hex): */
362 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
364 extern const struct ia64_templ_desc ia64_templ_desc
[16];
366 /* The tables are sorted by major opcode number and are otherwise in
367 the order in which the disassembler should consider instructions. */
368 extern struct ia64_opcode ia64_opcodes_a
[];
369 extern struct ia64_opcode ia64_opcodes_i
[];
370 extern struct ia64_opcode ia64_opcodes_m
[];
371 extern struct ia64_opcode ia64_opcodes_b
[];
372 extern struct ia64_opcode ia64_opcodes_f
[];
373 extern struct ia64_opcode ia64_opcodes_d
[];
376 extern struct ia64_opcode
*ia64_find_opcode (const char *name
);
377 extern struct ia64_opcode
*ia64_find_next_opcode (struct ia64_opcode
*ent
);
379 extern struct ia64_opcode
*ia64_dis_opcode (ia64_insn insn
,
380 enum ia64_insn_type type
);
382 extern void ia64_free_opcode (struct ia64_opcode
*ent
);
383 extern const struct ia64_dependency
*ia64_find_dependency (int index
);
385 /* To avoid circular library dependencies, this array is implemented
386 in bfd/cpu-ia64-opc.c: */
387 extern const struct ia64_operand elf64_ia64_operands
[IA64_OPND_COUNT
];
389 #endif /* opcode_ia64_h */