include/opcode/m68k.h

   1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
   3    2003, 2004 Free Software Foundation, Inc.
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    1, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 /* These are used as bit flags for the arch field in the m68k_opcode
  23    structure.  */
  24 #define _m68k_undef  0
  25 #define m68000   0x001
  26 #define m68008   m68000 /* Synonym for -m68000.  otherwise unused.  */
  27 #define m68010   0x002
  28 #define m68020   0x004
  29 #define m68030   0x008
  30 #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
  31                            gas will deal with the few differences.  */
  32 #define m68040   0x010
  33 /* There is no 68050.  */
  34 #define m68060   0x020
  35 #define m68881   0x040
  36 #define m68882   m68881 /* Synonym for -m68881.  otherwise unused.  */
  37 #define m68851   0x080
  38 #define cpu32    0x100          /* e.g., 68332 */
  39
  40 #define mcfmac   0x200          /* ColdFire MAC. */
  41 #define mcfemac  0x400          /* ColdFire EMAC. */
  42 #define cfloat   0x800          /* ColdFire FPU.  */
  43 #define mcfhwdiv 0x1000         /* ColdFire hardware divide.  */
  44
  45 #define mcfisa_a 0x2000         /* ColdFire ISA_A.  */
  46 #define mcfisa_aa 0x4000        /* ColdFire ISA_A+.  */
  47 #define mcfisa_b 0x8000         /* ColdFire ISA_B.  */
  48 #define mcfusp   0x10000        /* ColdFire USP instructions.  */
  49
  50 #define mcf5200  0x20000
  51 #define mcf5206e 0x40000
  52 #define mcf521x  0x80000
  53 #define mcf5249  0x100000
  54 #define mcf528x  0x200000
  55 #define mcf5307  0x400000
  56 #define mcf5407  0x800000
  57 #define mcf5470  0x1000000
  58 #define mcf5480  0x2000000
  59
  60  /* Handy aliases.  */
  61 #define m68040up   (m68040 | m68060)
  62 #define m68030up   (m68030 | m68040up)
  63 #define m68020up   (m68020 | m68030up)
  64 #define m68010up   (m68010 | cpu32 | m68020up)
  65 #define m68000up   (m68000 | m68010up)
  66
  67 #define mfloat  (m68881 | m68882 | m68040 | m68060)
  68 #define mmmu    (m68851 | m68030 | m68040 | m68060)
  69
  70 /* The structure used to hold information for an opcode.  */
  71
  72 struct m68k_opcode
  73 {
  74   /* The opcode name.  */
  75   const char *name;
  76   /* The opcode itself.  */
  77   unsigned long opcode;
  78   /* The mask used by the disassembler.  */
  79   unsigned long match;
  80   /* The arguments.  */
  81   const char *args;
  82   /* The architectures which support this opcode.  */
  83   unsigned int arch;
  84 };
  85
  86 /* The structure used to hold information for an opcode alias.  */
  87
  88 struct m68k_opcode_alias
  89 {
  90   /* The alias name.  */
  91   const char *alias;
  92   /* The instruction for which this is an alias.  */
  93   const char *primary;
  94 };
  95
  96 /* We store four bytes of opcode for all opcodes because that is the
  97    most any of them need.  The actual length of an instruction is
  98    always at least 2 bytes, and is as much longer as necessary to hold
  99    the operands it has.
 100
 101    The match field is a mask saying which bits must match particular
 102    opcode in order for an instruction to be an instance of that
 103    opcode.
 104
 105    The args field is a string containing two characters for each
 106    operand of the instruction.  The first specifies the kind of
 107    operand; the second, the place it is stored.  */
 108
 109 /* Kinds of operands:
 110    Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
 111
 112    D  data register only.  Stored as 3 bits.
 113    A  address register only.  Stored as 3 bits.
 114    a  address register indirect only.  Stored as 3 bits.
 115    R  either kind of register.  Stored as 4 bits.
 116    r  either kind of register indirect only.  Stored as 4 bits.
 117       At the moment, used only for cas2 instruction.
 118    F  floating point coprocessor register only.   Stored as 3 bits.
 119    O  an offset (or width): immediate data 0-31 or data register.
 120       Stored as 6 bits in special format for BF... insns.
 121    +  autoincrement only.  Stored as 3 bits (number of the address register).
 122    -  autodecrement only.  Stored as 3 bits (number of the address register).
 123    Q  quick immediate data.  Stored as 3 bits.
 124       This matches an immediate operand only when value is in range 1 .. 8.
 125    M  moveq immediate data.  Stored as 8 bits.
 126       This matches an immediate operand only when value is in range -128..127
 127    T  trap vector immediate data.  Stored as 4 bits.
 128
 129    k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
 130       a three bit register offset, depending on the field type.
 131
 132    #  immediate data.  Stored in special places (b, w or l)
 133       which say how many bits to store.
 134    ^  immediate data for floating point instructions.   Special places
 135       are offset by 2 bytes from '#'...
 136    B  pc-relative address, converted to an offset
 137       that is treated as immediate data.
 138    d  displacement and register.  Stores the register as 3 bits
 139       and stores the displacement in the entire second word.
 140
 141    C  the CCR.  No need to store it; this is just for filtering validity.
 142    S  the SR.  No need to store, just as with CCR.
 143    U  the USP.  No need to store, just as with CCR.
 144    E  the MAC ACC.  No need to store, just as with CCR.
 145    e  the EMAC ACC[0123].
 146    G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
 147    g  the EMAC ACCEXT{01,23}.
 148    H  the MASK.  No need to store, just as with CCR.
 149    i  the MAC/EMAC scale factor.
 150
 151    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
 152       extracted from the 'd' field of word one, which means that an extended
 153       coprocessor opcode can be skipped using the 'i' place, if needed.
 154
 155    s  System Control register for the floating point coprocessor.
 156
 157    J  Misc register for movec instruction, stored in 'j' format.
 158         Possible values:
 159         0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
 160         0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
 161         0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
 162         0x003   TC      MMU Translation Control         [60, 40]
 163         0x004   ITT0    Instruction Transparent
 164                                 Translation reg 0       [60, 40]
 165         0x005   ITT1    Instruction Transparent
 166                                 Translation reg 1       [60, 40]
 167         0x006   DTT0    Data Transparent
 168                                 Translation reg 0       [60, 40]
 169         0x007   DTT1    Data Transparent
 170                                 Translation reg 1       [60, 40]
 171         0x008   BUSCR   Bus Control Register            [60]
 172         0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
 173         0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
 174         0x802   CAAR    Cache Address Register          [        30, 20]
 175         0x803   MSP     Master Stack Pointer            [    40, 30, 20]
 176         0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
 177         0x805   MMUSR   MMU Status reg                  [    40]
 178         0x806   URP     User Root Pointer               [60, 40]
 179         0x807   SRP     Supervisor Root Pointer         [60, 40]
 180         0x808   PCR     Processor Configuration reg     [60]
 181         0xC00   ROMBAR  ROM Base Address Register       [520X]
 182         0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
 183         0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
 184         0xC0F   MBAR0   RAM Base Address Register 0     [520X]
 185         0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
 186         0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
 187
 188     L  Register list of the type d0-d7/a0-a7 etc.
 189        (New!  Improved!  Can also hold fp0-fp7, as well!)
 190        The assembler tries to see if the registers match the insn by
 191        looking at where the insn wants them stored.
 192
 193     l  Register list like L, but with all the bits reversed.
 194        Used for going the other way. . .
 195
 196     c  cache identifier which may be "nc" for no cache, "ic"
 197        for instruction cache, "dc" for data cache, or "bc"
 198        for both caches.  Used in cinv and cpush.  Always
 199        stored in position "d".
 200
 201     u  Any register, with ``upper'' or ``lower'' specification.  Used
 202        in the mac instructions with size word.
 203
 204  The remainder are all stored as 6 bits using an address mode and a
 205  register number; they differ in which addressing modes they match.
 206
 207    *  all                                       (modes 0-6,7.0-4)
 208    ~  alterable memory                          (modes 2-6,7.0,7.1)
 209                                                 (not 0,1,7.2-4)
 210    %  alterable                                 (modes 0-6,7.0,7.1)
 211                                                 (not 7.2-4)
 212    ;  data                                      (modes 0,2-6,7.0-4)
 213                                                 (not 1)
 214    @  data, but not immediate                   (modes 0,2-6,7.0-3)
 215                                                 (not 1,7.4)
 216    !  control                                   (modes 2,5,6,7.0-3)
 217                                                 (not 0,1,3,4,7.4)
 218    &  alterable control                         (modes 2,5,6,7.0,7.1)
 219                                                 (not 0,1,7.2-4)
 220    $  alterable data                            (modes 0,2-6,7.0,7.1)
 221                                                 (not 1,7.2-4)
 222    ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
 223                                                 (not 1,3,4,7.2-4)
 224    /  control, or data register                 (modes 0,2,5,6,7.0-3)
 225                                                 (not 1,3,4,7.4)
 226    >  *save operands                            (modes 2,4,5,6,7.0,7.1)
 227                                                 (not 0,1,3,7.2-4)
 228    <  *restore operands                         (modes 2,3,5,6,7.0-3)
 229                                                 (not 0,1,4,7.4)
 230
 231    coldfire move operands:
 232    m                                            (modes 0-4)
 233    n                                            (modes 5,7.2)
 234    o                                            (modes 6,7.0,7.1,7.3,7.4)
 235    p                                            (modes 0-5)
 236
 237    coldfire bset/bclr/btst/mulsl/mulul operands:
 238    q                                            (modes 0,2-5)
 239    v                                            (modes 0,2-5,7.0,7.1)
 240    b                                            (modes 0,2-5,7.2)
 241    w                                            (modes 2-5,7.2)
 242    y                                            (modes 2,5)
 243    z                                            (modes 2,5,7.2)
 244    x  mov3q immediate operand.
 245    4                                            (modes 2,3,4,5)
 246   */
 247
 248 /* For the 68851:  */
 249 /* I didn't use much imagination in choosing the
 250    following codes, so many of them aren't very
 251    mnemonic. -rab
 252
 253    0  32 bit pmmu register
 254         Possible values:
 255         000     TC      Translation Control Register (68030, 68851)
 256
 257    1  16 bit pmmu register
 258         111     AC      Access Control (68851)
 259
 260    2  8 bit pmmu register
 261         100     CAL     Current Access Level (68851)
 262         101     VAL     Validate Access Level (68851)
 263         110     SCC     Stack Change Control (68851)
 264
 265    3  68030-only pmmu registers (32 bit)
 266         010     TT0     Transparent Translation reg 0
 267                         (aka Access Control reg 0 -- AC0 -- on 68ec030)
 268         011     TT1     Transparent Translation reg 1
 269                         (aka Access Control reg 1 -- AC1 -- on 68ec030)
 270
 271    W  wide pmmu registers
 272         Possible values:
 273         001     DRP     Dma Root Pointer (68851)
 274         010     SRP     Supervisor Root Pointer (68030, 68851)
 275         011     CRP     Cpu Root Pointer (68030, 68851)
 276
 277    f    function code register (68030, 68851)
 278         0       SFC
 279         1       DFC
 280
 281    V    VAL register only (68851)
 282
 283    X    BADx, BACx (16 bit)
 284         100     BAD     Breakpoint Acknowledge Data (68851)
 285         101     BAC     Breakpoint Acknowledge Control (68851)
 286
 287    Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
 288    Z    PCSR (68851)
 289
 290    |    memory          (modes 2-6, 7.*)
 291
 292    t  address test level (68030 only)
 293       Stored as 3 bits, range 0-7.
 294       Also used for breakpoint instruction now.
 295
 296 */
 297
 298 /* Places to put an operand, for non-general operands:
 299    Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
 300
 301    s  source, low bits of first word.
 302    d  dest, shifted 9 in first word
 303    1  second word, shifted 12
 304    2  second word, shifted 6
 305    3  second word, shifted 0
 306    4  third word, shifted 12
 307    5  third word, shifted 6
 308    6  third word, shifted 0
 309    7  second word, shifted 7
 310    8  second word, shifted 10
 311    9  second word, shifted 5
 312    D  store in both place 1 and place 3; for divul and divsl.
 313    B  first word, low byte, for branch displacements
 314    W  second word (entire), for branch displacements
 315    L  second and third words (entire), for branch displacements
 316       (also overloaded for move16)
 317    b  second word, low byte
 318    w  second word (entire) [variable word/long branch offset for dbra]
 319    W  second word (entire) (must be signed 16 bit value)
 320    l  second and third word (entire)
 321    g  variable branch offset for bra and similar instructions.
 322       The place to store depends on the magnitude of offset.
 323    t  store in both place 7 and place 8; for floating point operations
 324    c  branch offset for cpBcc operations.
 325       The place to store is word two if bit six of word one is zero,
 326       and words two and three if bit six of word one is one.
 327    i  Increment by two, to skip over coprocessor extended operands.   Only
 328       works with the 'I' format.
 329    k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
 330       Also used for dynamic fmovem instruction.
 331    C  floating point coprocessor constant - 7 bits.  Also used for static
 332       K-factors...
 333    j  Movec register #, stored in 12 low bits of second word.
 334    m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
 335       and remaining 3 bits of register shifted 9 bits in first word.
 336       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 337       Use with `R' or `u' format.
 338    n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
 339       with MSB shifted 6 bits in first word and remaining 3 bits of
 340       register shifted 9 bits in first word.  No upper/lower
 341       indication is done.)  Use with `R' or `u' format.
 342    o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
 343       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 344       Use with `R' or `u' format.
 345    M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
 346       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 347       `R' or `u' format.
 348    N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
 349       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 350       `R' or `u' format.
 351    h  shift indicator (scale factor), 1 bit shifted 10 in second word
 352
 353  Places to put operand, for general operands:
 354    d  destination, shifted 6 bits in first word
 355    b  source, at low bit of first word, and immediate uses one byte
 356    w  source, at low bit of first word, and immediate uses two bytes
 357    l  source, at low bit of first word, and immediate uses four bytes
 358    s  source, at low bit of first word.
 359       Used sometimes in contexts where immediate is not allowed anyway.
 360    f  single precision float, low bit of 1st word, immediate uses 4 bytes
 361    F  double precision float, low bit of 1st word, immediate uses 8 bytes
 362    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
 363    p  packed float, low bit of 1st word, immediate uses 12 bytes
 364    G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
 365    H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
 366    F  EMAC ACCx
 367    f  EMAC ACCy
 368    I  MAC/EMAC scale factor
 369    /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
 370    ]  first word, bit 10
 371 */
 372
 373 extern const struct m68k_opcode m68k_opcodes[];
 374 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
 375
 376 extern const int m68k_numopcodes, m68k_numaliases;
 377
 378 /* end of m68k-opcode.h */