include/opcode/m68k.h

   1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
   2    Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  19 02111-1307, USA.  */
  20
  21 /* These are used as bit flags for the arch field in the m68k_opcode
  22    structure.  */
  23 #define _m68k_undef  0
  24 #define m68000  0x001
  25 #define m68008  m68000 /* synonym for -m68000.  otherwise unused. */
  26 #define m68010  0x002
  27 #define m68020  0x004
  28 #define m68030  0x008
  29 #define m68ec030 m68030 /* similar enough to -m68030 to ignore differences;
  30                            gas will deal with the few differences.  */
  31 #define m68040  0x010
  32 /* there is no 68050 */
  33 #define m68060  0x020
  34 #define m68881  0x040
  35 #define m68882  m68881 /* synonym for -m68881.  otherwise unused. */
  36 #define m68851  0x080
  37 #define cpu32   0x100   /* e.g., 68332 */
  38 #define mcf5200 0x200
  39 /* start-sanitize-coldfire */
  40 #define mcfmac  0x400   /* coldfire multiply accumlate module */
  41 #define mcfdiv  0x800   /* coldfire integer division module */
  42 /* end-sanitize-coldfire */
  43
  44  /* handy aliases */
  45 #define m68040up  (m68040 | m68060)
  46 #define m68030up  (m68030 | m68040up)
  47 #define m68020up  (m68020 | m68030up)
  48 #define m68010up  (m68010 | cpu32 | m68020up)
  49 #define m68000up  (m68000 | m68010up)
  50
  51 #define mfloat  (m68881 | m68882 | m68040 | m68060)
  52 #define mmmu    (m68851 | m68030 | m68040 | m68060)
  53
  54 /* The structure used to hold information for an opcode.  */
  55
  56 struct m68k_opcode
  57 {
  58   /* The opcode name.  */
  59   const char *name;
  60   /* The opcode itself.  */
  61   unsigned long opcode;
  62   /* The mask used by the disassembler.  */
  63   unsigned long match;
  64   /* The arguments.  */
  65   const char *args;
  66   /* The architectures which support this opcode.  */
  67   unsigned int arch;
  68 };
  69
  70 /* The structure used to hold information for an opcode alias.  */
  71
  72 struct m68k_opcode_alias
  73 {
  74   /* The alias name.  */
  75   const char *alias;
  76   /* The instruction for which this is an alias.  */
  77   const char *primary;
  78 };
  79
  80 /* We store four bytes of opcode for all opcodes because that is the
  81    most any of them need.  The actual length of an instruction is
  82    always at least 2 bytes, and is as much longer as necessary to hold
  83    the operands it has.
  84
  85    The match field is a mask saying which bits must match particular
  86    opcode in order for an instruction to be an instance of that
  87    opcode.
  88
  89    The args field is a string containing two characters for each
  90    operand of the instruction.  The first specifies the kind of
  91    operand; the second, the place it is stored.  */
  92
  93 /* Kinds of operands:
  94    Characters used: AaBCcDdFfIJkLlMOQRrSsTtUVWXYZ0123|*~%;@!&$?/#^+-
  95
  96    D  data register only.  Stored as 3 bits.
  97    A  address register only.  Stored as 3 bits.
  98    a  address register indirect only.  Stored as 3 bits.
  99    R  either kind of register.  Stored as 4 bits.
 100    r  either kind of register indirect only.  Stored as 4 bits.
 101       At the moment, used only for cas2 instruction.
 102    F  floating point coprocessor register only.   Stored as 3 bits.
 103    O  an offset (or width): immediate data 0-31 or data register.
 104       Stored as 6 bits in special format for BF... insns.
 105    +  autoincrement only.  Stored as 3 bits (number of the address register).
 106    -  autodecrement only.  Stored as 3 bits (number of the address register).
 107    Q  quick immediate data.  Stored as 3 bits.
 108       This matches an immediate operand only when value is in range 1 .. 8.
 109    M  moveq immediate data.  Stored as 8 bits.
 110       This matches an immediate operand only when value is in range -128..127
 111    T  trap vector immediate data.  Stored as 4 bits.
 112
 113    k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
 114       a three bit register offset, depending on the field type.
 115
 116    #  immediate data.  Stored in special places (b, w or l)
 117       which say how many bits to store.
 118    ^  immediate data for floating point instructions.   Special places
 119       are offset by 2 bytes from '#'...
 120    B  pc-relative address, converted to an offset
 121       that is treated as immediate data.
 122    d  displacement and register.  Stores the register as 3 bits
 123       and stores the displacement in the entire second word.
 124
 125    C  the CCR.  No need to store it; this is just for filtering validity.
 126    S  the SR.  No need to store, just as with CCR.
 127    U  the USP.  No need to store, just as with CCR.
 128
 129    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
 130       extracted from the 'd' field of word one, which means that an extended
 131       coprocessor opcode can be skipped using the 'i' place, if needed.
 132
 133    s  System Control register for the floating point coprocessor.
 134
 135    J  Misc register for movec instruction, stored in 'j' format.
 136         Possible values:
 137         0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
 138         0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
 139         0x002   CACR    Cache Control Register          [60, 40, 30, 20]
 140         0x003   TC      MMU Translation Control         [60, 40]
 141         0x004   ITT0    Instruction Transparent
 142                                 Translation reg 0       [60, 40]
 143         0x005   ITT1    Instruction Transparent
 144                                 Translation reg 1       [60, 40]
 145         0x006   DTT0    Data Transparent
 146                                 Translation reg 0       [60, 40]
 147         0x007   DTT1    Data Transparent
 148                                 Translation reg 1       [60, 40]
 149         0x008   BUSCR   Bus Control Register            [60]
 150         0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
 151         0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10]
 152         0x802   CAAR    Cache Address Register          [        30, 20]
 153         0x803   MSP     Master Stack Pointer            [    40, 30, 20]
 154         0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
 155         0x805   MMUSR   MMU Status reg                  [    40]
 156         0x806   URP     User Root Pointer               [60, 40]
 157         0x807   SRP     Supervisor Root Pointer         [60, 40]
 158         0x808   PCR     Processor Configuration reg     [60]
 159         0xC00   ROMBAR  ROM Base Address Register       [520X]
 160         0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
 161         0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
 162         0xC0F   MBAR0   RAM Base Address Register 0     [520X]
 163
 164     L  Register list of the type d0-d7/a0-a7 etc.
 165        (New!  Improved!  Can also hold fp0-fp7, as well!)
 166        The assembler tries to see if the registers match the insn by
 167        looking at where the insn wants them stored.
 168
 169     l  Register list like L, but with all the bits reversed.
 170        Used for going the other way. . .
 171
 172     c  cache identifier which may be "nc" for no cache, "ic"
 173        for instruction cache, "dc" for data cache, or "bc"
 174        for both caches.  Used in cinv and cpush.  Always
 175        stored in position "d".
 176
 177  The remainder are all stored as 6 bits using an address mode and a
 178  register number; they differ in which addressing modes they match.
 179
 180    *  all                                       (modes 0-6,7.*)
 181    ~  alterable memory                          (modes 2-6,7.0,7.1)
 182                                                 (not 0,1,7.~)
 183    %  alterable                                 (modes 0-6,7.0,7.1)
 184                                                 (not 7.~)
 185    ;  data                                      (modes 0,2-6,7.*)(not 1)
 186    @  data, but not immediate                   (modes 0,2-6,7.? ? ?)
 187                                                 (not 1,7.?)
 188                                                 This may really be ;,
 189                                                 the 68020 book says it is
 190    !  control                                   (modes 2,5,6,7.*-)
 191                                                 (not 0,1,3,4,7.4)
 192    &  alterable control                         (modes 2,5,6,7.0,7.1)
 193                                                 (not 0,1,7.? ? ?)
 194    $  alterable data                            (modes 0,2-6,7.0,7.1)
 195                                                 (not 1,7.~)
 196    ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
 197                                                 (not 1,3,4,7.~)
 198    /  control, or data register                 (modes 0,2,5,6,7.0,7.1,7.2,7.3)
 199                                                 (not 1,3,4,7.4)
 200    `  control, plus pre-dec, not simple indir.  (modes 4,5,6,7.*-)
 201                                                 (not 0,1,2,3,7.4)
 202    >  *save operands                            (modes 2,4,5,6,7.0,7.1)
 203    <  *restore operands                         (modes 2,3,5,6,7.0,7.1,7.2,7.3)
 204
 205    coldfire move operands:
 206    m                                            (modes 0-4)
 207    n                                            (modes 5,7.2)
 208    o                                            (modes 6,7.0,7.1,7.3)
 209    p                                            (modes 0-5)
 210
 211    coldfire bset/bclr/btst operands:
 212    q                                            (modes 0,2-5)
 213    v                                            (modes 0,2-5,7.0,7.1)
 214 */
 215
 216 /* For the 68851: */
 217 /*
 218    I didn't use much imagination in choosing the
 219    following codes, so many of them aren't very
 220    mnemonic. -rab
 221
 222    0  32 bit pmmu register
 223         Possible values:
 224         000     TC      Translation Control Register (68030, 68851)
 225
 226    1  16 bit pmmu register
 227         111     AC      Access Control (68851)
 228
 229    2  8 bit pmmu register
 230         100     CAL     Current Access Level (68851)
 231         101     VAL     Validate Access Level (68851)
 232         110     SCC     Stack Change Control (68851)
 233
 234    3  68030-only pmmu registers (32 bit)
 235         010     TT0     Transparent Translation reg 0
 236                         (aka Access Control reg 0 -- AC0 -- on 68ec030)
 237         011     TT1     Transparent Translation reg 1
 238                         (aka Access Control reg 1 -- AC1 -- on 68ec030)
 239
 240    W  wide pmmu registers
 241         Possible values:
 242         001     DRP     Dma Root Pointer (68851)
 243         010     SRP     Supervisor Root Pointer (68030, 68851)
 244         011     CRP     Cpu Root Pointer (68030, 68851)
 245
 246    f    function code register (68030, 68851)
 247         0       SFC
 248         1       DFC
 249
 250    V    VAL register only (68851)
 251
 252    X    BADx, BACx (16 bit)
 253         100     BAD     Breakpoint Acknowledge Data (68851)
 254         101     BAC     Breakpoint Acknowledge Control (68851)
 255
 256    Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
 257    Z    PCSR (68851)
 258
 259    |    memory          (modes 2-6, 7.*)
 260
 261    t  address test level (68030 only)
 262       Stored as 3 bits, range 0-7.
 263       Also used for breakpoint instruction now.
 264
 265 */
 266
 267 /* Places to put an operand, for non-general operands:
 268    s  source, low bits of first word.
 269    d  dest, shifted 9 in first word
 270    1  second word, shifted 12
 271    2  second word, shifted 6
 272    3  second word, shifted 0
 273    4  third word, shifted 12
 274    5  third word, shifted 6
 275    6  third word, shifted 0
 276    7  second word, shifted 7
 277    8  second word, shifted 10
 278    9  second word, shifted 5
 279    D  store in both place 1 and place 3; for divul and divsl.
 280    B  first word, low byte, for branch displacements
 281    W  second word (entire), for branch displacements
 282    L  second and third words (entire), for branch displacements
 283       (also overloaded for move16)
 284    b  second word, low byte
 285    w  second word (entire) [variable word/long branch offset for dbra]
 286    W  second word (entire) (must be signed 16 bit value)
 287    l  second and third word (entire)
 288    g  variable branch offset for bra and similar instructions.
 289       The place to store depends on the magnitude of offset.
 290    t  store in both place 7 and place 8; for floating point operations
 291    c  branch offset for cpBcc operations.
 292       The place to store is word two if bit six of word one is zero,
 293       and words two and three if bit six of word one is one.
 294    i  Increment by two, to skip over coprocessor extended operands.   Only
 295       works with the 'I' format.
 296    k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
 297       Also used for dynamic fmovem instruction.
 298    C  floating point coprocessor constant - 7 bits.  Also used for static
 299       K-factors...
 300    j  Movec register #, stored in 12 low bits of second word.
 301
 302  Places to put operand, for general operands:
 303    d  destination, shifted 6 bits in first word
 304    b  source, at low bit of first word, and immediate uses one byte
 305    w  source, at low bit of first word, and immediate uses two bytes
 306    l  source, at low bit of first word, and immediate uses four bytes
 307    s  source, at low bit of first word.
 308       Used sometimes in contexts where immediate is not allowed anyway.
 309    f  single precision float, low bit of 1st word, immediate uses 4 bytes
 310    F  double precision float, low bit of 1st word, immediate uses 8 bytes
 311    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
 312    p  packed float, low bit of 1st word, immediate uses 12 bytes
 313 */
 314
 315 extern const struct m68k_opcode m68k_opcodes[];
 316 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
 317
 318 extern const int m68k_numopcodes, m68k_numaliases;
 319
 320 /* end of m68k-opcode.h */