1 /* Table of opcodes for the Motorola M88k family.
2 Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010
3 Free Software Foundation, Inc.
5 This file is part of GDB and GAS.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 * Disassembler Instruction Table
25 * The first field of the table is the opcode field. If an opcode
26 * is specified which has any non-opcode bits on, a system error
27 * will occur when the system attempts the install it into the
28 * instruction table. The second parameter is a pointer to the
29 * instruction mnemonic. Each operand is specified by offset, width,
30 * and type. The offset is the bit number of the least significant
31 * bit of the operand with bit 0 being the least significant bit of
32 * the instruction. The width is the number of bits used to specify
33 * the operand. The type specifies the output format to be used for
34 * the operand. The valid formats are: register, register indirect,
35 * hex constant, and bit field specification. The last field is a
36 * pointer to the next instruction in the linked list. These pointers
37 * are initialized by init_disasm().
41 * Revision 1.0 11/08/85 Creation date
42 * 1.1 02/05/86 Updated instruction mnemonic table MD
43 * 1.2 06/16/86 Updated SIM_FLAGS for floating point
44 * 1.3 09/20/86 Updated for new encoding
45 * 05/11/89 R. Trawick adapted from Motorola disassembler
50 /* Define the number of bits in the primary opcode field of the instruction,
51 the destination field, the source 1 and source 2 fields. */
53 /* Size of opcode field. */
56 /* Size of destination. */
59 /* Size of source1. */
62 /* Size of source2. */
65 /* Number of registers. */
68 /* Type definitions. */
70 typedef unsigned int UINT
;
75 /* The next four equates define the priorities that the various classes
76 * of instructions have regarding writing results back into registers and
77 * signalling exceptions. */
79 /* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */
82 /* Integer priority. */
85 /* Floating point priority. */
88 /* Memory priority. */
91 /* Not applicable, instruction doesn't write to regs. */
94 /* Highest of these priorities. */
97 /* The instruction registers are an artificial mechanism to speed up
98 * simulator execution. In the real processor, an instruction register
99 * is 32 bits wide. In the simulator, the 32 bit instruction is kept in
100 * a structure field called rawop, and the instruction is partially decoded,
101 * and split into various fields and flags which make up the other fields
103 * The partial decode is done when the instructions are initially loaded
104 * into simulator memory. The simulator code memory is not an array of
105 * 32 bit words, but is an array of instruction register structures.
106 * Yes this wastes memory, but it executes much quicker.
117 /* Writeback priority. */
119 /* Immediate size. */
120 unsigned imm_flags
:2,
121 /* Register source 1 used. */
123 /* Register source 2 used. */
125 /* Register source/dest. used. */
129 /* Upper half word. */
133 /* Uses writeback slot. */
142 /* Scaled register. */
148 /* Pointer (returned by calloc) to segment. */
151 /* Base load address from file headers. */
152 unsigned long baseaddr
;
154 /* Ending address of segment. */
155 unsigned long endaddr
;
157 /* Segment control flags (none defined). */
161 #define MAXSEGS (10) /* max number of segment allowed */
162 #define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */
165 #define BRK_RD (0x01) /* break on memory read */
166 #define BRK_WR (0x02) /* break on memory write */
167 #define BRK_EXEC (0x04) /* break on execution */
168 #define BRK_CNT (0x08) /* break on terminal count */
173 /* Simulator instruction break down. */
174 struct IR_FIELDS opcode
;
176 /* Memory element break down. */
183 /* Size of each 32 bit memory model. */
184 #define MEMWRDSIZE (sizeof (struct mem_wrd))
186 extern struct mem_segs memory
[];
187 extern struct PROCESSOR m78000
;
192 /* Execute instruction pointer. */
194 /* Vector base register. */
196 /* Processor status register. */
205 /* Data address bus. */
208 /* Data registers. */
210 /* Max clocks before reg is available. */
212 /* Writeback priority of reg. */
214 /* Integer unit control regs. */
216 /* Floating point control regs. */
220 unsigned WORD scoreboard
,
223 /* Waiting for a jump instruction. */
227 /* Size of immediate field. */
233 /* Definitions for fields in psr. */
252 /* The 1 clock operations. */
292 #define XMEMBU LDHU+5
329 /* Control register manipulations. */
341 /* Floating point instructions. */
358 #define UEXT(src,off,wid) \
359 ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
361 #define SEXT(src,off,wid) \
362 (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
364 #define MAKE(src,off,wid) \
365 ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
367 #define opword(n) (unsigned long) (memaddr->mem.l)
369 /* Constants and masks. */
371 #define SFU0 0x80000000
372 #define SFU1 0x84000000
373 #define SFU7 0x9c000000
374 #define RRI10 0xf0000000
375 #define RRR 0xf4000000
376 #define SFUMASK 0xfc00ffe0
377 #define RRRMASK 0xfc00ffe0
378 #define RRI10MASK 0xfc00fc00
379 #define DEFMASK 0xfc000000
380 #define CTRL 0x0000f000
381 #define CTRLMASK 0xfc00f800
383 /* Operands types. */
392 /* Scaled register. */
394 /* Control register. */
396 /* Floating point control register. */
400 /* Extended register. */
406 /* Hashing specification. */
410 /* Structure templates. */
416 enum operand_type type
;
421 int ltncy
, /* latency (max number of clocks needed to execute). */
422 extime
, /* execution time (min number of clocks needed to execute). */
423 wb_pri
; /* writeback slot priority. */
424 unsigned op
:OP
, /* simulator version of opcode. */
425 imm_flags
:2, /* 10,16 or 26 bit immediate flags. */
426 rs1_used
:1, /* register source 1 used. */
427 rs2_used
:1, /* register source 2 used. */
428 rsd_used
:1, /* register source/dest used. */
429 c_flag
:1, /* complement. */
430 u_flag
:1, /* upper half word. */
431 n_flag
:1, /* execute next. */
432 wb_flag
:1, /* uses writeback slot. */
433 dest_64
:1, /* double precision dest. */
434 s1_64
:1, /* double precision source 1. */
435 s2_64
:1, /* double precision source 2. */
436 scale_flag
:1; /* register is scaled. */
439 typedef struct INSTRUCTAB
{
443 struct SIM_FLAGS flgs
;
447 #define NO_OPERAND {0,0,0}
449 extern const INSTAB instructions
[];
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