1 /* Table of opcodes for the Motorola M88k family.
2 Copyright 1989, 1990, 1991, 1993, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GDB and GAS.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 * Disassembler Instruction Table
24 * The first field of the table is the opcode field. If an opcode
25 * is specified which has any non-opcode bits on, a system error
26 * will occur when the system attempts the install it into the
27 * instruction table. The second parameter is a pointer to the
28 * instruction mnemonic. Each operand is specified by offset, width,
29 * and type. The offset is the bit number of the least significant
30 * bit of the operand with bit 0 being the least significant bit of
31 * the instruction. The width is the number of bits used to specify
32 * the operand. The type specifies the output format to be used for
33 * the operand. The valid formats are: register, register indirect,
34 * hex constant, and bit field specification. The last field is a
35 * pointer to the next instruction in the linked list. These pointers
36 * are initialized by init_disasm().
40 * Revision 1.0 11/08/85 Creation date
41 * 1.1 02/05/86 Updated instruction mnemonic table MD
42 * 1.2 06/16/86 Updated SIM_FLAGS for floating point
43 * 1.3 09/20/86 Updated for new encoding
44 * 05/11/89 R. Trawick adapted from Motorola disassembler
49 /* Define the number of bits in the primary opcode field of the instruction,
50 the destination field, the source 1 and source 2 fields. */
52 /* Size of opcode field. */
55 /* Size of destination. */
58 /* Size of source1. */
61 /* Size of source2. */
64 /* Number of registers. */
67 /* Type definitions. */
69 typedef unsigned int UINT
;
74 /* The next four equates define the priorities that the various classes
75 * of instructions have regarding writing results back into registers and
76 * signalling exceptions. */
78 /* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */
81 /* Integer priority. */
84 /* Floating point priority. */
87 /* Memory priority. */
90 /* Not applicable, instruction doesn't write to regs. */
93 /* Highest of these priorities. */
96 /* The instruction registers are an artificial mechanism to speed up
97 * simulator execution. In the real processor, an instruction register
98 * is 32 bits wide. In the simulator, the 32 bit instruction is kept in
99 * a structure field called rawop, and the instruction is partially decoded,
100 * and split into various fields and flags which make up the other fields
102 * The partial decode is done when the instructions are initially loaded
103 * into simulator memory. The simulator code memory is not an array of
104 * 32 bit words, but is an array of instruction register structures.
105 * Yes this wastes memory, but it executes much quicker.
116 /* Writeback priority. */
118 /* Immediate size. */
119 unsigned imm_flags
:2,
120 /* Register source 1 used. */
122 /* Register source 2 used. */
124 /* Register source/dest. used. */
128 /* Upper half word. */
132 /* Uses writeback slot. */
141 /* Scaled register. */
147 /* Pointer (returned by calloc) to segment. */
150 /* Base load address from file headers. */
151 unsigned long baseaddr
;
153 /* Ending address of segment. */
154 unsigned long endaddr
;
156 /* Segment control flags (none defined). */
160 #define MAXSEGS (10) /* max number of segment allowed */
161 #define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */
164 #define BRK_RD (0x01) /* break on memory read */
165 #define BRK_WR (0x02) /* break on memory write */
166 #define BRK_EXEC (0x04) /* break on execution */
167 #define BRK_CNT (0x08) /* break on terminal count */
172 /* Simulator instruction break down. */
173 struct IR_FIELDS opcode
;
175 /* Memory element break down. */
182 /* Size of each 32 bit memory model. */
183 #define MEMWRDSIZE (sizeof (struct mem_wrd))
185 extern struct mem_segs memory
[];
186 extern struct PROCESSOR m78000
;
191 /* Execute instruction pointer. */
193 /* Vector base register. */
195 /* Processor status register. */
204 /* Data address bus. */
207 /* Data registers. */
209 /* Max clocks before reg is available. */
211 /* Writeback priority of reg. */
213 /* Integer unit control regs. */
215 /* Floating point control regs. */
219 unsigned WORD scoreboard
,
222 /* Waiting for a jump instruction. */
226 /* Size of immediate field. */
232 /* Definitions for fields in psr. */
251 /* The 1 clock operations. */
291 #define XMEMBU LDHU+5
328 /* Control register manipulations. */
340 /* Floating point instructions. */
357 #define UEXT(src,off,wid) \
358 ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
360 #define SEXT(src,off,wid) \
361 (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
363 #define MAKE(src,off,wid) \
364 ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
366 #define opword(n) (unsigned long) (memaddr->mem.l)
368 /* Constants and masks. */
370 #define SFU0 0x80000000
371 #define SFU1 0x84000000
372 #define SFU7 0x9c000000
373 #define RRI10 0xf0000000
374 #define RRR 0xf4000000
375 #define SFUMASK 0xfc00ffe0
376 #define RRRMASK 0xfc00ffe0
377 #define RRI10MASK 0xfc00fc00
378 #define DEFMASK 0xfc000000
379 #define CTRL 0x0000f000
380 #define CTRLMASK 0xfc00f800
382 /* Operands types. */
391 /* Scaled register. */
393 /* Control register. */
395 /* Floating point control register. */
399 /* Extended register. */
405 /* Hashing specification. */
409 /* Structure templates. */
415 enum operand_type type
;
420 int ltncy
, /* latency (max number of clocks needed to execute). */
421 extime
, /* execution time (min number of clocks needed to execute). */
422 wb_pri
; /* writeback slot priority. */
423 unsigned op
:OP
, /* simulator version of opcode. */
424 imm_flags
:2, /* 10,16 or 26 bit immediate flags. */
425 rs1_used
:1, /* register source 1 used. */
426 rs2_used
:1, /* register source 2 used. */
427 rsd_used
:1, /* register source/dest used. */
428 c_flag
:1, /* complement. */
429 u_flag
:1, /* upper half word. */
430 n_flag
:1, /* execute next. */
431 wb_flag
:1, /* uses writeback slot. */
432 dest_64
:1, /* double precision dest. */
433 s1_64
:1, /* double precision source 1. */
434 s2_64
:1, /* double precision source 2. */
435 scale_flag
:1; /* register is scaled. */
438 typedef struct INSTRUCTAB
{
442 struct SIM_FLAGS flgs
;
446 #define NO_OPERAND {0,0,0}
448 extern const INSTAB instructions
[];
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