include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  21
  22 /* These are bit masks and shift counts to use to access the various
  23    fields of an instruction.  To retrieve the X field of an
  24    instruction, use the expression
  25         (i >> OP_SH_X) & OP_MASK_X
  26    To set the same field (to j), use
  27         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  28
  29    Make sure you use fields that are appropriate for the instruction,
  30    of course.
  31
  32    The 'i' format uses OP, RS, RT and IMMEDIATE.
  33
  34    The 'j' format uses OP and TARGET.
  35
  36    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  37
  38    The 'b' format uses OP, RS, RT and DELTA.
  39
  40    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  41
  42    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  43
  44    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  45    breakpoint instruction are not defined; Kane says the breakpoint
  46    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  47    only use ten bits).
  48
  49    The syscall instruction uses SYSCALL.
  50
  51    The general coprocessor instructions use COPZ.  */
  52
  53 #define OP_MASK_OP              0x3f
  54 #define OP_SH_OP                26
  55 #define OP_MASK_RS              0x1f
  56 #define OP_SH_RS                21
  57 #define OP_MASK_FMT             0x1f
  58 #define OP_SH_FMT               21
  59 #define OP_MASK_CODE            0x3ff
  60 #define OP_SH_CODE              16
  61 #define OP_MASK_RT              0x1f
  62 #define OP_SH_RT                16
  63 #define OP_MASK_FT              0x1f
  64 #define OP_SH_FT                16
  65 #define OP_MASK_CACHE           0x1f
  66 #define OP_SH_CACHE             16
  67 #define OP_MASK_RD              0x1f
  68 #define OP_SH_RD                11
  69 #define OP_MASK_FS              0x1f
  70 #define OP_SH_FS                11
  71 #define OP_MASK_SYSCALL         0xfffff
  72 #define OP_SH_SYSCALL           6
  73 #define OP_MASK_SHAMT           0x1f
  74 #define OP_SH_SHAMT             6
  75 #define OP_MASK_FD              0x1f
  76 #define OP_SH_FD                6
  77 #define OP_MASK_TARGET          0x3ffffff
  78 #define OP_SH_TARGET            0
  79 #define OP_MASK_COPZ            0x1ffffff
  80 #define OP_SH_COPZ              0
  81 #define OP_MASK_IMMEDIATE       0xffff
  82 #define OP_SH_IMMEDIATE         0
  83 #define OP_MASK_DELTA           0xffff
  84 #define OP_SH_DELTA             0
  85 #define OP_MASK_FUNCT           0x3f
  86 #define OP_SH_FUNCT             0
  87 #define OP_MASK_SPEC            0x3f
  88 #define OP_SH_SPEC              0
  89
  90 /* This structure holds information for a particular instruction.  */
  91
  92 struct mips_opcode
  93 {
  94   /* The name of the instruction.  */
  95   const char *name;
  96   /* A string describing the arguments for this instruction.  */
  97   const char *args;
  98   /* The basic opcode for the instruction.  When assembling, this
  99      opcode is modified by the arguments to produce the actual opcode
 100      that is used.  If pinfo is INSN_MACRO, then this is instead the
 101      ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
 102      etc.).  */
 103   unsigned long match;
 104   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 105      relevant portions of the opcode when disassembling.  If the
 106      actual opcode anded with the match field equals the opcode field,
 107      then we have found the correct instruction.  If pinfo is
 108      INSN_MACRO, then this field is the macro identifier.  */
 109   unsigned long mask;
 110   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 111      of bits describing the instruction, notably any relevant hazard
 112      information.  */
 113   unsigned long pinfo;
 114 };
 115
 116 /* These are the characters which may appears in the args field of an
 117    instruction.  They appear in the order in which the fields appear
 118    when the instruction is used.  Commas and parentheses in the args
 119    string are ignored when assembling, and written into the output
 120    when disassembling.
 121
 122    Each of these characters corresponds to a mask field defined above.
 123
 124    "<" 5 bit shift amount (OP_*_SHAMT)
 125    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 126    "a" 26 bit target address (OP_*_TARGET)
 127    "b" 5 bit base register (OP_*_RS)
 128    "c" 10 bit breakpoint code (OP_*_CODE)
 129    "d" 5 bit destination register specifier (OP_*_RD)
 130    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 131    "j" 16 bit signed immediate (OP_*_DELTA)
 132    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 133    "o" 16 bit signed offset (OP_*_DELTA)
 134    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 135    "r" 5 bit same register used as both source and target (OP_*_RS)
 136    "s" 5 bit source register specifier (OP_*_RS)
 137    "t" 5 bit target register (OP_*_RT)
 138    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 139    "v" 5 bit same register used as both source and destination (OP_*_RS)
 140    "w" 5 bit same register used as both target and destination (OP_*_RT)
 141    "C" 25 bit coprocessor function code (OP_*_COPZ)
 142    "B" 20 bit syscall function code (OP_*_SYSCALL)
 143    "x" accept and ignore register name
 144    "z" must be zero register
 145
 146    Floating point instructions:
 147    "D" 5 bit destination register (OP_*_FD)
 148    "S" 5 bit fs source 1 register (OP_*_FS)
 149    "T" 5 bit ft source 2 register (OP_*_FT)
 150    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 151    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 152
 153    Coprocessor instructions:
 154    "E" 5 bit target register (OP_*_RT)
 155    "G" 5 bit destination register (OP_*_RD)
 156
 157    Macro instructions:
 158    "A" General 32 bit expression
 159    "I" 32 bit immediate
 160    "F" 64 bit floating point constant in .rdata
 161    "L" 64 bit floating point constant in .lit8
 162    "f" 32 bit floating point constant
 163    "l" 32 bit floating point constant in .lit4
 164 */
 165
 166 /* These are the bits which may be set in the pinfo field of an
 167    instructions, if it is not equal to INSN_MACRO.  */
 168
 169 /* Modifies the general purpose register in OP_*_RD.  */
 170 #define INSN_WRITE_GPR_D            0x00000001
 171 /* Modifies the general purpose register in OP_*_RT.  */
 172 #define INSN_WRITE_GPR_T            0x00000002
 173 /* Modifies general purpose register 31.  */
 174 #define INSN_WRITE_GPR_31           0x00000004
 175 /* Modifies the floating point register in OP_*_FD.  */
 176 #define INSN_WRITE_FPR_D            0x00000008
 177 /* Modifies the floating point register in OP_*_FS.  */
 178 #define INSN_WRITE_FPR_S            0x00000010
 179 /* Modifies the floating point register in OP_*_FT.  */
 180 #define INSN_WRITE_FPR_T            0x00000020
 181 /* Reads the general purpose register in OP_*_RS.  */
 182 #define INSN_READ_GPR_S             0x00000040
 183 /* Reads the general purpose register in OP_*_RT.  */
 184 #define INSN_READ_GPR_T             0x00000080
 185 /* Reads the floating point register in OP_*_FS.  */
 186 #define INSN_READ_FPR_S             0x00000100
 187 /* Reads the floating point register in OP_*_FT.  */
 188 #define INSN_READ_FPR_T             0x00000200
 189 /* Modifies coprocessor condition code.  */
 190 #define INSN_WRITE_COND_CODE        0x00000400
 191 /* Reads coprocessor condition code.  */
 192 #define INSN_READ_COND_CODE         0x00000800
 193 /* TLB operation.  */
 194 #define INSN_TLB                    0x00001000
 195 /* RFE (return from exception) instruction.  */
 196 #define INSN_RFE                    0x00002000
 197 /* Reads coprocessor register other than floating point register.  */
 198 #define INSN_COP                    0x00004000
 199 /* Instruction loads value from memory, requiring delay.  */
 200 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 201 /* Instruction loads value from coprocessor, requiring delay.  */
 202 #define INSN_LOAD_COPROC_DELAY      0x00010000
 203 /* Instruction has unconditional branch delay slot.  */
 204 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 205 /* Instruction has conditional branch delay slot.  */
 206 #define INSN_COND_BRANCH_DELAY      0x00040000
 207 /* Conditional branch likely: if branch not taken, insn nullified.  */
 208 #define INSN_COND_BRANCH_LIKELY     0x00080000
 209 /* Moves to coprocessor register, requiring delay.  */
 210 #define INSN_COPROC_MOVE_DELAY      0x00100000
 211 /* Loads coprocessor register from memory, requiring delay.  */
 212 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 213 /* Reads the HI register.  */
 214 #define INSN_READ_HI                0x00400000
 215 /* Reads the LO register.  */
 216 #define INSN_READ_LO                0x00800000
 217 /* Modifies the HI register.  */
 218 #define INSN_WRITE_HI               0x01000000
 219 /* Modifies the LO register.  */
 220 #define INSN_WRITE_LO               0x02000000
 221 /* Takes a trap (easier to keep out of delay slot).  */
 222 #define INSN_TRAP                   0x04000000
 223 /* Instruction stores value into memory.  */
 224 #define INSN_STORE_MEMORY           0x08000000
 225 /* MIPS ISA field--CPU level at which insn is supported.  */
 226 #define INSN_ISA                    0x70000000
 227 /* MIPS ISA 2 instruction (R6000 or R4000).  */
 228 #define INSN_ISA2                   0x10000000
 229 /* MIPS ISA 3 instruction (R4000).  */
 230 #define INSN_ISA3                   0x20000000
 231 /* MIPS R4650 instruction.  */
 232 #define INSN_4650                   0x30000000
 233 /* MIPS ISA 4 instruction (R8000).  */
 234 #define INSN_ISA4                   0x40000000
 235
 236 /* Instruction is actually a macro.  It should be ignored by the
 237    disassembler, and requires special treatment by the assembler.  */
 238 #define INSN_MACRO                  0xffffffff
 239
 240 /* This is a list of macro expanded instructions.
 241  *
 242  * _I appended means immediate
 243  * _A appended means address
 244  * _AB appended means address with base register
 245  * _D appended means 64 bit floating point constant
 246  * _S appended means 32 bit floating point constant
 247  */
 248 enum {
 249     M_ABS,
 250     M_ADD_I,
 251     M_ADDU_I,
 252     M_AND_I,
 253     M_BEQ_I,
 254     M_BEQL_I,
 255     M_BGE,
 256     M_BGEL,
 257     M_BGE_I,
 258     M_BGEL_I,
 259     M_BGEU,
 260     M_BGEUL,
 261     M_BGEU_I,
 262     M_BGEUL_I,
 263     M_BGT,
 264     M_BGTL,
 265     M_BGT_I,
 266     M_BGTL_I,
 267     M_BGTU,
 268     M_BGTUL,
 269     M_BGTU_I,
 270     M_BGTUL_I,
 271     M_BLE,
 272     M_BLEL,
 273     M_BLE_I,
 274     M_BLEL_I,
 275     M_BLEU,
 276     M_BLEUL,
 277     M_BLEU_I,
 278     M_BLEUL_I,
 279     M_BLT,
 280     M_BLTL,
 281     M_BLT_I,
 282     M_BLTL_I,
 283     M_BLTU,
 284     M_BLTUL,
 285     M_BLTU_I,
 286     M_BLTUL_I,
 287     M_BNE_I,
 288     M_BNEL_I,
 289     M_DABS,
 290     M_DADD_I,
 291     M_DADDU_I,
 292     M_DDIV_3,
 293     M_DDIV_3I,
 294     M_DDIVU_3,
 295     M_DDIVU_3I,
 296     M_DIV_3,
 297     M_DIV_3I,
 298     M_DIVU_3,
 299     M_DIVU_3I,
 300     M_DLA_AB,
 301     M_DLI,
 302     M_DMUL,
 303     M_DMUL_I,
 304     M_DMULO,
 305     M_DMULO_I,
 306     M_DMULOU,
 307     M_DMULOU_I,
 308     M_DREM_3,
 309     M_DREM_3I,
 310     M_DREMU_3,
 311     M_DREMU_3I,
 312     M_DSUB_I,
 313     M_DSUBU_I,
 314     M_J_A,
 315     M_JAL_1,
 316     M_JAL_2,
 317     M_JAL_A,
 318     M_L_DOB,
 319     M_L_DAB,
 320     M_LA_AB,
 321     M_LB_A,
 322     M_LB_AB,
 323     M_LBU_A,
 324     M_LBU_AB,
 325     M_LD_A,
 326     M_LD_OB,
 327     M_LD_AB,
 328     M_LDC1_AB,
 329     M_LDC2_AB,
 330     M_LDC3_AB,
 331     M_LDL_AB,
 332     M_LDR_AB,
 333     M_LH_A,
 334     M_LH_AB,
 335     M_LHU_A,
 336     M_LHU_AB,
 337     M_LI,
 338     M_LI_D,
 339     M_LI_DD,
 340     M_LI_S,
 341     M_LI_SS,
 342     M_LL_AB,
 343     M_LLD_AB,
 344     M_LS_A,
 345     M_LW_A,
 346     M_LW_AB,
 347     M_LWC0_A,
 348     M_LWC0_AB,
 349     M_LWC1_A,
 350     M_LWC1_AB,
 351     M_LWC2_A,
 352     M_LWC2_AB,
 353     M_LWC3_A,
 354     M_LWC3_AB,
 355     M_LWL_A,
 356     M_LWL_AB,
 357     M_LWR_A,
 358     M_LWR_AB,
 359     M_LWU_AB,
 360     M_MUL,
 361     M_MUL_I,
 362     M_MULO,
 363     M_MULO_I,
 364     M_MULOU,
 365     M_MULOU_I,
 366     M_NOR_I,
 367     M_OR_I,
 368     M_REM_3,
 369     M_REM_3I,
 370     M_REMU_3,
 371     M_REMU_3I,
 372     M_ROL,
 373     M_ROL_I,
 374     M_ROR,
 375     M_ROR_I,
 376     M_S_DA,
 377     M_S_DOB,
 378     M_S_DAB,
 379     M_S_S,
 380     M_SC_AB,
 381     M_SCD_AB,
 382     M_SD_A,
 383     M_SD_OB,
 384     M_SD_AB,
 385     M_SDC1_AB,
 386     M_SDC2_AB,
 387     M_SDC3_AB,
 388     M_SDL_AB,
 389     M_SDR_AB,
 390     M_SEQ,
 391     M_SEQ_I,
 392     M_SGE,
 393     M_SGE_I,
 394     M_SGEU,
 395     M_SGEU_I,
 396     M_SGT,
 397     M_SGT_I,
 398     M_SGTU,
 399     M_SGTU_I,
 400     M_SLE,
 401     M_SLE_I,
 402     M_SLEU,
 403     M_SLEU_I,
 404     M_SLT_I,
 405     M_SLTU_I,
 406     M_SNE,
 407     M_SNE_I,
 408     M_SB_A,
 409     M_SB_AB,
 410     M_SH_A,
 411     M_SH_AB,
 412     M_SW_A,
 413     M_SW_AB,
 414     M_SWC0_A,
 415     M_SWC0_AB,
 416     M_SWC1_A,
 417     M_SWC1_AB,
 418     M_SWC2_A,
 419     M_SWC2_AB,
 420     M_SWC3_A,
 421     M_SWC3_AB,
 422     M_SWL_A,
 423     M_SWL_AB,
 424     M_SWR_A,
 425     M_SWR_AB,
 426     M_SUB_I,
 427     M_SUBU_I,
 428     M_TEQ_I,
 429     M_TGE_I,
 430     M_TGEU_I,
 431     M_TLT_I,
 432     M_TLTU_I,
 433     M_TNE_I,
 434     M_TRUNCWD,
 435     M_TRUNCWS,
 436     M_ULD,
 437     M_ULD_A,
 438     M_ULH,
 439     M_ULH_A,
 440     M_ULHU,
 441     M_ULHU_A,
 442     M_ULW,
 443     M_ULW_A,
 444     M_USH,
 445     M_USH_A,
 446     M_USW,
 447     M_USW_A,
 448     M_USD,
 449     M_USD_A,
 450     M_XOR_I
 451 };
 452
 453 /* The order of overloaded instructions matters.  Label arguments and
 454    register arguments look the same. Instructions that can have either
 455    for arguments must apear in the correct order in this table for the
 456    assembler to pick the right one. In other words, entries with
 457    immediate operands must apear after the same instruction with
 458    registers.
 459
 460    Many instructions are short hand for other instructions (i.e., The
 461    jal <register> instruction is short for jalr <register>).  */
 462
 463 extern const struct mips_opcode mips_opcodes[];
 464 extern const int bfd_mips_num_opcodes;
 465 #define NUMOPCODES bfd_mips_num_opcodes