projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
* mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
[deliverable/binutils-gdb.git] / include / opcode / mips.h
1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
7
8 This file is part of GDB, GAS, and the GNU binutils.
9
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version
13 1, or (at your option) any later version.
14
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
23
24 #ifndef _MIPS_H_
25 #define _MIPS_H_
26
27 /* These are bit masks and shift counts to use to access the various
28 fields of an instruction. To retrieve the X field of an
29 instruction, use the expression
30 (i >> OP_SH_X) & OP_MASK_X
31 To set the same field (to j), use
32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
33
34 Make sure you use fields that are appropriate for the instruction,
35 of course.
36
37 The 'i' format uses OP, RS, RT and IMMEDIATE.
38
39 The 'j' format uses OP and TARGET.
40
41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
42
43 The 'b' format uses OP, RS, RT and DELTA.
44
45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
46
47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
48
49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
50 breakpoint instruction are not defined; Kane says the breakpoint
51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
52 only use ten bits). An optional two-operand form of break/sdbbp
53 allows the lower ten bits to be set too, and MIPS32 and later
54 architectures allow 20 bits to be set with a signal operand
55 (using CODE20).
56
57 The syscall instruction uses CODE20.
58
59 The general coprocessor instructions use COPZ. */
60
61 #define OP_MASK_OP 0x3f
62 #define OP_SH_OP 26
63 #define OP_MASK_RS 0x1f
64 #define OP_SH_RS 21
65 #define OP_MASK_FR 0x1f
66 #define OP_SH_FR 21
67 #define OP_MASK_FMT 0x1f
68 #define OP_SH_FMT 21
69 #define OP_MASK_BCC 0x7
70 #define OP_SH_BCC 18
71 #define OP_MASK_CODE 0x3ff
72 #define OP_SH_CODE 16
73 #define OP_MASK_CODE2 0x3ff
74 #define OP_SH_CODE2 6
75 #define OP_MASK_RT 0x1f
76 #define OP_SH_RT 16
77 #define OP_MASK_FT 0x1f
78 #define OP_SH_FT 16
79 #define OP_MASK_CACHE 0x1f
80 #define OP_SH_CACHE 16
81 #define OP_MASK_RD 0x1f
82 #define OP_SH_RD 11
83 #define OP_MASK_FS 0x1f
84 #define OP_SH_FS 11
85 #define OP_MASK_PREFX 0x1f
86 #define OP_SH_PREFX 11
87 #define OP_MASK_CCC 0x7
88 #define OP_SH_CCC 8
89 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
90 #define OP_SH_CODE20 6
91 #define OP_MASK_SHAMT 0x1f
92 #define OP_SH_SHAMT 6
93 #define OP_MASK_FD 0x1f
94 #define OP_SH_FD 6
95 #define OP_MASK_TARGET 0x3ffffff
96 #define OP_SH_TARGET 0
97 #define OP_MASK_COPZ 0x1ffffff
98 #define OP_SH_COPZ 0
99 #define OP_MASK_IMMEDIATE 0xffff
100 #define OP_SH_IMMEDIATE 0
101 #define OP_MASK_DELTA 0xffff
102 #define OP_SH_DELTA 0
103 #define OP_MASK_FUNCT 0x3f
104 #define OP_SH_FUNCT 0
105 #define OP_MASK_SPEC 0x3f
106 #define OP_SH_SPEC 0
107 #define OP_SH_LOCC 8 /* FP condition code. */
108 #define OP_SH_HICC 18 /* FP condition code. */
109 #define OP_MASK_CC 0x7
110 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
111 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
112 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
113 #define OP_MASK_COP1SPEC 0xf
114 #define OP_MASK_COP1SCLR 0x4
115 #define OP_MASK_COP1CMP 0x3
116 #define OP_SH_COP1CMP 4
117 #define OP_SH_FORMAT 21 /* FP short format field. */
118 #define OP_MASK_FORMAT 0x7
119 #define OP_SH_TRUE 16
120 #define OP_MASK_TRUE 0x1
121 #define OP_SH_GE 17
122 #define OP_MASK_GE 0x01
123 #define OP_SH_UNSIGNED 16
124 #define OP_MASK_UNSIGNED 0x1
125 #define OP_SH_HINT 16
126 #define OP_MASK_HINT 0x1f
127 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
128 #define OP_MASK_MMI 0x3f
129 #define OP_SH_MMISUB 6
130 #define OP_MASK_MMISUB 0x1f
131 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
132 #define OP_SH_PERFREG 1
133 #define OP_SH_SEL 0 /* Coprocessor select field. */
134 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
135 #define OP_SH_CODE19 6 /* 19 bit wait code. */
136 #define OP_MASK_CODE19 0x7ffff
137 #define OP_SH_ALN 21
138 #define OP_MASK_ALN 0x7
139 #define OP_SH_VSEL 21
140 #define OP_MASK_VSEL 0x1f
141 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
142 but 0x8-0xf don't select bytes. */
143 #define OP_SH_VECBYTE 22
144 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
145 #define OP_SH_VECALIGN 21
146 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
147 #define OP_SH_INSMSB 11
148 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
149 #define OP_SH_EXTMSBD 11
150
151 /* MIPS DSP ASE */
152 #define OP_SH_DSPACC 11
153 #define OP_MASK_DSPACC 0x3
154 #define OP_SH_DSPACC_S 21
155 #define OP_MASK_DSPACC_S 0x3
156 #define OP_SH_DSPSFT 20
157 #define OP_MASK_DSPSFT 0x3f
158 #define OP_SH_DSPSFT_7 19
159 #define OP_MASK_DSPSFT_7 0x7f
160 #define OP_SH_SA3 21
161 #define OP_MASK_SA3 0x7
162 #define OP_SH_SA4 21
163 #define OP_MASK_SA4 0xf
164 #define OP_SH_IMM8 16
165 #define OP_MASK_IMM8 0xff
166 #define OP_SH_IMM10 16
167 #define OP_MASK_IMM10 0x3ff
168 #define OP_SH_WRDSP 11
169 #define OP_MASK_WRDSP 0x3f
170 #define OP_SH_RDDSP 16
171 #define OP_MASK_RDDSP 0x3f
172
173 /* MIPS MT ASE */
174 #define OP_SH_MT_U 5
175 #define OP_MASK_MT_U 0x1
176 #define OP_SH_MT_H 4
177 #define OP_MASK_MT_H 0x1
178 #define OP_SH_MTACC_T 18
179 #define OP_MASK_MTACC_T 0x3
180 #define OP_SH_MTACC_D 13
181 #define OP_MASK_MTACC_D 0x3
182
183 #define OP_OP_COP0 0x10
184 #define OP_OP_COP1 0x11
185 #define OP_OP_COP2 0x12
186 #define OP_OP_COP3 0x13
187 #define OP_OP_LWC1 0x31
188 #define OP_OP_LWC2 0x32
189 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
190 #define OP_OP_LDC1 0x35
191 #define OP_OP_LDC2 0x36
192 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
193 #define OP_OP_SWC1 0x39
194 #define OP_OP_SWC2 0x3a
195 #define OP_OP_SWC3 0x3b
196 #define OP_OP_SDC1 0x3d
197 #define OP_OP_SDC2 0x3e
198 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
199
200 /* Values in the 'VSEL' field. */
201 #define MDMX_FMTSEL_IMM_QH 0x1d
202 #define MDMX_FMTSEL_IMM_OB 0x1e
203 #define MDMX_FMTSEL_VEC_QH 0x15
204 #define MDMX_FMTSEL_VEC_OB 0x16
205
206 /* This structure holds information for a particular instruction. */
207
208 struct mips_opcode
209 {
210 /* The name of the instruction. */
211 const char *name;
212 /* A string describing the arguments for this instruction. */
213 const char *args;
214 /* The basic opcode for the instruction. When assembling, this
215 opcode is modified by the arguments to produce the actual opcode
216 that is used. If pinfo is INSN_MACRO, then this is 0. */
217 unsigned long match;
218 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
219 relevant portions of the opcode when disassembling. If the
220 actual opcode anded with the match field equals the opcode field,
221 then we have found the correct instruction. If pinfo is
222 INSN_MACRO, then this field is the macro identifier. */
223 unsigned long mask;
224 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
225 of bits describing the instruction, notably any relevant hazard
226 information. */
227 unsigned long pinfo;
228 /* A collection of additional bits describing the instruction. */
229 unsigned long pinfo2;
230 /* A collection of bits describing the instruction sets of which this
231 instruction or macro is a member. */
232 unsigned long membership;
233 };
234
235 /* These are the characters which may appear in the args field of an
236 instruction. They appear in the order in which the fields appear
237 when the instruction is used. Commas and parentheses in the args
238 string are ignored when assembling, and written into the output
239 when disassembling.
240
241 Each of these characters corresponds to a mask field defined above.
242
243 "<" 5 bit shift amount (OP_*_SHAMT)
244 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
245 "a" 26 bit target address (OP_*_TARGET)
246 "b" 5 bit base register (OP_*_RS)
247 "c" 10 bit breakpoint code (OP_*_CODE)
248 "d" 5 bit destination register specifier (OP_*_RD)
249 "h" 5 bit prefx hint (OP_*_PREFX)
250 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
251 "j" 16 bit signed immediate (OP_*_DELTA)
252 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
253 Also used for immediate operands in vr5400 vector insns.
254 "o" 16 bit signed offset (OP_*_DELTA)
255 "p" 16 bit PC relative branch target address (OP_*_DELTA)
256 "q" 10 bit extra breakpoint code (OP_*_CODE2)
257 "r" 5 bit same register used as both source and target (OP_*_RS)
258 "s" 5 bit source register specifier (OP_*_RS)
259 "t" 5 bit target register (OP_*_RT)
260 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
261 "v" 5 bit same register used as both source and destination (OP_*_RS)
262 "w" 5 bit same register used as both target and destination (OP_*_RT)
263 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
264 (used by clo and clz)
265 "C" 25 bit coprocessor function code (OP_*_COPZ)
266 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
267 "J" 19 bit wait function code (OP_*_CODE19)
268 "x" accept and ignore register name
269 "z" must be zero register
270 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
271 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
272 Enforces: 0 <= pos < 32.
273 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
274 Requires that "+A" or "+E" occur first to set position.
275 Enforces: 0 < (pos+size) <= 32.
276 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
277 Requires that "+A" or "+E" occur first to set position.
278 Enforces: 0 < (pos+size) <= 32.
279 (Also used by "dext" w/ different limits, but limits for
280 that are checked by the M_DEXT macro.)
281 "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
282 Enforces: 32 <= pos < 64.
283 "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
284 Requires that "+A" or "+E" occur first to set position.
285 Enforces: 32 < (pos+size) <= 64.
286 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
287 Requires that "+A" or "+E" occur first to set position.
288 Enforces: 32 < (pos+size) <= 64.
289 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
290 Requires that "+A" or "+E" occur first to set position.
291 Enforces: 32 < (pos+size) <= 64.
292
293 Floating point instructions:
294 "D" 5 bit destination register (OP_*_FD)
295 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
296 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
297 "S" 5 bit fs source 1 register (OP_*_FS)
298 "T" 5 bit ft source 2 register (OP_*_FT)
299 "R" 5 bit fr source 3 register (OP_*_FR)
300 "V" 5 bit same register used as floating source and destination (OP_*_FS)
301 "W" 5 bit same register used as floating target and destination (OP_*_FT)
302
303 Coprocessor instructions:
304 "E" 5 bit target register (OP_*_RT)
305 "G" 5 bit destination register (OP_*_RD)
306 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
307 "P" 5 bit performance-monitor register (OP_*_PERFREG)
308 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
309 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
310 see also "k" above
311 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
312 for pretty-printing in disassembly only.
313
314 Macro instructions:
315 "A" General 32 bit expression
316 "I" 32 bit immediate (value placed in imm_expr).
317 "+I" 32 bit immediate (value placed in imm2_expr).
318 "F" 64 bit floating point constant in .rdata
319 "L" 64 bit floating point constant in .lit8
320 "f" 32 bit floating point constant
321 "l" 32 bit floating point constant in .lit4
322
323 MDMX instruction operands (note that while these use the FP register
324 fields, they accept both $fN and $vN names for the registers):
325 "O" MDMX alignment offset (OP_*_ALN)
326 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
327 "X" MDMX destination register (OP_*_FD)
328 "Y" MDMX source register (OP_*_FS)
329 "Z" MDMX source register (OP_*_FT)
330
331 DSP ASE usage:
332 "3" 3 bit unsigned immediate (OP_*_SA3)
333 "4" 4 bit unsigned immediate (OP_*_SA4)
334 "5" 8 bit unsigned immediate (OP_*_IMM8)
335 "6" 5 bit unsigned immediate (OP_*_RS)
336 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
337 "8" 6 bit unsigned immediate (OP_*_WRDSP)
338 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
339 "0" 6 bit signed immediate (OP_*_DSPSFT)
340 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
341 "'" 6 bit unsigned immediate (OP_*_RDDSP)
342 "@" 10 bit signed immediate (OP_*_IMM10)
343
344 MT ASE usage:
345 "!" 1 bit immediate at bit 5
346 "$" 1 bit immediate at bit 4
347 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
348 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
349 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
350 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
351 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
352
353 Other:
354 "()" parens surrounding optional value
355 "," separates operands
356 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
357 "+" Start of extension sequence.
358
359 Characters used so far, for quick reference when adding more:
360 "34567890"
361 "%[]<>(),+:'@!$*&"
362 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
363 "abcdefghijklopqrstuvwxz"
364
365 Extension character sequences used so far ("+" followed by the
366 following), for quick reference when adding more:
367 "ABCDEFGHIT"
368 "t"
369 */
370
371 /* These are the bits which may be set in the pinfo field of an
372 instructions, if it is not equal to INSN_MACRO. */
373
374 /* Modifies the general purpose register in OP_*_RD. */
375 #define INSN_WRITE_GPR_D 0x00000001
376 /* Modifies the general purpose register in OP_*_RT. */
377 #define INSN_WRITE_GPR_T 0x00000002
378 /* Modifies general purpose register 31. */
379 #define INSN_WRITE_GPR_31 0x00000004
380 /* Modifies the floating point register in OP_*_FD. */
381 #define INSN_WRITE_FPR_D 0x00000008
382 /* Modifies the floating point register in OP_*_FS. */
383 #define INSN_WRITE_FPR_S 0x00000010
384 /* Modifies the floating point register in OP_*_FT. */
385 #define INSN_WRITE_FPR_T 0x00000020
386 /* Reads the general purpose register in OP_*_RS. */
387 #define INSN_READ_GPR_S 0x00000040
388 /* Reads the general purpose register in OP_*_RT. */
389 #define INSN_READ_GPR_T 0x00000080
390 /* Reads the floating point register in OP_*_FS. */
391 #define INSN_READ_FPR_S 0x00000100
392 /* Reads the floating point register in OP_*_FT. */
393 #define INSN_READ_FPR_T 0x00000200
394 /* Reads the floating point register in OP_*_FR. */
395 #define INSN_READ_FPR_R 0x00000400
396 /* Modifies coprocessor condition code. */
397 #define INSN_WRITE_COND_CODE 0x00000800
398 /* Reads coprocessor condition code. */
399 #define INSN_READ_COND_CODE 0x00001000
400 /* TLB operation. */
401 #define INSN_TLB 0x00002000
402 /* Reads coprocessor register other than floating point register. */
403 #define INSN_COP 0x00004000
404 /* Instruction loads value from memory, requiring delay. */
405 #define INSN_LOAD_MEMORY_DELAY 0x00008000
406 /* Instruction loads value from coprocessor, requiring delay. */
407 #define INSN_LOAD_COPROC_DELAY 0x00010000
408 /* Instruction has unconditional branch delay slot. */
409 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
410 /* Instruction has conditional branch delay slot. */
411 #define INSN_COND_BRANCH_DELAY 0x00040000
412 /* Conditional branch likely: if branch not taken, insn nullified. */
413 #define INSN_COND_BRANCH_LIKELY 0x00080000
414 /* Moves to coprocessor register, requiring delay. */
415 #define INSN_COPROC_MOVE_DELAY 0x00100000
416 /* Loads coprocessor register from memory, requiring delay. */
417 #define INSN_COPROC_MEMORY_DELAY 0x00200000
418 /* Reads the HI register. */
419 #define INSN_READ_HI 0x00400000
420 /* Reads the LO register. */
421 #define INSN_READ_LO 0x00800000
422 /* Modifies the HI register. */
423 #define INSN_WRITE_HI 0x01000000
424 /* Modifies the LO register. */
425 #define INSN_WRITE_LO 0x02000000
426 /* Takes a trap (easier to keep out of delay slot). */
427 #define INSN_TRAP 0x04000000
428 /* Instruction stores value into memory. */
429 #define INSN_STORE_MEMORY 0x08000000
430 /* Instruction uses single precision floating point. */
431 #define FP_S 0x10000000
432 /* Instruction uses double precision floating point. */
433 #define FP_D 0x20000000
434 /* Instruction is part of the tx39's integer multiply family. */
435 #define INSN_MULT 0x40000000
436 /* Instruction synchronize shared memory. */
437 #define INSN_SYNC 0x80000000
438
439 /* These are the bits which may be set in the pinfo2 field of an
440 instruction. */
441
442 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
443 #define INSN2_ALIAS 0x00000001
444 /* Instruction reads MDMX accumulator. */
445 #define INSN2_READ_MDMX_ACC 0x00000002
446 /* Instruction writes MDMX accumulator. */
447 #define INSN2_WRITE_MDMX_ACC 0x00000004
448
449 /* Instruction is actually a macro. It should be ignored by the
450 disassembler, and requires special treatment by the assembler. */
451 #define INSN_MACRO 0xffffffff
452
453 /* Masks used to mark instructions to indicate which MIPS ISA level
454 they were introduced in. ISAs, as defined below, are logical
455 ORs of these bits, indicating that they support the instructions
456 defined at the given level. */
457
458 #define INSN_ISA_MASK 0x00000fff
459 #define INSN_ISA1 0x00000001
460 #define INSN_ISA2 0x00000002
461 #define INSN_ISA3 0x00000004
462 #define INSN_ISA4 0x00000008
463 #define INSN_ISA5 0x00000010
464 #define INSN_ISA32 0x00000020
465 #define INSN_ISA64 0x00000040
466 #define INSN_ISA32R2 0x00000080
467 #define INSN_ISA64R2 0x00000100
468
469 /* Masks used for MIPS-defined ASEs. */
470 #define INSN_ASE_MASK 0x0400f000
471
472 /* DSP ASE */
473 #define INSN_DSP 0x00001000
474 /* MIPS 16 ASE */
475 #define INSN_MIPS16 0x00002000
476 /* MIPS-3D ASE */
477 #define INSN_MIPS3D 0x00004000
478 /* MDMX ASE */
479 #define INSN_MDMX 0x00008000
480
481 /* Chip specific instructions. These are bitmasks. */
482
483 /* MIPS R4650 instruction. */
484 #define INSN_4650 0x00010000
485 /* LSI R4010 instruction. */
486 #define INSN_4010 0x00020000
487 /* NEC VR4100 instruction. */
488 #define INSN_4100 0x00040000
489 /* Toshiba R3900 instruction. */
490 #define INSN_3900 0x00080000
491 /* MIPS R10000 instruction. */
492 #define INSN_10000 0x00100000
493 /* Broadcom SB-1 instruction. */
494 #define INSN_SB1 0x00200000
495 /* NEC VR4111/VR4181 instruction. */
496 #define INSN_4111 0x00400000
497 /* NEC VR4120 instruction. */
498 #define INSN_4120 0x00800000
499 /* NEC VR5400 instruction. */
500 #define INSN_5400 0x01000000
501 /* NEC VR5500 instruction. */
502 #define INSN_5500 0x02000000
503 /* MT ASE */
504 #define INSN_MT 0x04000000
505
506 /* MIPS ISA defines, use instead of hardcoding ISA level. */
507
508 #define ISA_UNKNOWN 0 /* Gas internal use. */
509 #define ISA_MIPS1 (INSN_ISA1)
510 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
511 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
512 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
513 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
514
515 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
516 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
517
518 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
519 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
520
521
522 /* CPU defines, use instead of hardcoding processor number. Keep this
523 in sync with bfd/archures.c in order for machine selection to work. */
524 #define CPU_UNKNOWN 0 /* Gas internal use. */
525 #define CPU_R3000 3000
526 #define CPU_R3900 3900
527 #define CPU_R4000 4000
528 #define CPU_R4010 4010
529 #define CPU_VR4100 4100
530 #define CPU_R4111 4111
531 #define CPU_VR4120 4120
532 #define CPU_R4300 4300
533 #define CPU_R4400 4400
534 #define CPU_R4600 4600
535 #define CPU_R4650 4650
536 #define CPU_R5000 5000
537 #define CPU_VR5400 5400
538 #define CPU_VR5500 5500
539 #define CPU_R6000 6000
540 #define CPU_RM7000 7000
541 #define CPU_R8000 8000
542 #define CPU_RM9000 9000
543 #define CPU_R10000 10000
544 #define CPU_R12000 12000
545 #define CPU_MIPS16 16
546 #define CPU_MIPS32 32
547 #define CPU_MIPS32R2 33
548 #define CPU_MIPS5 5
549 #define CPU_MIPS64 64
550 #define CPU_MIPS64R2 65
551 #define CPU_SB1 12310201 /* octal 'SB', 01. */
552
553 /* Test for membership in an ISA including chip specific ISAs. INSN
554 is pointer to an element of the opcode table; ISA is the specified
555 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
556 test, or zero if no CPU specific ISA test is desired. */
557
558 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
559 (((insn)->membership & isa) != 0 \
560 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
561 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
562 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
563 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
564 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
565 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
566 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
567 && ((insn)->membership & INSN_10000) != 0) \
568 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
569 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
570 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
571 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
572 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
573 || 0) /* Please keep this term for easier source merging. */
574
575 /* This is a list of macro expanded instructions.
576
577 _I appended means immediate
578 _A appended means address
579 _AB appended means address with base register
580 _D appended means 64 bit floating point constant
581 _S appended means 32 bit floating point constant. */
582
583 enum
584 {
585 M_ABS,
586 M_ADD_I,
587 M_ADDU_I,
588 M_AND_I,
589 M_BEQ,
590 M_BEQ_I,
591 M_BEQL_I,
592 M_BGE,
593 M_BGEL,
594 M_BGE_I,
595 M_BGEL_I,
596 M_BGEU,
597 M_BGEUL,
598 M_BGEU_I,
599 M_BGEUL_I,
600 M_BGT,
601 M_BGTL,
602 M_BGT_I,
603 M_BGTL_I,
604 M_BGTU,
605 M_BGTUL,
606 M_BGTU_I,
607 M_BGTUL_I,
608 M_BLE,
609 M_BLEL,
610 M_BLE_I,
611 M_BLEL_I,
612 M_BLEU,
613 M_BLEUL,
614 M_BLEU_I,
615 M_BLEUL_I,
616 M_BLT,
617 M_BLTL,
618 M_BLT_I,
619 M_BLTL_I,
620 M_BLTU,
621 M_BLTUL,
622 M_BLTU_I,
623 M_BLTUL_I,
624 M_BNE,
625 M_BNE_I,
626 M_BNEL_I,
627 M_DABS,
628 M_DADD_I,
629 M_DADDU_I,
630 M_DDIV_3,
631 M_DDIV_3I,
632 M_DDIVU_3,
633 M_DDIVU_3I,
634 M_DEXT,
635 M_DINS,
636 M_DIV_3,
637 M_DIV_3I,
638 M_DIVU_3,
639 M_DIVU_3I,
640 M_DLA_AB,
641 M_DLCA_AB,
642 M_DLI,
643 M_DMUL,
644 M_DMUL_I,
645 M_DMULO,
646 M_DMULO_I,
647 M_DMULOU,
648 M_DMULOU_I,
649 M_DREM_3,
650 M_DREM_3I,
651 M_DREMU_3,
652 M_DREMU_3I,
653 M_DSUB_I,
654 M_DSUBU_I,
655 M_DSUBU_I_2,
656 M_J_A,
657 M_JAL_1,
658 M_JAL_2,
659 M_JAL_A,
660 M_L_DOB,
661 M_L_DAB,
662 M_LA_AB,
663 M_LB_A,
664 M_LB_AB,
665 M_LBU_A,
666 M_LBU_AB,
667 M_LCA_AB,
668 M_LD_A,
669 M_LD_OB,
670 M_LD_AB,
671 M_LDC1_AB,
672 M_LDC2_AB,
673 M_LDC3_AB,
674 M_LDL_AB,
675 M_LDR_AB,
676 M_LH_A,
677 M_LH_AB,
678 M_LHU_A,
679 M_LHU_AB,
680 M_LI,
681 M_LI_D,
682 M_LI_DD,
683 M_LI_S,
684 M_LI_SS,
685 M_LL_AB,
686 M_LLD_AB,
687 M_LS_A,
688 M_LW_A,
689 M_LW_AB,
690 M_LWC0_A,
691 M_LWC0_AB,
692 M_LWC1_A,
693 M_LWC1_AB,
694 M_LWC2_A,
695 M_LWC2_AB,
696 M_LWC3_A,
697 M_LWC3_AB,
698 M_LWL_A,
699 M_LWL_AB,
700 M_LWR_A,
701 M_LWR_AB,
702 M_LWU_AB,
703 M_MOVE,
704 M_MUL,
705 M_MUL_I,
706 M_MULO,
707 M_MULO_I,
708 M_MULOU,
709 M_MULOU_I,
710 M_NOR_I,
711 M_OR_I,
712 M_REM_3,
713 M_REM_3I,
714 M_REMU_3,
715 M_REMU_3I,
716 M_DROL,
717 M_ROL,
718 M_DROL_I,
719 M_ROL_I,
720 M_DROR,
721 M_ROR,
722 M_DROR_I,
723 M_ROR_I,
724 M_S_DA,
725 M_S_DOB,
726 M_S_DAB,
727 M_S_S,
728 M_SC_AB,
729 M_SCD_AB,
730 M_SD_A,
731 M_SD_OB,
732 M_SD_AB,
733 M_SDC1_AB,
734 M_SDC2_AB,
735 M_SDC3_AB,
736 M_SDL_AB,
737 M_SDR_AB,
738 M_SEQ,
739 M_SEQ_I,
740 M_SGE,
741 M_SGE_I,
742 M_SGEU,
743 M_SGEU_I,
744 M_SGT,
745 M_SGT_I,
746 M_SGTU,
747 M_SGTU_I,
748 M_SLE,
749 M_SLE_I,
750 M_SLEU,
751 M_SLEU_I,
752 M_SLT_I,
753 M_SLTU_I,
754 M_SNE,
755 M_SNE_I,
756 M_SB_A,
757 M_SB_AB,
758 M_SH_A,
759 M_SH_AB,
760 M_SW_A,
761 M_SW_AB,
762 M_SWC0_A,
763 M_SWC0_AB,
764 M_SWC1_A,
765 M_SWC1_AB,
766 M_SWC2_A,
767 M_SWC2_AB,
768 M_SWC3_A,
769 M_SWC3_AB,
770 M_SWL_A,
771 M_SWL_AB,
772 M_SWR_A,
773 M_SWR_AB,
774 M_SUB_I,
775 M_SUBU_I,
776 M_SUBU_I_2,
777 M_TEQ_I,
778 M_TGE_I,
779 M_TGEU_I,
780 M_TLT_I,
781 M_TLTU_I,
782 M_TNE_I,
783 M_TRUNCWD,
784 M_TRUNCWS,
785 M_ULD,
786 M_ULD_A,
787 M_ULH,
788 M_ULH_A,
789 M_ULHU,
790 M_ULHU_A,
791 M_ULW,
792 M_ULW_A,
793 M_USH,
794 M_USH_A,
795 M_USW,
796 M_USW_A,
797 M_USD,
798 M_USD_A,
799 M_XOR_I,
800 M_COP0,
801 M_COP1,
802 M_COP2,
803 M_COP3,
804 M_NUM_MACROS
805 };
806
807
808 /* The order of overloaded instructions matters. Label arguments and
809 register arguments look the same. Instructions that can have either
810 for arguments must apear in the correct order in this table for the
811 assembler to pick the right one. In other words, entries with
812 immediate operands must apear after the same instruction with
813 registers.
814
815 Many instructions are short hand for other instructions (i.e., The
816 jal <register> instruction is short for jalr <register>). */
817
818 extern const struct mips_opcode mips_builtin_opcodes[];
819 extern const int bfd_mips_num_builtin_opcodes;
820 extern struct mips_opcode *mips_opcodes;
821 extern int bfd_mips_num_opcodes;
822 #define NUMOPCODES bfd_mips_num_opcodes
823
824 \f
825 /* The rest of this file adds definitions for the mips16 TinyRISC
826 processor. */
827
828 /* These are the bitmasks and shift counts used for the different
829 fields in the instruction formats. Other than OP, no masks are
830 provided for the fixed portions of an instruction, since they are
831 not needed.
832
833 The I format uses IMM11.
834
835 The RI format uses RX and IMM8.
836
837 The RR format uses RX, and RY.
838
839 The RRI format uses RX, RY, and IMM5.
840
841 The RRR format uses RX, RY, and RZ.
842
843 The RRI_A format uses RX, RY, and IMM4.
844
845 The SHIFT format uses RX, RY, and SHAMT.
846
847 The I8 format uses IMM8.
848
849 The I8_MOVR32 format uses RY and REGR32.
850
851 The IR_MOV32R format uses REG32R and MOV32Z.
852
853 The I64 format uses IMM8.
854
855 The RI64 format uses RY and IMM5.
856 */
857
858 #define MIPS16OP_MASK_OP 0x1f
859 #define MIPS16OP_SH_OP 11
860 #define MIPS16OP_MASK_IMM11 0x7ff
861 #define MIPS16OP_SH_IMM11 0
862 #define MIPS16OP_MASK_RX 0x7
863 #define MIPS16OP_SH_RX 8
864 #define MIPS16OP_MASK_IMM8 0xff
865 #define MIPS16OP_SH_IMM8 0
866 #define MIPS16OP_MASK_RY 0x7
867 #define MIPS16OP_SH_RY 5
868 #define MIPS16OP_MASK_IMM5 0x1f
869 #define MIPS16OP_SH_IMM5 0
870 #define MIPS16OP_MASK_RZ 0x7
871 #define MIPS16OP_SH_RZ 2
872 #define MIPS16OP_MASK_IMM4 0xf
873 #define MIPS16OP_SH_IMM4 0
874 #define MIPS16OP_MASK_REGR32 0x1f
875 #define MIPS16OP_SH_REGR32 0
876 #define MIPS16OP_MASK_REG32R 0x1f
877 #define MIPS16OP_SH_REG32R 3
878 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
879 #define MIPS16OP_MASK_MOVE32Z 0x7
880 #define MIPS16OP_SH_MOVE32Z 0
881 #define MIPS16OP_MASK_IMM6 0x3f
882 #define MIPS16OP_SH_IMM6 5
883
884 /* These are the characters which may appears in the args field of an
885 instruction. They appear in the order in which the fields appear
886 when the instruction is used. Commas and parentheses in the args
887 string are ignored when assembling, and written into the output
888 when disassembling.
889
890 "y" 3 bit register (MIPS16OP_*_RY)
891 "x" 3 bit register (MIPS16OP_*_RX)
892 "z" 3 bit register (MIPS16OP_*_RZ)
893 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
894 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
895 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
896 "0" zero register ($0)
897 "S" stack pointer ($sp or $29)
898 "P" program counter
899 "R" return address register ($ra or $31)
900 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
901 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
902 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
903 "a" 26 bit jump address
904 "e" 11 bit extension value
905 "l" register list for entry instruction
906 "L" register list for exit instruction
907
908 The remaining codes may be extended. Except as otherwise noted,
909 the full extended operand is a 16 bit signed value.
910 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
911 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
912 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
913 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
914 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
915 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
916 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
917 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
918 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
919 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
920 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
921 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
922 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
923 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
924 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
925 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
926 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
927 "q" 11 bit branch address (MIPS16OP_*_IMM11)
928 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
929 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
930 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
931 "m" 7 bit register list for save instruction (18 bit extended)
932 "M" 7 bit register list for restore instruction (18 bit extended)
933 */
934
935 /* Save/restore encoding for the args field when all 4 registers are
936 either saved as arguments or saved/restored as statics. */
937 #define MIPS16_ALL_ARGS 0xe
938 #define MIPS16_ALL_STATICS 0xb
939
940 /* For the mips16, we use the same opcode table format and a few of
941 the same flags. However, most of the flags are different. */
942
943 /* Modifies the register in MIPS16OP_*_RX. */
944 #define MIPS16_INSN_WRITE_X 0x00000001
945 /* Modifies the register in MIPS16OP_*_RY. */
946 #define MIPS16_INSN_WRITE_Y 0x00000002
947 /* Modifies the register in MIPS16OP_*_RZ. */
948 #define MIPS16_INSN_WRITE_Z 0x00000004
949 /* Modifies the T ($24) register. */
950 #define MIPS16_INSN_WRITE_T 0x00000008
951 /* Modifies the SP ($29) register. */
952 #define MIPS16_INSN_WRITE_SP 0x00000010
953 /* Modifies the RA ($31) register. */
954 #define MIPS16_INSN_WRITE_31 0x00000020
955 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
956 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
957 /* Reads the register in MIPS16OP_*_RX. */
958 #define MIPS16_INSN_READ_X 0x00000080
959 /* Reads the register in MIPS16OP_*_RY. */
960 #define MIPS16_INSN_READ_Y 0x00000100
961 /* Reads the register in MIPS16OP_*_MOVE32Z. */
962 #define MIPS16_INSN_READ_Z 0x00000200
963 /* Reads the T ($24) register. */
964 #define MIPS16_INSN_READ_T 0x00000400
965 /* Reads the SP ($29) register. */
966 #define MIPS16_INSN_READ_SP 0x00000800
967 /* Reads the RA ($31) register. */
968 #define MIPS16_INSN_READ_31 0x00001000
969 /* Reads the program counter. */
970 #define MIPS16_INSN_READ_PC 0x00002000
971 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
972 #define MIPS16_INSN_READ_GPR_X 0x00004000
973 /* Is a branch insn. */
974 #define MIPS16_INSN_BRANCH 0x00010000
975
976 /* The following flags have the same value for the mips16 opcode
977 table:
978 INSN_UNCOND_BRANCH_DELAY
979 INSN_COND_BRANCH_DELAY
980 INSN_COND_BRANCH_LIKELY (never used)
981 INSN_READ_HI
982 INSN_READ_LO
983 INSN_WRITE_HI
984 INSN_WRITE_LO
985 INSN_TRAP
986 INSN_ISA3
987 */
988
989 extern const struct mips_opcode mips16_opcodes[];
990 extern const int bfd_mips16_num_opcodes;
991
992 #endif /* _MIPS_H_ */
GDB Binutils - Deliverables
This page took 0.0681 seconds and 4 git commands to generate.