include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  21
  22 /* These are bit masks and shift counts to use to access the various
  23    fields of an instruction.  To retrieve the X field of an
  24    instruction, use the expression
  25         (i >> OP_SH_X) & OP_MASK_X
  26    To set the same field (to j), use
  27         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  28
  29    Make sure you use fields that are appropriate for the instruction,
  30    of course.
  31
  32    The 'i' format uses OP, RS, RT and IMMEDIATE.
  33
  34    The 'j' format uses OP and TARGET.
  35
  36    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  37
  38    The 'b' format uses OP, RS, RT and DELTA.
  39
  40    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  41
  42    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  43
  44    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  45    breakpoint instruction are not defined; Kane says the breakpoint
  46    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  47    only use ten bits).
  48
  49    The syscall instruction uses SYSCALL.
  50
  51    The general coprocessor instructions use COPZ.  */
  52
  53 #define OP_MASK_OP              0x3f
  54 #define OP_SH_OP                26
  55 #define OP_MASK_RS              0x1f
  56 #define OP_SH_RS                21
  57 #define OP_MASK_FMT             0x1f
  58 #define OP_SH_FMT               21
  59 #define OP_MASK_CODE            0x3ff
  60 #define OP_SH_CODE              16
  61 #define OP_MASK_RT              0x1f
  62 #define OP_SH_RT                16
  63 #define OP_MASK_FT              0x1f
  64 #define OP_SH_FT                16
  65 #define OP_MASK_RD              0x1f
  66 #define OP_SH_RD                11
  67 #define OP_MASK_FS              0x1f
  68 #define OP_SH_FS                11
  69 #define OP_MASK_SYSCALL         0xfffff
  70 #define OP_SH_SYSCALL           6
  71 #define OP_MASK_SHAMT           0x1f
  72 #define OP_SH_SHAMT             6
  73 #define OP_MASK_FD              0x1f
  74 #define OP_SH_FD                6
  75 #define OP_MASK_TARGET          0x3ffffff
  76 #define OP_SH_TARGET            0
  77 #define OP_MASK_COPZ            0x1ffffff
  78 #define OP_SH_COPZ              0
  79 #define OP_MASK_IMMEDIATE       0xffff
  80 #define OP_SH_IMMEDIATE         0
  81 #define OP_MASK_DELTA           0xffff
  82 #define OP_SH_DELTA             0
  83 #define OP_MASK_FUNCT           0x3f
  84 #define OP_SH_FUNCT             0
  85 #define OP_MASK_SPEC            0x3f
  86 #define OP_SH_SPEC              0
  87
  88 /* This structure holds information for a particular instruction.  */
  89
  90 struct mips_opcode
  91 {
  92   /* The name of the instruction.  */
  93   const char *name;
  94   /* A string describing the arguments for this instruction.  */
  95   const char *args;
  96   /* The basic opcode for the instruction.  When assembling, this
  97      opcode is modified by the arguments to produce the actual opcode
  98      that is used.  */
  99   unsigned long match;
 100   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 101      relevant portions of the opcode when disassembling.  If the
 102      actual opcode anded with the match field equals the opcode field,
 103      then we have found the correct instruction.  If pinfo is
 104      INSN_MACRO, then this field is the macro identifier.  */
 105   unsigned long mask;
 106   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 107      of bits describing the instruction, notably any relevant hazard
 108      information.  */
 109   unsigned long pinfo;
 110 };
 111
 112 /* These are the characters which may appears in the args field of an
 113    instruction.  They appear in the order in which the fields appear
 114    when the instruction is used.  Commas and parentheses in the args
 115    string are ignored when assembling, and written into the output
 116    when disassembling.
 117
 118    Each of these characters corresponds to a mask field defined above.
 119
 120    "<" 5 bit shift amount (OP_*_SHAMT)
 121    "a" 26 bit target address (OP_*_TARGET)
 122    "b" 5 bit base register (OP_*_RS)
 123    "c" 10 bit breakpoint code (OP_*_CODE)
 124    "d" 5 bit destination register specifier (OP_*_RD)
 125    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 126    "j" 16 bit signed immediate (OP_*_DELTA)
 127    "o" 16 bit signed offset (OP_*_DELTA)
 128    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 129    "r" 5 bit same register used as both source and target (OP_*_RS)
 130    "s" 5 bit source register specifier (OP_*_RS)
 131    "t" 5 bit target register (OP_*_RT)
 132    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 133    "v" 5 bit same register used as both source and destination (OP_*_RS)
 134    "w" 5 bit same register used as both target and destination (OP_*_RT)
 135    "C" 25 bit coprocessor function code (OP_*_COPZ)
 136    "B" 20 bit syscall function code (OP_*_SYSCALL)
 137
 138    Floating point instructions:
 139    "D" 5 bit destination register (OP_*_FD)
 140    "S" 5 bit fs source 1 register (OP_*_FS)
 141    "T" 5 bit ft source 2 register (OP_*_FT)
 142    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 143    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 144
 145    Coprocessor instructions:
 146    "E" 5 bit target register (OP_*_RT)
 147    "G" 5 bit destination register (OP_*_RD)
 148
 149    Macro instructions:
 150    "I" 32 bit immediate
 151    "F" 64 bit floating point constant
 152 */
 153
 154 /* These are the bits which may be set in the pinfo field of an
 155    instructions, if it is not equal to INSN_MACRO.  */
 156
 157 /* Modifies the general purpose register in OP_*_RD.  */
 158 #define INSN_WRITE_GPR_D            0x00000001
 159 /* Modifies the general purpose register in OP_*_RS (FIXME: not used).  */
 160 #define INSN_WRITE_GPR_S            0x00000002
 161 /* Modifies the general purpose register in OP_*_RT.  */
 162 #define INSN_WRITE_GPR_T            0x00000004
 163 /* Modifies general purpose register 31.  */
 164 #define INSN_WRITE_GPR_31           0x00000008
 165 /* Modifies the floating point register in OP_*_FD.  */
 166 #define INSN_WRITE_FPR_D            0x00000010
 167 /* Modifies the floating point register in OP_*_FS (FIXME: not used).  */
 168 #define INSN_WRITE_FPR_S            0x00000020
 169 /* Modifies the floating point register in OP_*_FT.  */
 170 #define INSN_WRITE_FPR_T            0x00000040
 171 /* Reads the general purpose register in OP_*_RD (FIXME: not used).  */
 172 #define INSN_READ_GPR_D             0x00000080
 173 /* Reads the general purpose register in OP_*_RS.  */
 174 #define INSN_READ_GPR_S             0x00000100
 175 /* Reads the general purpose register in OP_*_RT.  */
 176 #define INSN_READ_GPR_T             0x00000200
 177 /* Reads general purpose register 31 (FIXME: not used).  */
 178 #define INSN_READ_GPR_31            0x00000400
 179 /* Reads the floating point register in OP_*_FD (FIXME: not used).  */
 180 #define INSN_READ_FPR_D             0x00000800
 181 /* Reads the floating point register in OP_*_FS.  */
 182 #define INSN_READ_FPR_S             0x00001000
 183 /* Reads the floating point register in OP_*_FT.  */
 184 #define INSN_READ_FPR_T             0x00002000
 185 /* Modifies coprocessor condition code.  */
 186 #define INSN_WRITE_COND_CODE        0x00004000
 187 /* Reads coprocessor condition code.  */
 188 #define INSN_READ_COND_CODE         0x00008000
 189 /* TLB operation.  */
 190 #define INSN_TLB                    0x00010000
 191 /* RFE (return from exception) instruction.  */
 192 #define INSN_RFE                    0x00020000
 193 /* Reads coprocessor register other than floating point register.  */
 194 #define INSN_COP                    0x00040000
 195 /* Instruction destination requires load delay.  */
 196 #define INSN_LOAD_DELAY             0x00080000
 197 /* Instruction has unconditional branch delay slot.  */
 198 #define INSN_UNCOND_BRANCH_DELAY    0x00100000
 199 /* Instruction has conditional branch delay slot.  */
 200 #define INSN_COND_BRANCH_DELAY      0x00200000
 201 /* Writes coprocessor register, requiring delay.  */
 202 #define INSN_COPROC_DELAY           0x00400000
 203 /* Reads the HI register.  */
 204 #define INSN_READ_HI                0x00800000
 205 /* Reads the LO register.  */
 206 #define INSN_READ_LO                0x01000000
 207 /* Modifies the HI register.  */
 208 #define INSN_WRITE_HI               0x02000000
 209 /* Modifies the LO register.  */
 210 #define INSN_WRITE_LO               0x04000000
 211 /* Takes a trap (FIXME: why is this interesting?).  */
 212 #define INSN_TRAP                   0x08000000
 213 /* R4000 instruction.  */
 214 #define INSN_R4000                  0x80000000
 215
 216 /* Instruction is actually a macro.  It should be ignored by the
 217    disassembler, and requires special treatment by the assembler.  */
 218 #define INSN_MACRO                  0xffffffff
 219
 220 /* This is a list of macro expanded instructions.
 221  *
 222  * _I appended means immediate
 223  * _A appended means address
 224  * _AB appended means address with base register
 225  * _D appended means floating point constant
 226  */
 227 enum {
 228     M_ABS,
 229     M_ABSU,
 230     M_ADD_I,
 231     M_ADDU_I,
 232     M_AND_I,
 233     M_BEQ_I,
 234     M_BGE,
 235     M_BGE_I,
 236     M_BGEU,
 237     M_BGEU_I,
 238     M_BGT,
 239     M_BGT_I,
 240     M_BGTU,
 241     M_BGTU_I,
 242     M_BLE,
 243     M_BLE_I,
 244     M_BLEU,
 245     M_BLEU_I,
 246     M_BLT,
 247     M_BLT_I,
 248     M_BLTU,
 249     M_BLTU_I,
 250     M_BNE_I,
 251     M_DIV_3,
 252     M_DIV_3I,
 253     M_DIVU_3,
 254     M_DIVU_3I,
 255     M_L_DOB,
 256     M_L_DAB,
 257     M_LA,
 258     M_LA_AB,
 259     M_LB_A,
 260     M_LB_AB,
 261     M_LBU_A,
 262     M_LBU_AB,
 263     M_LD_A,
 264     M_LD_OB,
 265     M_LD_AB,
 266     M_LH_A,
 267     M_LH_AB,
 268     M_LHU_A,
 269     M_LHU_AB,
 270     M_LI,
 271     M_LI_D,
 272     M_LI_DD,
 273     M_LS_A,
 274     M_LW_A,
 275     M_LW_AB,
 276     M_LWC0_A,
 277     M_LWC0_AB,
 278     M_LWC1_A,
 279     M_LWC1_AB,
 280     M_LWC2_A,
 281     M_LWC2_AB,
 282     M_LWC3_A,
 283     M_LWC3_AB,
 284     M_LWL_A,
 285     M_LWL_AB,
 286     M_LWR_A,
 287     M_LWR_AB,
 288     M_MUL,
 289     M_MUL_I,
 290     M_MULO,
 291     M_MULO_I,
 292     M_MULOU,
 293     M_MULOU_I,
 294     M_NOR_I,
 295     M_OR_I,
 296     M_REM_3,
 297     M_REM_3I,
 298     M_REMU_3,
 299     M_REMU_3I,
 300     M_ROL,
 301     M_ROL_I,
 302     M_ROR,
 303     M_ROR_I,
 304     M_S_DA,
 305     M_S_DOB,
 306     M_S_DAB,
 307     M_S_S,
 308     M_SD_A,
 309     M_SD_OB,
 310     M_SD_AB,
 311     M_SEQ,
 312     M_SEQ_I,
 313     M_SGE,
 314     M_SGE_I,
 315     M_SGEU,
 316     M_SGEU_I,
 317     M_SGT,
 318     M_SGT_I,
 319     M_SGTU,
 320     M_SGTU_I,
 321     M_SLE,
 322     M_SLE_I,
 323     M_SLEU,
 324     M_SLEU_I,
 325     M_SLT_I,
 326     M_SLTU_I,
 327     M_SNE,
 328     M_SNE_I,
 329     M_SB_A,
 330     M_SB_AB,
 331     M_SH_A,
 332     M_SH_AB,
 333     M_SW_A,
 334     M_SW_AB,
 335     M_SWC0_A,
 336     M_SWC0_AB,
 337     M_SWC1_A,
 338     M_SWC1_AB,
 339     M_SWC2_A,
 340     M_SWC2_AB,
 341     M_SWC3_A,
 342     M_SWC3_AB,
 343     M_SWL_A,
 344     M_SWL_AB,
 345     M_SWR_A,
 346     M_SWR_AB,
 347     M_SUB_I,
 348     M_SUBU_I,
 349     M_TRUNCWD,
 350     M_TRUNCWS,
 351     M_ULH,
 352     M_ULH_A,
 353     M_ULHU,
 354     M_ULHU_A,
 355     M_ULW,
 356     M_ULW_A,
 357     M_USH,
 358     M_USH_A,
 359     M_USW,
 360     M_USW_A,
 361     M_XOR_I
 362 };
 363
 364 /* Short hand so the lines aren't too long. */
 365
 366 #define LDD     INSN_LOAD_DELAY
 367 #define UBD     INSN_UNCOND_BRANCH_DELAY
 368 #define CBD     INSN_COND_BRANCH_DELAY
 369 #define COD     INSN_COPROC_DELAY
 370
 371 /* True if this instruction may require a delay slot.  */
 372 #define ANY_DELAY (LDD|UBD|CBD|COD \
 373                    |INSN_READ_HI|INSN_READ_LO \
 374                    |INSN_READ_COND_CODE|INSN_WRITE_COND_CODE)
 375
 376 #define WR_d    INSN_WRITE_GPR_D
 377 #define WR_t    INSN_WRITE_GPR_T
 378 #define WR_31   INSN_WRITE_GPR_31
 379 #define WR_D    INSN_WRITE_FPR_D
 380 #define WR_T    INSN_WRITE_FPR_T
 381 #define RD_s    INSN_READ_GPR_S
 382 #define RD_b    INSN_READ_GPR_S
 383 #define RD_t    INSN_READ_GPR_T
 384 #define RD_S    INSN_READ_FPR_S
 385 #define RD_T    INSN_READ_FPR_T
 386 #define WR_CC   INSN_WRITE_COND_CODE
 387 #define RD_CC   INSN_READ_COND_CODE
 388 #define RD_C0   INSN_COP
 389 #define RD_C1   INSN_COP
 390 #define RD_C2   INSN_COP
 391 #define RD_C3   INSN_COP
 392 #define WR_C0   INSN_COP
 393 #define WR_C1   INSN_COP
 394 #define WR_C2   INSN_COP
 395 #define WR_C3   INSN_COP
 396 #define WR_HI   INSN_WRITE_HI
 397 #define WR_LO   INSN_WRITE_LO
 398 #define RD_HI   INSN_READ_HI
 399 #define RD_LO   INSN_READ_LO
 400
 401 /* The order of overloaded instructions matters.  Label arguments and
 402    register arguments look the same. Instructions that can have either
 403    for arguments must apear in the correct order in this table for the
 404    assembler to pick the right one. In other words, entries with
 405    immediate operands must apear after the same instruction with
 406    registers.
 407
 408    Many instructions are short hand for other instructions (i.e., The
 409    jal <register> instruction is short for jalr <register>).  */
 410
 411 static const struct mips_opcode mips_opcodes[] = {
 412 /* These instructions appear first so that the disassembler will find
 413    them first.  The assemblers uses a hash table based on the
 414    instruction name anyhow.  */
 415 {"nop",     "",         0x00000000, 0xffffffff, 0               },
 416 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t            }, /* addiu */
 417 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t            }, /* ori */
 418 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO      },
 419 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s       }, /* addu */
 420 {"b",       "p",        0x10000000, 0xffff0000, UBD             }, /* beq 0,0 */
 421 {"b",       "p",        0x40100000, 0xffff0000, UBD             }, /* bgez 0 */
 422 {"bal",     "p",        0x04110000, 0xffff0000, UBD             }, /* bgezal 0 */
 423
 424 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO      },
 425 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S       },
 426 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S       },
 427 {"absu",    "d,s",      0,    (int) M_ABSU,     INSN_MACRO      },
 428 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t  },
 429 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO      },
 430 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T  },
 431 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T  },
 432 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s       },
 433 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s       },
 434 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t  },
 435 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO      },
 436 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t  },
 437 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO      },
 438 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s       },
 439 /* b is at the top of the table.  */
 440 /* bal is at the top of the table.  */
 441 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC       },
 442 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC       },
 443 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC       },
 444 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC       },
 445 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC       },
 446 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC       },
 447 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC       },
 448 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC       },
 449 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t   },
 450 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO      },
 451 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s        },
 452 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO      },
 453 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO      },
 454 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO      },
 455 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO      },
 456 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s        },
 457 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s        },
 458 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO      },
 459 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO      },
 460 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO      },
 461 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO      },
 462 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s        },
 463 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO      },
 464 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO      },
 465 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO      },
 466 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO      },
 467 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s        },
 468 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO      },
 469 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO      },
 470 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO      },
 471 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO      },
 472 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s        },
 473 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s        },
 474 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t   },
 475 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO      },
 476 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s        },
 477 {"break",   "",         0x0000000d, 0xffffffff, INSN_TRAP       },
 478 {"break",   "c",        0x0000000d, 0xfc00003f, INSN_TRAP       },
 479 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
 480 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
 481 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
 482 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC },
 483 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC },
 484 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC },
 485 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC },
 486 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC },
 487 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC },
 488 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC },
 489 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC },
 490 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
 491 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
 492 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
 493 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
 494 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
 495 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
 496 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
 497 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
 498 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
 499 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 500 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 501 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 502 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 503 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 504 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 505 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 506 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 507 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 508 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 509 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 510 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 511 #if 0
 512 /* these are not very safe to use, no bounds checking. */
 513 {"c0",      "I",        0x42000000, 0xfe000000, 0               },
 514 {"c1",      "I",        0x46000000, 0xfe000000, 0               },
 515 {"c2",      "I",        0x4a000000, 0xfe000000, 0               },
 516 {"c3",      "I",        0x4e000000, 0xfe000000, 0               },
 517 #endif
 518 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LDD|WR_t|RD_C0  },
 519 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LDD|WR_t|RD_C1  },
 520 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LDD|WR_t|RD_C1  },
 521 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LDD|WR_t|RD_C2  },
 522 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LDD|WR_t|RD_C3  },
 523 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 524 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 525 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 526 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 527 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC  },
 528 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S       },
 529 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S       },
 530 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S       },
 531 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S       },
 532 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S       },
 533 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S       },
 534 {"div",     "s,t",      0x0000001a, 0xfc00003f, RD_s|RD_t|WR_HI|WR_LO   },
 535 {"div",     "d,s,t",    0,    (int) M_DIV_3,    INSN_MACRO      },
 536 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO      },
 537 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T  },
 538 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T  },
 539 {"divu",    "s,t",      0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 540 {"divu",    "d,s,t",    0,    (int) M_DIVU_3,   INSN_MACRO      },
 541 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO      },
 542 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s        },
 543 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s        },
 544 {"j",       "a",        0x08000000, 0xfc000000, UBD             },
 545 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d   },
 546 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d   },
 547 {"jal",     "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d   },/* jalr */
 548 {"jal",     "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d   },/* jalr $ra */
 549 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31       },
 550 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO      },
 551 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO      },
 552 {"la",      "t,A",      0,    (int) M_LA,       INSN_MACRO      },
 553 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO      },
 554 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t   },
 555 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO      },
 556 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t   },
 557 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO      },
 558 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO      },
 559 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO      },
 560 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t   },
 561 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO      },
 562 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t   },
 563 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO      },
 564 /* li is at the start of the table.  */
 565 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO      },
 566 {"li.d",    "S,F",      0,    (int) M_LI_DD,    INSN_MACRO      },
 567 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t            },
 568 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t   },
 569 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO      },
 570 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, COD|RD_b|WR_CC  },
 571 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO      },
 572 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, COD|RD_b|WR_T   },
 573 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, COD|RD_b|WR_T   },
 574 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 575 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, COD|RD_b|WR_T   }, /* lwc1 */
 576 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 577 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, COD|RD_b|WR_CC  },
 578 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO      },
 579 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, COD|RD_b|WR_CC  },
 580 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO      },
 581 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t   },
 582 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO      },
 583 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t   },
 584 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO      },
 585 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LDD|WR_t|RD_C0  },
 586 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LDD|WR_t|RD_S   },
 587 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LDD|WR_t|RD_S   },
 588 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LDD|WR_t|RD_C2  },
 589 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LDD|WR_t|RD_C3  },
 590 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI      },
 591 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO      },
 592 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S       },
 593 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S       },
 594 /* move is at the top of the table.  */
 595 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC    },
 596 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_D   },
 597 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_D   },
 598 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC    },
 599 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC    },
 600 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI      },
 601 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO      },
 602 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T  },
 603 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T  },
 604 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO      },
 605 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO      },
 606 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO      },
 607 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO      },
 608 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO      },
 609 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO      },
 610 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 611 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 612 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t       }, /* sub 0 */
 613 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t       }, /* subu 0 */
 614 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S       },
 615 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S       },
 616 /* nop is at the start of the table.  */
 617 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },
 618 {"nor",     "d,v,I",    0,    (int) M_NOR_I,    INSN_MACRO      },
 619 {"not",     "d,v",      0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  }, /* nor d,s,zero */
 620 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t  },
 621 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO      },
 622 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s       },
 623 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO      },
 624 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO      },
 625 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO      },
 626 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO      },
 627 {"rfe",     "",         0x42000010, 0xffffffff, INSN_RFE        },
 628 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO      },
 629 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO      },
 630 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO      },
 631 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO      },
 632 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO      },
 633 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO      },
 634 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, RD_t|RD_b       },
 635 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO      },
 636 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO      },
 637 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO      },
 638 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO      },
 639 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO      },
 640 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO      },
 641 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO      },
 642 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO      },
 643 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO      },
 644 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO      },
 645 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO      },
 646 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO      },
 647 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO      },
 648 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, RD_t|RD_b       },
 649 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO      },
 650 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO      },
 651 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO      },
 652 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO      },
 653 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO      },
 654 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  },
 655 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* sllv */
 656 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t       },
 657 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t  },
 658 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO      },
 659 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s       },
 660 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s       },
 661 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t  },
 662 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO      },
 663 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO      },
 664 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO      },
 665 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  },
 666 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srav */
 667 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t       },
 668 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  },
 669 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srlv */
 670 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t       },
 671 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t  },
 672 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO      },
 673 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T  },
 674 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T  },
 675 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t  },
 676 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO      },
 677 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, RD_t|RD_b       },
 678 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO      },
 679 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, RD_C0|RD_b      },
 680 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO      },
 681 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, RD_T|RD_b       },
 682 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, RD_T|RD_b       },
 683 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 684 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, RD_T|RD_b       }, /* swc1 */
 685 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 686 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, RD_C2|RD_b      },
 687 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO      },
 688 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, RD_C3|RD_b      },
 689 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO      },
 690 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b       },
 691 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO      },
 692 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, RD_t|RD_b       },
 693 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO      },
 694 {"syscall", "",         0x0000000c, 0xffffffff, INSN_TRAP       },
 695 {"syscall", "B",        0x0000000c, 0xfc00003f, INSN_TRAP       },
 696 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB        },
 697 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB        },
 698 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB        },
 699 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB        },
 700 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO      },
 701 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO      },
 702 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO      },
 703 {"ulh",     "t,A",      0,    (int) M_ULH_A,    INSN_MACRO      },
 704 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO      },
 705 {"ulhu",    "t,A",      0,    (int) M_ULHU_A,   INSN_MACRO      },
 706 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO      },
 707 {"ulw",     "t,A",      0,    (int) M_ULW_A,    INSN_MACRO      },
 708 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO      },
 709 {"ush",     "t,A",      0,    (int) M_USH_A,    INSN_MACRO      },
 710 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO      },
 711 {"usw",     "t,A",      0,    (int) M_USW_A,    INSN_MACRO      },
 712 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t  },
 713 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO      },
 714 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s       },
 715 };
 716
 717 #define NUMOPCODES          (sizeof(mips_opcodes)/sizeof(*mips_opcodes))