include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Contributed by Ralph Campbell and OSF
   5    Commented and modified by Ian Lance Taylor, Cygnus Support
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 GDB, GAS, and the GNU binutils are free software; you can redistribute
  10 them and/or modify them under the terms of the GNU General Public
  11 License as published by the Free Software Foundation; either version
  12 1, or (at your option) any later version.
  13
  14 GDB, GAS, and the GNU binutils are distributed in the hope that they
  15 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  16 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  17 the GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this file; see the file COPYING.  If not, write to the Free
  21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef _MIPS_H_
  24 #define _MIPS_H_
  25
  26 /* These are bit masks and shift counts to use to access the various
  27    fields of an instruction.  To retrieve the X field of an
  28    instruction, use the expression
  29         (i >> OP_SH_X) & OP_MASK_X
  30    To set the same field (to j), use
  31         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  32
  33    Make sure you use fields that are appropriate for the instruction,
  34    of course.
  35
  36    The 'i' format uses OP, RS, RT and IMMEDIATE.
  37
  38    The 'j' format uses OP and TARGET.
  39
  40    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  41
  42    The 'b' format uses OP, RS, RT and DELTA.
  43
  44    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  45
  46    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  47
  48    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  49    breakpoint instruction are not defined; Kane says the breakpoint
  50    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  51    only use ten bits).  An optional two-operand form of break/sdbbp
  52    allows the lower ten bits to be set too, and MIPS32 and later
  53    architectures allow 20 bits to be set with a signal operand
  54    (using CODE20).
  55
  56    The syscall instruction uses CODE20.
  57
  58    The general coprocessor instructions use COPZ.  */
  59
  60 #define OP_MASK_OP              0x3f
  61 #define OP_SH_OP                26
  62 #define OP_MASK_RS              0x1f
  63 #define OP_SH_RS                21
  64 #define OP_MASK_FR              0x1f
  65 #define OP_SH_FR                21
  66 #define OP_MASK_FMT             0x1f
  67 #define OP_SH_FMT               21
  68 #define OP_MASK_BCC             0x7
  69 #define OP_SH_BCC               18
  70 #define OP_MASK_CODE            0x3ff
  71 #define OP_SH_CODE              16
  72 #define OP_MASK_CODE2           0x3ff
  73 #define OP_SH_CODE2             6
  74 #define OP_MASK_RT              0x1f
  75 #define OP_SH_RT                16
  76 #define OP_MASK_FT              0x1f
  77 #define OP_SH_FT                16
  78 #define OP_MASK_CACHE           0x1f
  79 #define OP_SH_CACHE             16
  80 #define OP_MASK_RD              0x1f
  81 #define OP_SH_RD                11
  82 #define OP_MASK_FS              0x1f
  83 #define OP_SH_FS                11
  84 #define OP_MASK_PREFX           0x1f
  85 #define OP_SH_PREFX             11
  86 #define OP_MASK_CCC             0x7
  87 #define OP_SH_CCC               8
  88 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  89 #define OP_SH_CODE20            6
  90 #define OP_MASK_SHAMT           0x1f
  91 #define OP_SH_SHAMT             6
  92 #define OP_MASK_FD              0x1f
  93 #define OP_SH_FD                6
  94 #define OP_MASK_TARGET          0x3ffffff
  95 #define OP_SH_TARGET            0
  96 #define OP_MASK_COPZ            0x1ffffff
  97 #define OP_SH_COPZ              0
  98 #define OP_MASK_IMMEDIATE       0xffff
  99 #define OP_SH_IMMEDIATE         0
 100 #define OP_MASK_DELTA           0xffff
 101 #define OP_SH_DELTA             0
 102 #define OP_MASK_FUNCT           0x3f
 103 #define OP_SH_FUNCT             0
 104 #define OP_MASK_SPEC            0x3f
 105 #define OP_SH_SPEC              0
 106 #define OP_SH_LOCC              8       /* FP condition code.  */
 107 #define OP_SH_HICC              18      /* FP condition code.  */
 108 #define OP_MASK_CC              0x7
 109 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 110 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 111 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 112 #define OP_MASK_COP1SPEC        0xf
 113 #define OP_MASK_COP1SCLR        0x4
 114 #define OP_MASK_COP1CMP         0x3
 115 #define OP_SH_COP1CMP           4
 116 #define OP_SH_FORMAT            21      /* FP short format field.  */
 117 #define OP_MASK_FORMAT          0x7
 118 #define OP_SH_TRUE              16
 119 #define OP_MASK_TRUE            0x1
 120 #define OP_SH_GE                17
 121 #define OP_MASK_GE              0x01
 122 #define OP_SH_UNSIGNED          16
 123 #define OP_MASK_UNSIGNED        0x1
 124 #define OP_SH_HINT              16
 125 #define OP_MASK_HINT            0x1f
 126 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 127 #define OP_MASK_MMI             0x3f
 128 #define OP_SH_MMISUB            6
 129 #define OP_MASK_MMISUB          0x1f
 130 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 131 #define OP_SH_PERFREG           1
 132 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 133 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 134 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 135 #define OP_MASK_CODE19          0x7ffff
 136 #define OP_SH_ALN               21
 137 #define OP_MASK_ALN             0x7
 138 #define OP_SH_VSEL              21
 139 #define OP_MASK_VSEL            0x1f
 140
 141 /* Values in the 'VSEL' field.  */
 142 #define MDMX_FMTSEL_IMM_QH      0x1d
 143 #define MDMX_FMTSEL_IMM_OB      0x1e
 144 #define MDMX_FMTSEL_VEC_QH      0x15
 145 #define MDMX_FMTSEL_VEC_OB      0x16
 146
 147 /* This structure holds information for a particular instruction.  */
 148
 149 struct mips_opcode
 150 {
 151   /* The name of the instruction.  */
 152   const char *name;
 153   /* A string describing the arguments for this instruction.  */
 154   const char *args;
 155   /* The basic opcode for the instruction.  When assembling, this
 156      opcode is modified by the arguments to produce the actual opcode
 157      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 158   unsigned long match;
 159   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 160      relevant portions of the opcode when disassembling.  If the
 161      actual opcode anded with the match field equals the opcode field,
 162      then we have found the correct instruction.  If pinfo is
 163      INSN_MACRO, then this field is the macro identifier.  */
 164   unsigned long mask;
 165   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 166      of bits describing the instruction, notably any relevant hazard
 167      information.  */
 168   unsigned long pinfo;
 169   /* A collection of bits describing the instruction sets of which this
 170      instruction or macro is a member. */
 171   unsigned long membership;
 172 };
 173
 174 /* These are the characters which may appears in the args field of an
 175    instruction.  They appear in the order in which the fields appear
 176    when the instruction is used.  Commas and parentheses in the args
 177    string are ignored when assembling, and written into the output
 178    when disassembling.
 179
 180    Each of these characters corresponds to a mask field defined above.
 181
 182    "<" 5 bit shift amount (OP_*_SHAMT)
 183    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 184    "a" 26 bit target address (OP_*_TARGET)
 185    "b" 5 bit base register (OP_*_RS)
 186    "c" 10 bit breakpoint code (OP_*_CODE)
 187    "d" 5 bit destination register specifier (OP_*_RD)
 188    "h" 5 bit prefx hint (OP_*_PREFX)
 189    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 190    "j" 16 bit signed immediate (OP_*_DELTA)
 191    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 192    "o" 16 bit signed offset (OP_*_DELTA)
 193    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 194    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 195    "r" 5 bit same register used as both source and target (OP_*_RS)
 196    "s" 5 bit source register specifier (OP_*_RS)
 197    "t" 5 bit target register (OP_*_RT)
 198    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 199    "v" 5 bit same register used as both source and destination (OP_*_RS)
 200    "w" 5 bit same register used as both target and destination (OP_*_RT)
 201    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 202        (used by clo and clz)
 203    "C" 25 bit coprocessor function code (OP_*_COPZ)
 204    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 205    "J" 19 bit wait function code (OP_*_CODE19)
 206    "x" accept and ignore register name
 207    "z" must be zero register
 208
 209    Floating point instructions:
 210    "D" 5 bit destination register (OP_*_FD)
 211    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 212    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 213    "S" 5 bit fs source 1 register (OP_*_FS)
 214    "T" 5 bit ft source 2 register (OP_*_FT)
 215    "R" 5 bit fr source 3 register (OP_*_FR)
 216    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 217    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 218
 219    Coprocessor instructions:
 220    "E" 5 bit target register (OP_*_RT)
 221    "G" 5 bit destination register (OP_*_RD)
 222    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 223    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 224
 225    Macro instructions:
 226    "A" General 32 bit expression
 227    "I" 32 bit immediate
 228    "F" 64 bit floating point constant in .rdata
 229    "L" 64 bit floating point constant in .lit8
 230    "f" 32 bit floating point constant
 231    "l" 32 bit floating point constant in .lit4
 232
 233    MDMX instruction operands (note that while these use the FP register
 234    fields, they accept both $fN and $vN names for the registers):
 235    "O"  MDMX alignment offset (OP_*_ALN)
 236    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 237    "X"  MDMX destination register (OP_*_FD)
 238    "Y"  MDMX source register (OP_*_FS)
 239    "Z"  MDMX source register (OP_*_FT)
 240
 241    Other:
 242    "()" parens surrounding optional value
 243    ","  separates operands
 244
 245    Characters used so far, for quick reference when adding more:
 246    "<>(),"
 247    "ABCDEFGHIJLMNOPQRSTUVWXYZ"
 248    "abcdfhijklopqrstuvwxz"
 249 */
 250
 251 /* These are the bits which may be set in the pinfo field of an
 252    instructions, if it is not equal to INSN_MACRO.  */
 253
 254 /* Modifies the general purpose register in OP_*_RD.  */
 255 #define INSN_WRITE_GPR_D            0x00000001
 256 /* Modifies the general purpose register in OP_*_RT.  */
 257 #define INSN_WRITE_GPR_T            0x00000002
 258 /* Modifies general purpose register 31.  */
 259 #define INSN_WRITE_GPR_31           0x00000004
 260 /* Modifies the floating point register in OP_*_FD.  */
 261 #define INSN_WRITE_FPR_D            0x00000008
 262 /* Modifies the floating point register in OP_*_FS.  */
 263 #define INSN_WRITE_FPR_S            0x00000010
 264 /* Modifies the floating point register in OP_*_FT.  */
 265 #define INSN_WRITE_FPR_T            0x00000020
 266 /* Reads the general purpose register in OP_*_RS.  */
 267 #define INSN_READ_GPR_S             0x00000040
 268 /* Reads the general purpose register in OP_*_RT.  */
 269 #define INSN_READ_GPR_T             0x00000080
 270 /* Reads the floating point register in OP_*_FS.  */
 271 #define INSN_READ_FPR_S             0x00000100
 272 /* Reads the floating point register in OP_*_FT.  */
 273 #define INSN_READ_FPR_T             0x00000200
 274 /* Reads the floating point register in OP_*_FR.  */
 275 #define INSN_READ_FPR_R             0x00000400
 276 /* Modifies coprocessor condition code.  */
 277 #define INSN_WRITE_COND_CODE        0x00000800
 278 /* Reads coprocessor condition code.  */
 279 #define INSN_READ_COND_CODE         0x00001000
 280 /* TLB operation.  */
 281 #define INSN_TLB                    0x00002000
 282 /* Reads coprocessor register other than floating point register.  */
 283 #define INSN_COP                    0x00004000
 284 /* Instruction loads value from memory, requiring delay.  */
 285 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 286 /* Instruction loads value from coprocessor, requiring delay.  */
 287 #define INSN_LOAD_COPROC_DELAY      0x00010000
 288 /* Instruction has unconditional branch delay slot.  */
 289 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 290 /* Instruction has conditional branch delay slot.  */
 291 #define INSN_COND_BRANCH_DELAY      0x00040000
 292 /* Conditional branch likely: if branch not taken, insn nullified.  */
 293 #define INSN_COND_BRANCH_LIKELY     0x00080000
 294 /* Moves to coprocessor register, requiring delay.  */
 295 #define INSN_COPROC_MOVE_DELAY      0x00100000
 296 /* Loads coprocessor register from memory, requiring delay.  */
 297 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 298 /* Reads the HI register.  */
 299 #define INSN_READ_HI                0x00400000
 300 /* Reads the LO register.  */
 301 #define INSN_READ_LO                0x00800000
 302 /* Modifies the HI register.  */
 303 #define INSN_WRITE_HI               0x01000000
 304 /* Modifies the LO register.  */
 305 #define INSN_WRITE_LO               0x02000000
 306 /* Takes a trap (easier to keep out of delay slot).  */
 307 #define INSN_TRAP                   0x04000000
 308 /* Instruction stores value into memory.  */
 309 #define INSN_STORE_MEMORY           0x08000000
 310 /* Instruction uses single precision floating point.  */
 311 #define FP_S                        0x10000000
 312 /* Instruction uses double precision floating point.  */
 313 #define FP_D                        0x20000000
 314 /* Instruction is part of the tx39's integer multiply family.    */
 315 #define INSN_MULT                   0x40000000
 316 /* Instruction synchronize shared memory.  */
 317 #define INSN_SYNC                   0x80000000
 318 /* Instruction reads MDMX accumulator.  XXX FIXME: No bits left!  */
 319 #define INSN_READ_MDMX_ACC          0
 320 /* Instruction writes MDMX accumulator.  XXX FIXME: No bits left!  */
 321 #define INSN_WRITE_MDMX_ACC         0
 322
 323 /* Instruction is actually a macro.  It should be ignored by the
 324    disassembler, and requires special treatment by the assembler.  */
 325 #define INSN_MACRO                  0xffffffff
 326
 327 /* Masks used to mark instructions to indicate which MIPS ISA level
 328    they were introduced in.  ISAs, as defined below, are logical
 329    ORs of these bits, indicatingthat they support the instructions
 330    defined at the given level.  */
 331
 332 #define INSN_ISA_MASK             0x00000fff
 333 #define INSN_ISA1                 0x00000010
 334 #define INSN_ISA2                 0x00000020
 335 #define INSN_ISA3                 0x00000040
 336 #define INSN_ISA4                 0x00000080
 337 #define INSN_ISA5                 0x00000100
 338 #define INSN_ISA32                0x00000200
 339 #define INSN_ISA64                0x00000400
 340
 341 /* Masks used for MIPS-defined ASEs.  */
 342
 343 /* MIPS-3D ASE */
 344 #define INSN_MIPS3D               0x00004000
 345 /* MDMX ASE */
 346 #define INSN_MDMX                 0x00008000
 347
 348 /* Chip specific instructions.  These are bitmasks.  */
 349
 350 /* MIPS R4650 instruction.  */
 351 #define INSN_4650                 0x00010000
 352 /* LSI R4010 instruction.  */
 353 #define INSN_4010                 0x00020000
 354 /* NEC VR4100 instruction.  */
 355 #define INSN_4100                 0x00040000
 356 /* Toshiba R3900 instruction.  */
 357 #define INSN_3900                 0x00080000
 358 /* MIPS R10000 instruction.  */
 359 #define INSN_10000                0x00100000
 360 /* Broadcom SB-1 instruction.  */
 361 #define INSN_SB1                  0x00200000
 362
 363 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 364
 365 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 366 #define       ISA_MIPS1       (INSN_ISA1)
 367 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 368 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 369 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 370 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 371 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 372 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 373
 374 /* CPU defines, use instead of hardcoding processor number. Keep this
 375    in sync with bfd/archures.c in order for machine selection to work.  */
 376 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 377 #define CPU_R2000       2000
 378 #define CPU_R3000       3000
 379 #define CPU_R3900       3900
 380 #define CPU_R4000       4000
 381 #define CPU_R4010       4010
 382 #define CPU_VR4100      4100
 383 #define CPU_R4111       4111
 384 #define CPU_R4300       4300
 385 #define CPU_R4400       4400
 386 #define CPU_R4600       4600
 387 #define CPU_R4650       4650
 388 #define CPU_R5000       5000
 389 #define CPU_R6000       6000
 390 #define CPU_R8000       8000
 391 #define CPU_R10000      10000
 392 #define CPU_R12000      12000
 393 #define CPU_MIPS16      16
 394 #define CPU_MIPS32      32
 395 #define CPU_MIPS5       5
 396 #define CPU_MIPS64      64
 397 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 398
 399 /* Test for membership in an ISA including chip specific ISAs.  INSN
 400    is pointer to an element of the opcode table; ISA is the specified
 401    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 402    test, or zero if no CPU specific ISA test is desired.  */
 403
 404 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 405     (((insn)->membership & isa) != 0                                    \
 406      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 407      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 408      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)                        \
 409          && ((insn)->membership & INSN_4100) != 0)                      \
 410      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 411      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 412          && ((insn)->membership & INSN_10000) != 0)                     \
 413      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 414      || 0)      /* Please keep this term for easier source merging.  */
 415
 416 /* This is a list of macro expanded instructions.
 417
 418    _I appended means immediate
 419    _A appended means address
 420    _AB appended means address with base register
 421    _D appended means 64 bit floating point constant
 422    _S appended means 32 bit floating point constant.  */
 423
 424 enum
 425 {
 426   M_ABS,
 427   M_ADD_I,
 428   M_ADDU_I,
 429   M_AND_I,
 430   M_BEQ,
 431   M_BEQ_I,
 432   M_BEQL_I,
 433   M_BGE,
 434   M_BGEL,
 435   M_BGE_I,
 436   M_BGEL_I,
 437   M_BGEU,
 438   M_BGEUL,
 439   M_BGEU_I,
 440   M_BGEUL_I,
 441   M_BGT,
 442   M_BGTL,
 443   M_BGT_I,
 444   M_BGTL_I,
 445   M_BGTU,
 446   M_BGTUL,
 447   M_BGTU_I,
 448   M_BGTUL_I,
 449   M_BLE,
 450   M_BLEL,
 451   M_BLE_I,
 452   M_BLEL_I,
 453   M_BLEU,
 454   M_BLEUL,
 455   M_BLEU_I,
 456   M_BLEUL_I,
 457   M_BLT,
 458   M_BLTL,
 459   M_BLT_I,
 460   M_BLTL_I,
 461   M_BLTU,
 462   M_BLTUL,
 463   M_BLTU_I,
 464   M_BLTUL_I,
 465   M_BNE,
 466   M_BNE_I,
 467   M_BNEL_I,
 468   M_DABS,
 469   M_DADD_I,
 470   M_DADDU_I,
 471   M_DDIV_3,
 472   M_DDIV_3I,
 473   M_DDIVU_3,
 474   M_DDIVU_3I,
 475   M_DIV_3,
 476   M_DIV_3I,
 477   M_DIVU_3,
 478   M_DIVU_3I,
 479   M_DLA_AB,
 480   M_DLI,
 481   M_DMUL,
 482   M_DMUL_I,
 483   M_DMULO,
 484   M_DMULO_I,
 485   M_DMULOU,
 486   M_DMULOU_I,
 487   M_DREM_3,
 488   M_DREM_3I,
 489   M_DREMU_3,
 490   M_DREMU_3I,
 491   M_DSUB_I,
 492   M_DSUBU_I,
 493   M_DSUBU_I_2,
 494   M_J_A,
 495   M_JAL_1,
 496   M_JAL_2,
 497   M_JAL_A,
 498   M_L_DOB,
 499   M_L_DAB,
 500   M_LA_AB,
 501   M_LB_A,
 502   M_LB_AB,
 503   M_LBU_A,
 504   M_LBU_AB,
 505   M_LD_A,
 506   M_LD_OB,
 507   M_LD_AB,
 508   M_LDC1_AB,
 509   M_LDC2_AB,
 510   M_LDC3_AB,
 511   M_LDL_AB,
 512   M_LDR_AB,
 513   M_LH_A,
 514   M_LH_AB,
 515   M_LHU_A,
 516   M_LHU_AB,
 517   M_LI,
 518   M_LI_D,
 519   M_LI_DD,
 520   M_LI_S,
 521   M_LI_SS,
 522   M_LL_AB,
 523   M_LLD_AB,
 524   M_LS_A,
 525   M_LW_A,
 526   M_LW_AB,
 527   M_LWC0_A,
 528   M_LWC0_AB,
 529   M_LWC1_A,
 530   M_LWC1_AB,
 531   M_LWC2_A,
 532   M_LWC2_AB,
 533   M_LWC3_A,
 534   M_LWC3_AB,
 535   M_LWL_A,
 536   M_LWL_AB,
 537   M_LWR_A,
 538   M_LWR_AB,
 539   M_LWU_AB,
 540   M_MOVE,
 541   M_MUL,
 542   M_MUL_I,
 543   M_MULO,
 544   M_MULO_I,
 545   M_MULOU,
 546   M_MULOU_I,
 547   M_NOR_I,
 548   M_OR_I,
 549   M_REM_3,
 550   M_REM_3I,
 551   M_REMU_3,
 552   M_REMU_3I,
 553   M_DROL,
 554   M_ROL,
 555   M_DROL_I,
 556   M_ROL_I,
 557   M_DROR,
 558   M_ROR,
 559   M_DROR_I,
 560   M_ROR_I,
 561   M_S_DA,
 562   M_S_DOB,
 563   M_S_DAB,
 564   M_S_S,
 565   M_SC_AB,
 566   M_SCD_AB,
 567   M_SD_A,
 568   M_SD_OB,
 569   M_SD_AB,
 570   M_SDC1_AB,
 571   M_SDC2_AB,
 572   M_SDC3_AB,
 573   M_SDL_AB,
 574   M_SDR_AB,
 575   M_SEQ,
 576   M_SEQ_I,
 577   M_SGE,
 578   M_SGE_I,
 579   M_SGEU,
 580   M_SGEU_I,
 581   M_SGT,
 582   M_SGT_I,
 583   M_SGTU,
 584   M_SGTU_I,
 585   M_SLE,
 586   M_SLE_I,
 587   M_SLEU,
 588   M_SLEU_I,
 589   M_SLT_I,
 590   M_SLTU_I,
 591   M_SNE,
 592   M_SNE_I,
 593   M_SB_A,
 594   M_SB_AB,
 595   M_SH_A,
 596   M_SH_AB,
 597   M_SW_A,
 598   M_SW_AB,
 599   M_SWC0_A,
 600   M_SWC0_AB,
 601   M_SWC1_A,
 602   M_SWC1_AB,
 603   M_SWC2_A,
 604   M_SWC2_AB,
 605   M_SWC3_A,
 606   M_SWC3_AB,
 607   M_SWL_A,
 608   M_SWL_AB,
 609   M_SWR_A,
 610   M_SWR_AB,
 611   M_SUB_I,
 612   M_SUBU_I,
 613   M_SUBU_I_2,
 614   M_TEQ_I,
 615   M_TGE_I,
 616   M_TGEU_I,
 617   M_TLT_I,
 618   M_TLTU_I,
 619   M_TNE_I,
 620   M_TRUNCWD,
 621   M_TRUNCWS,
 622   M_ULD,
 623   M_ULD_A,
 624   M_ULH,
 625   M_ULH_A,
 626   M_ULHU,
 627   M_ULHU_A,
 628   M_ULW,
 629   M_ULW_A,
 630   M_USH,
 631   M_USH_A,
 632   M_USW,
 633   M_USW_A,
 634   M_USD,
 635   M_USD_A,
 636   M_XOR_I,
 637   M_COP0,
 638   M_COP1,
 639   M_COP2,
 640   M_COP3,
 641   M_NUM_MACROS
 642 };
 643
 644
 645 /* The order of overloaded instructions matters.  Label arguments and
 646    register arguments look the same. Instructions that can have either
 647    for arguments must apear in the correct order in this table for the
 648    assembler to pick the right one. In other words, entries with
 649    immediate operands must apear after the same instruction with
 650    registers.
 651
 652    Many instructions are short hand for other instructions (i.e., The
 653    jal <register> instruction is short for jalr <register>).  */
 654
 655 extern const struct mips_opcode mips_builtin_opcodes[];
 656 extern const int bfd_mips_num_builtin_opcodes;
 657 extern struct mips_opcode *mips_opcodes;
 658 extern int bfd_mips_num_opcodes;
 659 #define NUMOPCODES bfd_mips_num_opcodes
 660
 661 \f
 662 /* The rest of this file adds definitions for the mips16 TinyRISC
 663    processor.  */
 664
 665 /* These are the bitmasks and shift counts used for the different
 666    fields in the instruction formats.  Other than OP, no masks are
 667    provided for the fixed portions of an instruction, since they are
 668    not needed.
 669
 670    The I format uses IMM11.
 671
 672    The RI format uses RX and IMM8.
 673
 674    The RR format uses RX, and RY.
 675
 676    The RRI format uses RX, RY, and IMM5.
 677
 678    The RRR format uses RX, RY, and RZ.
 679
 680    The RRI_A format uses RX, RY, and IMM4.
 681
 682    The SHIFT format uses RX, RY, and SHAMT.
 683
 684    The I8 format uses IMM8.
 685
 686    The I8_MOVR32 format uses RY and REGR32.
 687
 688    The IR_MOV32R format uses REG32R and MOV32Z.
 689
 690    The I64 format uses IMM8.
 691
 692    The RI64 format uses RY and IMM5.
 693    */
 694
 695 #define MIPS16OP_MASK_OP        0x1f
 696 #define MIPS16OP_SH_OP          11
 697 #define MIPS16OP_MASK_IMM11     0x7ff
 698 #define MIPS16OP_SH_IMM11       0
 699 #define MIPS16OP_MASK_RX        0x7
 700 #define MIPS16OP_SH_RX          8
 701 #define MIPS16OP_MASK_IMM8      0xff
 702 #define MIPS16OP_SH_IMM8        0
 703 #define MIPS16OP_MASK_RY        0x7
 704 #define MIPS16OP_SH_RY          5
 705 #define MIPS16OP_MASK_IMM5      0x1f
 706 #define MIPS16OP_SH_IMM5        0
 707 #define MIPS16OP_MASK_RZ        0x7
 708 #define MIPS16OP_SH_RZ          2
 709 #define MIPS16OP_MASK_IMM4      0xf
 710 #define MIPS16OP_SH_IMM4        0
 711 #define MIPS16OP_MASK_REGR32    0x1f
 712 #define MIPS16OP_SH_REGR32      0
 713 #define MIPS16OP_MASK_REG32R    0x1f
 714 #define MIPS16OP_SH_REG32R      3
 715 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 716 #define MIPS16OP_MASK_MOVE32Z   0x7
 717 #define MIPS16OP_SH_MOVE32Z     0
 718 #define MIPS16OP_MASK_IMM6      0x3f
 719 #define MIPS16OP_SH_IMM6        5
 720
 721 /* These are the characters which may appears in the args field of an
 722    instruction.  They appear in the order in which the fields appear
 723    when the instruction is used.  Commas and parentheses in the args
 724    string are ignored when assembling, and written into the output
 725    when disassembling.
 726
 727    "y" 3 bit register (MIPS16OP_*_RY)
 728    "x" 3 bit register (MIPS16OP_*_RX)
 729    "z" 3 bit register (MIPS16OP_*_RZ)
 730    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 731    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 732    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 733    "0" zero register ($0)
 734    "S" stack pointer ($sp or $29)
 735    "P" program counter
 736    "R" return address register ($ra or $31)
 737    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 738    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 739    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 740    "a" 26 bit jump address
 741    "e" 11 bit extension value
 742    "l" register list for entry instruction
 743    "L" register list for exit instruction
 744
 745    The remaining codes may be extended.  Except as otherwise noted,
 746    the full extended operand is a 16 bit signed value.
 747    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 748    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 749    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 750    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 751    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 752    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 753    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 754    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 755    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 756    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 757    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 758    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 759    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 760    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 761    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 762    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 763    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 764    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 765    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 766    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
 767    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
 768    */
 769
 770 /* For the mips16, we use the same opcode table format and a few of
 771    the same flags.  However, most of the flags are different.  */
 772
 773 /* Modifies the register in MIPS16OP_*_RX.  */
 774 #define MIPS16_INSN_WRITE_X                 0x00000001
 775 /* Modifies the register in MIPS16OP_*_RY.  */
 776 #define MIPS16_INSN_WRITE_Y                 0x00000002
 777 /* Modifies the register in MIPS16OP_*_RZ.  */
 778 #define MIPS16_INSN_WRITE_Z                 0x00000004
 779 /* Modifies the T ($24) register.  */
 780 #define MIPS16_INSN_WRITE_T                 0x00000008
 781 /* Modifies the SP ($29) register.  */
 782 #define MIPS16_INSN_WRITE_SP                0x00000010
 783 /* Modifies the RA ($31) register.  */
 784 #define MIPS16_INSN_WRITE_31                0x00000020
 785 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
 786 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
 787 /* Reads the register in MIPS16OP_*_RX.  */
 788 #define MIPS16_INSN_READ_X                  0x00000080
 789 /* Reads the register in MIPS16OP_*_RY.  */
 790 #define MIPS16_INSN_READ_Y                  0x00000100
 791 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
 792 #define MIPS16_INSN_READ_Z                  0x00000200
 793 /* Reads the T ($24) register.  */
 794 #define MIPS16_INSN_READ_T                  0x00000400
 795 /* Reads the SP ($29) register.  */
 796 #define MIPS16_INSN_READ_SP                 0x00000800
 797 /* Reads the RA ($31) register.  */
 798 #define MIPS16_INSN_READ_31                 0x00001000
 799 /* Reads the program counter.  */
 800 #define MIPS16_INSN_READ_PC                 0x00002000
 801 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 802 #define MIPS16_INSN_READ_GPR_X              0x00004000
 803 /* Is a branch insn. */
 804 #define MIPS16_INSN_BRANCH                  0x00010000
 805
 806 /* The following flags have the same value for the mips16 opcode
 807    table:
 808    INSN_UNCOND_BRANCH_DELAY
 809    INSN_COND_BRANCH_DELAY
 810    INSN_COND_BRANCH_LIKELY (never used)
 811    INSN_READ_HI
 812    INSN_READ_LO
 813    INSN_WRITE_HI
 814    INSN_WRITE_LO
 815    INSN_TRAP
 816    INSN_ISA3
 817    */
 818
 819 extern const struct mips_opcode mips16_opcodes[];
 820 extern const int bfd_mips16_num_opcodes;
 821
 822 #endif /* _MIPS_H_ */