include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1995 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 /* These are bit masks and shift counts to use to access the various
  23    fields of an instruction.  To retrieve the X field of an
  24    instruction, use the expression
  25         (i >> OP_SH_X) & OP_MASK_X
  26    To set the same field (to j), use
  27         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  28
  29    Make sure you use fields that are appropriate for the instruction,
  30    of course.
  31
  32    The 'i' format uses OP, RS, RT and IMMEDIATE.
  33
  34    The 'j' format uses OP and TARGET.
  35
  36    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  37
  38    The 'b' format uses OP, RS, RT and DELTA.
  39
  40    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  41
  42    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  43
  44    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  45    breakpoint instruction are not defined; Kane says the breakpoint
  46    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  47    only use ten bits).
  48
  49    The syscall instruction uses SYSCALL.
  50
  51    The general coprocessor instructions use COPZ.  */
  52
  53 #define OP_MASK_OP              0x3f
  54 #define OP_SH_OP                26
  55 #define OP_MASK_RS              0x1f
  56 #define OP_SH_RS                21
  57 #define OP_MASK_FR              0x1f
  58 #define OP_SH_FR                21
  59 #define OP_MASK_FMT             0x1f
  60 #define OP_SH_FMT               21
  61 #define OP_MASK_BCC             0x7
  62 #define OP_SH_BCC               18
  63 #define OP_MASK_CODE            0x3ff
  64 #define OP_SH_CODE              16
  65 #define OP_MASK_RT              0x1f
  66 #define OP_SH_RT                16
  67 #define OP_MASK_FT              0x1f
  68 #define OP_SH_FT                16
  69 #define OP_MASK_CACHE           0x1f
  70 #define OP_SH_CACHE             16
  71 #define OP_MASK_RD              0x1f
  72 #define OP_SH_RD                11
  73 #define OP_MASK_FS              0x1f
  74 #define OP_SH_FS                11
  75 #define OP_MASK_PREFX           0x1f
  76 #define OP_SH_PREFX             11
  77 #define OP_MASK_CCC             0x7
  78 #define OP_SH_CCC               8
  79 #define OP_MASK_SYSCALL         0xfffff
  80 #define OP_SH_SYSCALL           6
  81 #define OP_MASK_SHAMT           0x1f
  82 #define OP_SH_SHAMT             6
  83 #define OP_MASK_FD              0x1f
  84 #define OP_SH_FD                6
  85 #define OP_MASK_TARGET          0x3ffffff
  86 #define OP_SH_TARGET            0
  87 #define OP_MASK_COPZ            0x1ffffff
  88 #define OP_SH_COPZ              0
  89 #define OP_MASK_IMMEDIATE       0xffff
  90 #define OP_SH_IMMEDIATE         0
  91 #define OP_MASK_DELTA           0xffff
  92 #define OP_SH_DELTA             0
  93 #define OP_MASK_FUNCT           0x3f
  94 #define OP_SH_FUNCT             0
  95 #define OP_MASK_SPEC            0x3f
  96 #define OP_SH_SPEC              0
  97
  98 /* This structure holds information for a particular instruction.  */
  99
 100 struct mips_opcode
 101 {
 102   /* The name of the instruction.  */
 103   const char *name;
 104   /* A string describing the arguments for this instruction.  */
 105   const char *args;
 106   /* The basic opcode for the instruction.  When assembling, this
 107      opcode is modified by the arguments to produce the actual opcode
 108      that is used.  If pinfo is INSN_MACRO, then this is instead the
 109      ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
 110      etc.).  */
 111   unsigned long match;
 112   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 113      relevant portions of the opcode when disassembling.  If the
 114      actual opcode anded with the match field equals the opcode field,
 115      then we have found the correct instruction.  If pinfo is
 116      INSN_MACRO, then this field is the macro identifier.  */
 117   unsigned long mask;
 118   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 119      of bits describing the instruction, notably any relevant hazard
 120      information.  */
 121   unsigned long pinfo;
 122 };
 123
 124 /* These are the characters which may appears in the args field of an
 125    instruction.  They appear in the order in which the fields appear
 126    when the instruction is used.  Commas and parentheses in the args
 127    string are ignored when assembling, and written into the output
 128    when disassembling.
 129
 130    Each of these characters corresponds to a mask field defined above.
 131
 132    "<" 5 bit shift amount (OP_*_SHAMT)
 133    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 134    "a" 26 bit target address (OP_*_TARGET)
 135    "b" 5 bit base register (OP_*_RS)
 136    "c" 10 bit breakpoint code (OP_*_CODE)
 137    "d" 5 bit destination register specifier (OP_*_RD)
 138    "h" 5 bit prefx hint (OP_*_PREFX)
 139    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 140    "j" 16 bit signed immediate (OP_*_DELTA)
 141    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 142    "o" 16 bit signed offset (OP_*_DELTA)
 143    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 144    "r" 5 bit same register used as both source and target (OP_*_RS)
 145    "s" 5 bit source register specifier (OP_*_RS)
 146    "t" 5 bit target register (OP_*_RT)
 147    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 148    "v" 5 bit same register used as both source and destination (OP_*_RS)
 149    "w" 5 bit same register used as both target and destination (OP_*_RT)
 150    "C" 25 bit coprocessor function code (OP_*_COPZ)
 151    "B" 20 bit syscall function code (OP_*_SYSCALL)
 152    "x" accept and ignore register name
 153    "z" must be zero register
 154
 155    Floating point instructions:
 156    "D" 5 bit destination register (OP_*_FD)
 157    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 158    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 159    "S" 5 bit fs source 1 register (OP_*_FS)
 160    "T" 5 bit ft source 2 register (OP_*_FT)
 161    "R" 5 bit fr source 3 register (OP_*_FR)
 162    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 163    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 164
 165    Coprocessor instructions:
 166    "E" 5 bit target register (OP_*_RT)
 167    "G" 5 bit destination register (OP_*_RD)
 168
 169    Macro instructions:
 170    "A" General 32 bit expression
 171    "I" 32 bit immediate
 172    "F" 64 bit floating point constant in .rdata
 173    "L" 64 bit floating point constant in .lit8
 174    "f" 32 bit floating point constant
 175    "l" 32 bit floating point constant in .lit4
 176 */
 177
 178 /* These are the bits which may be set in the pinfo field of an
 179    instructions, if it is not equal to INSN_MACRO.  */
 180
 181 /* Modifies the general purpose register in OP_*_RD.  */
 182 #define INSN_WRITE_GPR_D            0x00000001
 183 /* Modifies the general purpose register in OP_*_RT.  */
 184 #define INSN_WRITE_GPR_T            0x00000002
 185 /* Modifies general purpose register 31.  */
 186 #define INSN_WRITE_GPR_31           0x00000004
 187 /* Modifies the floating point register in OP_*_FD.  */
 188 #define INSN_WRITE_FPR_D            0x00000008
 189 /* Modifies the floating point register in OP_*_FS.  */
 190 #define INSN_WRITE_FPR_S            0x00000010
 191 /* Modifies the floating point register in OP_*_FT.  */
 192 #define INSN_WRITE_FPR_T            0x00000020
 193 /* Reads the general purpose register in OP_*_RS.  */
 194 #define INSN_READ_GPR_S             0x00000040
 195 /* Reads the general purpose register in OP_*_RT.  */
 196 #define INSN_READ_GPR_T             0x00000080
 197 /* Reads the floating point register in OP_*_FS.  */
 198 #define INSN_READ_FPR_S             0x00000100
 199 /* Reads the floating point register in OP_*_FT.  */
 200 #define INSN_READ_FPR_T             0x00000200
 201 /* Reads the floating point register in OP_*_FR.  */
 202 #define INSN_READ_FPR_R             0x00000400
 203 /* Modifies coprocessor condition code.  */
 204 #define INSN_WRITE_COND_CODE        0x00000800
 205 /* Reads coprocessor condition code.  */
 206 #define INSN_READ_COND_CODE         0x00001000
 207 /* TLB operation.  */
 208 #define INSN_TLB                    0x00002000
 209 /* Reads coprocessor register other than floating point register.  */
 210 #define INSN_COP                    0x00004000
 211 /* Instruction loads value from memory, requiring delay.  */
 212 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 213 /* Instruction loads value from coprocessor, requiring delay.  */
 214 #define INSN_LOAD_COPROC_DELAY      0x00010000
 215 /* Instruction has unconditional branch delay slot.  */
 216 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 217 /* Instruction has conditional branch delay slot.  */
 218 #define INSN_COND_BRANCH_DELAY      0x00040000
 219 /* Conditional branch likely: if branch not taken, insn nullified.  */
 220 #define INSN_COND_BRANCH_LIKELY     0x00080000
 221 /* Moves to coprocessor register, requiring delay.  */
 222 #define INSN_COPROC_MOVE_DELAY      0x00100000
 223 /* Loads coprocessor register from memory, requiring delay.  */
 224 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 225 /* Reads the HI register.  */
 226 #define INSN_READ_HI                0x00400000
 227 /* Reads the LO register.  */
 228 #define INSN_READ_LO                0x00800000
 229 /* Modifies the HI register.  */
 230 #define INSN_WRITE_HI               0x01000000
 231 /* Modifies the LO register.  */
 232 #define INSN_WRITE_LO               0x02000000
 233 /* Takes a trap (easier to keep out of delay slot).  */
 234 #define INSN_TRAP                   0x04000000
 235 /* Instruction stores value into memory.  */
 236 #define INSN_STORE_MEMORY           0x08000000
 237 /* MIPS ISA field--CPU level at which insn is supported.  */
 238 #define INSN_ISA                    0x70000000
 239 /* MIPS ISA 2 instruction (R6000 or R4000).  */
 240 #define INSN_ISA2                   0x10000000
 241 /* MIPS ISA 3 instruction (R4000).  */
 242 #define INSN_ISA3                   0x20000000
 243 /* MIPS R4650 instruction.  */
 244 #define INSN_4650                   0x30000000
 245 /* MIPS ISA 4 instruction (R8000).  */
 246 #define INSN_ISA4                   0x40000000
 247 /* LSI R4010 instruction.  */
 248 #define INSN_4010                   0x50000000
 249
 250 /* Instruction is actually a macro.  It should be ignored by the
 251    disassembler, and requires special treatment by the assembler.  */
 252 #define INSN_MACRO                  0xffffffff
 253
 254 /* This is a list of macro expanded instructions.
 255  *
 256  * _I appended means immediate
 257  * _A appended means address
 258  * _AB appended means address with base register
 259  * _D appended means 64 bit floating point constant
 260  * _S appended means 32 bit floating point constant
 261  */
 262 enum {
 263     M_ABS,
 264     M_ADD_I,
 265     M_ADDU_I,
 266     M_AND_I,
 267     M_BEQ_I,
 268     M_BEQL_I,
 269     M_BGE,
 270     M_BGEL,
 271     M_BGE_I,
 272     M_BGEL_I,
 273     M_BGEU,
 274     M_BGEUL,
 275     M_BGEU_I,
 276     M_BGEUL_I,
 277     M_BGT,
 278     M_BGTL,
 279     M_BGT_I,
 280     M_BGTL_I,
 281     M_BGTU,
 282     M_BGTUL,
 283     M_BGTU_I,
 284     M_BGTUL_I,
 285     M_BLE,
 286     M_BLEL,
 287     M_BLE_I,
 288     M_BLEL_I,
 289     M_BLEU,
 290     M_BLEUL,
 291     M_BLEU_I,
 292     M_BLEUL_I,
 293     M_BLT,
 294     M_BLTL,
 295     M_BLT_I,
 296     M_BLTL_I,
 297     M_BLTU,
 298     M_BLTUL,
 299     M_BLTU_I,
 300     M_BLTUL_I,
 301     M_BNE_I,
 302     M_BNEL_I,
 303     M_DABS,
 304     M_DADD_I,
 305     M_DADDU_I,
 306     M_DDIV_3,
 307     M_DDIV_3I,
 308     M_DDIVU_3,
 309     M_DDIVU_3I,
 310     M_DIV_3,
 311     M_DIV_3I,
 312     M_DIVU_3,
 313     M_DIVU_3I,
 314     M_DLA_AB,
 315     M_DLI,
 316     M_DMUL,
 317     M_DMUL_I,
 318     M_DMULO,
 319     M_DMULO_I,
 320     M_DMULOU,
 321     M_DMULOU_I,
 322     M_DREM_3,
 323     M_DREM_3I,
 324     M_DREMU_3,
 325     M_DREMU_3I,
 326     M_DSUB_I,
 327     M_DSUBU_I,
 328     M_J_A,
 329     M_JAL_1,
 330     M_JAL_2,
 331     M_JAL_A,
 332     M_L_DOB,
 333     M_L_DAB,
 334     M_LA_AB,
 335     M_LB_A,
 336     M_LB_AB,
 337     M_LBU_A,
 338     M_LBU_AB,
 339     M_LD_A,
 340     M_LD_OB,
 341     M_LD_AB,
 342     M_LDC1_AB,
 343     M_LDC2_AB,
 344     M_LDC3_AB,
 345     M_LDL_AB,
 346     M_LDR_AB,
 347     M_LH_A,
 348     M_LH_AB,
 349     M_LHU_A,
 350     M_LHU_AB,
 351     M_LI,
 352     M_LI_D,
 353     M_LI_DD,
 354     M_LI_S,
 355     M_LI_SS,
 356     M_LL_AB,
 357     M_LLD_AB,
 358     M_LS_A,
 359     M_LW_A,
 360     M_LW_AB,
 361     M_LWC0_A,
 362     M_LWC0_AB,
 363     M_LWC1_A,
 364     M_LWC1_AB,
 365     M_LWC2_A,
 366     M_LWC2_AB,
 367     M_LWC3_A,
 368     M_LWC3_AB,
 369     M_LWL_A,
 370     M_LWL_AB,
 371     M_LWR_A,
 372     M_LWR_AB,
 373     M_LWU_AB,
 374     M_MUL,
 375     M_MUL_I,
 376     M_MULO,
 377     M_MULO_I,
 378     M_MULOU,
 379     M_MULOU_I,
 380     M_NOR_I,
 381     M_OR_I,
 382     M_REM_3,
 383     M_REM_3I,
 384     M_REMU_3,
 385     M_REMU_3I,
 386     M_ROL,
 387     M_ROL_I,
 388     M_ROR,
 389     M_ROR_I,
 390     M_S_DA,
 391     M_S_DOB,
 392     M_S_DAB,
 393     M_S_S,
 394     M_SC_AB,
 395     M_SCD_AB,
 396     M_SD_A,
 397     M_SD_OB,
 398     M_SD_AB,
 399     M_SDC1_AB,
 400     M_SDC2_AB,
 401     M_SDC3_AB,
 402     M_SDL_AB,
 403     M_SDR_AB,
 404     M_SEQ,
 405     M_SEQ_I,
 406     M_SGE,
 407     M_SGE_I,
 408     M_SGEU,
 409     M_SGEU_I,
 410     M_SGT,
 411     M_SGT_I,
 412     M_SGTU,
 413     M_SGTU_I,
 414     M_SLE,
 415     M_SLE_I,
 416     M_SLEU,
 417     M_SLEU_I,
 418     M_SLT_I,
 419     M_SLTU_I,
 420     M_SNE,
 421     M_SNE_I,
 422     M_SB_A,
 423     M_SB_AB,
 424     M_SH_A,
 425     M_SH_AB,
 426     M_SW_A,
 427     M_SW_AB,
 428     M_SWC0_A,
 429     M_SWC0_AB,
 430     M_SWC1_A,
 431     M_SWC1_AB,
 432     M_SWC2_A,
 433     M_SWC2_AB,
 434     M_SWC3_A,
 435     M_SWC3_AB,
 436     M_SWL_A,
 437     M_SWL_AB,
 438     M_SWR_A,
 439     M_SWR_AB,
 440     M_SUB_I,
 441     M_SUBU_I,
 442     M_TEQ_I,
 443     M_TGE_I,
 444     M_TGEU_I,
 445     M_TLT_I,
 446     M_TLTU_I,
 447     M_TNE_I,
 448     M_TRUNCWD,
 449     M_TRUNCWS,
 450     M_ULD,
 451     M_ULD_A,
 452     M_ULH,
 453     M_ULH_A,
 454     M_ULHU,
 455     M_ULHU_A,
 456     M_ULW,
 457     M_ULW_A,
 458     M_USH,
 459     M_USH_A,
 460     M_USW,
 461     M_USW_A,
 462     M_USD,
 463     M_USD_A,
 464     M_XOR_I
 465 };
 466
 467 /* The order of overloaded instructions matters.  Label arguments and
 468    register arguments look the same. Instructions that can have either
 469    for arguments must apear in the correct order in this table for the
 470    assembler to pick the right one. In other words, entries with
 471    immediate operands must apear after the same instruction with
 472    registers.
 473
 474    Many instructions are short hand for other instructions (i.e., The
 475    jal <register> instruction is short for jalr <register>).  */
 476
 477 extern const struct mips_opcode mips_opcodes[];
 478 extern const int bfd_mips_num_opcodes;
 479 #define NUMOPCODES bfd_mips_num_opcodes