include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef _MIPS_H_
  23 #define _MIPS_H_
  24
  25 /* These are bit masks and shift counts to use to access the various
  26    fields of an instruction.  To retrieve the X field of an
  27    instruction, use the expression
  28         (i >> OP_SH_X) & OP_MASK_X
  29    To set the same field (to j), use
  30         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  31
  32    Make sure you use fields that are appropriate for the instruction,
  33    of course.
  34
  35    The 'i' format uses OP, RS, RT and IMMEDIATE.
  36
  37    The 'j' format uses OP and TARGET.
  38
  39    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  40
  41    The 'b' format uses OP, RS, RT and DELTA.
  42
  43    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  44
  45    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  46
  47    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  48    breakpoint instruction are not defined; Kane says the breakpoint
  49    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  50    only use ten bits).  An optional two-operand form of break/sdbbp
  51    allows the lower ten bits to be set too.
  52
  53    The syscall instruction uses SYSCALL.
  54
  55    The general coprocessor instructions use COPZ.  */
  56
  57 #define OP_MASK_OP              0x3f
  58 #define OP_SH_OP                26
  59 #define OP_MASK_RS              0x1f
  60 #define OP_SH_RS                21
  61 #define OP_MASK_FR              0x1f
  62 #define OP_SH_FR                21
  63 #define OP_MASK_FMT             0x1f
  64 #define OP_SH_FMT               21
  65 #define OP_MASK_BCC             0x7
  66 #define OP_SH_BCC               18
  67 #define OP_MASK_CODE            0x3ff
  68 #define OP_SH_CODE              16
  69 #define OP_MASK_CODE2           0x3ff
  70 #define OP_SH_CODE2             6
  71 #define OP_MASK_RT              0x1f
  72 #define OP_SH_RT                16
  73 #define OP_MASK_FT              0x1f
  74 #define OP_SH_FT                16
  75 #define OP_MASK_CACHE           0x1f
  76 #define OP_SH_CACHE             16
  77 #define OP_MASK_RD              0x1f
  78 #define OP_SH_RD                11
  79 #define OP_MASK_FS              0x1f
  80 #define OP_SH_FS                11
  81 #define OP_MASK_PREFX           0x1f
  82 #define OP_SH_PREFX             11
  83 #define OP_MASK_CCC             0x7
  84 #define OP_SH_CCC               8
  85 #define OP_MASK_SYSCALL         0xfffff
  86 #define OP_SH_SYSCALL           6
  87 #define OP_MASK_SHAMT           0x1f
  88 #define OP_SH_SHAMT             6
  89 #define OP_MASK_FD              0x1f
  90 #define OP_SH_FD                6
  91 #define OP_MASK_TARGET          0x3ffffff
  92 #define OP_SH_TARGET            0
  93 #define OP_MASK_COPZ            0x1ffffff
  94 #define OP_SH_COPZ              0
  95 #define OP_MASK_IMMEDIATE       0xffff
  96 #define OP_SH_IMMEDIATE         0
  97 #define OP_MASK_DELTA           0xffff
  98 #define OP_SH_DELTA             0
  99 #define OP_MASK_FUNCT           0x3f
 100 #define OP_SH_FUNCT             0
 101 #define OP_MASK_SPEC            0x3f
 102 #define OP_SH_SPEC              0
 103 #define OP_SH_LOCC              8       /* FP condition code */
 104 #define OP_SH_HICC              18      /* FP condition code */
 105 #define OP_MASK_CC              0x7
 106 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding */
 107 #define OP_MASK_COP1NORM        0x1     /* a single bit */
 108 #define OP_SH_COP1SPEC          21      /* COP1 encodings */
 109 #define OP_MASK_COP1SPEC        0xf
 110 #define OP_MASK_COP1SCLR        0x4
 111 #define OP_MASK_COP1CMP         0x3
 112 #define OP_SH_COP1CMP           4
 113 #define OP_SH_FORMAT            21      /* FP short format field */
 114 #define OP_MASK_FORMAT          0x7
 115 #define OP_SH_TRUE              16
 116 #define OP_MASK_TRUE            0x1
 117 #define OP_SH_GE                17
 118 #define OP_MASK_GE              0x01
 119 #define OP_SH_UNSIGNED          16
 120 #define OP_MASK_UNSIGNED        0x1
 121 #define OP_SH_HINT              16
 122 #define OP_MASK_HINT            0x1f
 123 #define OP_SH_MMI               0       /* Multimedia (parallel) op */
 124 #define OP_MASK_MMI             0x3f
 125 #define OP_SH_MMISUB            6
 126 #define OP_MASK_MMISUB          0x1f
 127 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring */
 128 #define OP_SH_PERFREG           1
 129 /* start-sanitize-cygnus */
 130 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 131                                            but 0x8-0xf don't select bytes.  */
 132 #define OP_SH_VECBYTE           22
 133 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 134 #define OP_SH_VECALIGN          21
 135 /* end-sanitize-cygnus */
 136 /* start-sanitize-r5900 */
 137 #define OP_SH_VADDI             6
 138 #define OP_MASK_VADDI           0x1f
 139 #define OP_SH_VUTREG            16
 140 #define OP_MASK_VUTREG          0x1f
 141 #define OP_SH_VUSREG            11
 142 #define OP_MASK_VUSREG          0x1f
 143 #define OP_SH_VUDREG            6
 144 #define OP_MASK_VUDREG          0x1f
 145 #define OP_SH_VUFSF             21
 146 #define OP_MASK_VUFSF           0x3
 147 #define OP_SH_VUFTF             23
 148 #define OP_MASK_VUFTF           0x3
 149 #define OP_SH_VUDEST            21
 150 #define OP_MASK_VUDEST          0xf
 151 #define OP_SH_VUCALLMS          6
 152 #define OP_MASK_VUCALLMS        0x7fff
 153 /* end-sanitize-r5900 */
 154
 155 /* This structure holds information for a particular instruction.  */
 156
 157 struct mips_opcode
 158 {
 159   /* The name of the instruction.  */
 160   const char *name;
 161   /* A string describing the arguments for this instruction.  */
 162   const char *args;
 163   /* The basic opcode for the instruction.  When assembling, this
 164      opcode is modified by the arguments to produce the actual opcode
 165      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 166   unsigned long match;
 167   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 168      relevant portions of the opcode when disassembling.  If the
 169      actual opcode anded with the match field equals the opcode field,
 170      then we have found the correct instruction.  If pinfo is
 171      INSN_MACRO, then this field is the macro identifier.  */
 172   unsigned long mask;
 173   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 174      of bits describing the instruction, notably any relevant hazard
 175      information.  */
 176   unsigned long pinfo;
 177   /* A collection of bits describing the instruction sets of which this
 178      instruction or macro is a member. */
 179   unsigned long membership;
 180 };
 181
 182 /* These are the characters which may appears in the args field of an
 183    instruction.  They appear in the order in which the fields appear
 184    when the instruction is used.  Commas and parentheses in the args
 185    string are ignored when assembling, and written into the output
 186    when disassembling.
 187
 188    Each of these characters corresponds to a mask field defined above.
 189
 190    "<" 5 bit shift amount (OP_*_SHAMT)
 191    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 192    "a" 26 bit target address (OP_*_TARGET)
 193    "b" 5 bit base register (OP_*_RS)
 194    "c" 10 bit breakpoint code (OP_*_CODE)
 195    "d" 5 bit destination register specifier (OP_*_RD)
 196    "h" 5 bit prefx hint (OP_*_PREFX)
 197    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 198    "j" 16 bit signed immediate (OP_*_DELTA)
 199    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 200 start-sanitize-cygnus
 201              also vr5400 vector ops immediate operand
 202 end-sanitize-cygnus
 203    "o" 16 bit signed offset (OP_*_DELTA)
 204    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 205    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 206    "r" 5 bit same register used as both source and target (OP_*_RS)
 207    "s" 5 bit source register specifier (OP_*_RS)
 208    "t" 5 bit target register (OP_*_RT)
 209    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 210    "v" 5 bit same register used as both source and destination (OP_*_RS)
 211    "w" 5 bit same register used as both target and destination (OP_*_RT)
 212    "C" 25 bit coprocessor function code (OP_*_COPZ)
 213    "B" 20 bit syscall function code (OP_*_SYSCALL)
 214    "x" accept and ignore register name
 215    "z" must be zero register
 216
 217    Floating point instructions:
 218    "D" 5 bit destination register (OP_*_FD)
 219    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 220    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 221    "S" 5 bit fs source 1 register (OP_*_FS)
 222    "T" 5 bit ft source 2 register (OP_*_FT)
 223    "R" 5 bit fr source 3 register (OP_*_FR)
 224    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 225    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 226
 227    Coprocessor instructions:
 228    "E" 5 bit target register (OP_*_RT)
 229    "G" 5 bit destination register (OP_*_RD)
 230    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 231 start-sanitize-cygnus
 232    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 233    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 234    see also "k" above
 235 end-sanitize-cygnus
 236
 237    Macro instructions:
 238    "A" General 32 bit expression
 239    "I" 32 bit immediate
 240    "F" 64 bit floating point constant in .rdata
 241    "L" 64 bit floating point constant in .lit8
 242    "f" 32 bit floating point constant
 243    "l" 32 bit floating point constant in .lit4
 244
 245    Other:
 246    "()" parens surrounding optional value
 247    ","  separates operands
 248 start-sanitize-cygnus
 249    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 250 end-sanitize-cygnus
 251
 252    Characters used so far, for quick reference when adding more:
 253 start-sanitize-cygnus
 254    "Pe%[]" plus...
 255 end-sanitize-cygnus
 256    "<>(),"
 257    "ABCDEFGILMNSTRVW"
 258    "abcdfhijklopqrstuvwxz"
 259 */
 260
 261 /* These are the bits which may be set in the pinfo field of an
 262    instructions, if it is not equal to INSN_MACRO.  */
 263
 264 /* Modifies the general purpose register in OP_*_RD.  */
 265 #define INSN_WRITE_GPR_D            0x00000001
 266 /* Modifies the general purpose register in OP_*_RT.  */
 267 #define INSN_WRITE_GPR_T            0x00000002
 268 /* Modifies general purpose register 31.  */
 269 #define INSN_WRITE_GPR_31           0x00000004
 270 /* Modifies the floating point register in OP_*_FD.  */
 271 #define INSN_WRITE_FPR_D            0x00000008
 272 /* Modifies the floating point register in OP_*_FS.  */
 273 #define INSN_WRITE_FPR_S            0x00000010
 274 /* Modifies the floating point register in OP_*_FT.  */
 275 #define INSN_WRITE_FPR_T            0x00000020
 276 /* Reads the general purpose register in OP_*_RS.  */
 277 #define INSN_READ_GPR_S             0x00000040
 278 /* Reads the general purpose register in OP_*_RT.  */
 279 #define INSN_READ_GPR_T             0x00000080
 280 /* Reads the floating point register in OP_*_FS.  */
 281 #define INSN_READ_FPR_S             0x00000100
 282 /* Reads the floating point register in OP_*_FT.  */
 283 #define INSN_READ_FPR_T             0x00000200
 284 /* Reads the floating point register in OP_*_FR.  */
 285 #define INSN_READ_FPR_R             0x00000400
 286 /* Modifies coprocessor condition code.  */
 287 #define INSN_WRITE_COND_CODE        0x00000800
 288 /* Reads coprocessor condition code.  */
 289 #define INSN_READ_COND_CODE         0x00001000
 290 /* TLB operation.  */
 291 #define INSN_TLB                    0x00002000
 292 /* Reads coprocessor register other than floating point register.  */
 293 #define INSN_COP                    0x00004000
 294 /* Instruction loads value from memory, requiring delay.  */
 295 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 296 /* Instruction loads value from coprocessor, requiring delay.  */
 297 #define INSN_LOAD_COPROC_DELAY      0x00010000
 298 /* Instruction has unconditional branch delay slot.  */
 299 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 300 /* Instruction has conditional branch delay slot.  */
 301 #define INSN_COND_BRANCH_DELAY      0x00040000
 302 /* Conditional branch likely: if branch not taken, insn nullified.  */
 303 #define INSN_COND_BRANCH_LIKELY     0x00080000
 304 /* Moves to coprocessor register, requiring delay.  */
 305 #define INSN_COPROC_MOVE_DELAY      0x00100000
 306 /* Loads coprocessor register from memory, requiring delay.  */
 307 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 308 /* Reads the HI register.  */
 309 #define INSN_READ_HI                0x00400000
 310 /* Reads the LO register.  */
 311 #define INSN_READ_LO                0x00800000
 312 /* Modifies the HI register.  */
 313 #define INSN_WRITE_HI               0x01000000
 314 /* Modifies the LO register.  */
 315 #define INSN_WRITE_LO               0x02000000
 316 /* Takes a trap (easier to keep out of delay slot).  */
 317 #define INSN_TRAP                   0x04000000
 318 /* Instruction stores value into memory.  */
 319 #define INSN_STORE_MEMORY           0x08000000
 320 /* Instruction uses single precision floating point.  */
 321 #define FP_S                        0x10000000
 322 /* Instruction uses double precision floating point.  */
 323 #define FP_D                        0x20000000
 324 /* Instruction is part of the tx39's integer multiply family.    */
 325 #define INSN_MULT                   0x40000000
 326
 327 /* Instruction is actually a macro.  It should be ignored by the
 328    disassembler, and requires special treatment by the assembler.  */
 329 #define INSN_MACRO                  0xffffffff
 330
 331
 332
 333
 334
 335 /* MIPS ISA field--CPU level at which insn is supported.  */
 336 #define INSN_ISA                    0x0000000F
 337 /* An instruction which is not part of any basic MIPS ISA.
 338    (ie it is a chip specific instruction)  */
 339 #define INSN_NO_ISA                 0x00000000
 340 /* MIPS ISA 1 instruction.  */
 341 #define INSN_ISA1                   0x00000001
 342 /* MIPS ISA 2 instruction (R6000 or R4000).  */
 343 #define INSN_ISA2                   0x00000002
 344 /* MIPS ISA 3 instruction (R4000).  */
 345 #define INSN_ISA3                   0x00000003
 346 /* MIPS ISA 4 instruction (R8000).  */
 347 #define INSN_ISA4                   0x00000004
 348
 349 /* Chip specific instructions.  These are bitmasks.  */
 350 /* MIPS R4650 instruction.  */
 351 #define INSN_4650                   0x00000010
 352 /* LSI R4010 instruction.  */
 353 #define INSN_4010                   0x00000020
 354 /* NEC VR4100 instruction. */
 355 #define INSN_4100                   0x00000040
 356 /* Toshiba R3900 instruction.  */
 357 #define INSN_3900                   0x00000080
 358 /* start-sanitize-vr4320 */
 359 /* NEC VR4320 instruction.  */
 360 #define INSN_4320                   0x00002000
 361 /* end-sanitize-vr4320 */
 362 /* start-sanitize-cygnus */
 363 /* NEC VR5400 instruction.  */
 364 #define INSN_5400                   0x00001000
 365 /* end-sanitize-cygnus */
 366 /* start-sanitize-r5900 */
 367 /* Toshiba R5900 instruction */
 368 #define INSN_5900                   0x00000100
 369 /* end-sanitize-r5900 */
 370 /* start-sanitize-tx49 */
 371 #define INSN_4900                   0x00000200
 372 /* end-sanitize-tx49 */
 373
 374
 375 /* This is a list of macro expanded instructions.
 376  *
 377  * _I appended means immediate
 378  * _A appended means address
 379  * _AB appended means address with base register
 380  * _D appended means 64 bit floating point constant
 381  * _S appended means 32 bit floating point constant
 382  */
 383 enum {
 384     M_ABS,
 385     M_ADD_I,
 386     M_ADDU_I,
 387     M_AND_I,
 388     M_BEQ,
 389     M_BEQ_I,
 390     M_BEQL_I,
 391     M_BGE,
 392     M_BGEL,
 393     M_BGE_I,
 394     M_BGEL_I,
 395     M_BGEU,
 396     M_BGEUL,
 397     M_BGEU_I,
 398     M_BGEUL_I,
 399     M_BGT,
 400     M_BGTL,
 401     M_BGT_I,
 402     M_BGTL_I,
 403     M_BGTU,
 404     M_BGTUL,
 405     M_BGTU_I,
 406     M_BGTUL_I,
 407     M_BLE,
 408     M_BLEL,
 409     M_BLE_I,
 410     M_BLEL_I,
 411     M_BLEU,
 412     M_BLEUL,
 413     M_BLEU_I,
 414     M_BLEUL_I,
 415     M_BLT,
 416     M_BLTL,
 417     M_BLT_I,
 418     M_BLTL_I,
 419     M_BLTU,
 420     M_BLTUL,
 421     M_BLTU_I,
 422     M_BLTUL_I,
 423     M_BNE,
 424     M_BNE_I,
 425     M_BNEL_I,
 426     M_DABS,
 427     M_DADD_I,
 428     M_DADDU_I,
 429     M_DDIV_3,
 430     M_DDIV_3I,
 431     M_DDIVU_3,
 432     M_DDIVU_3I,
 433     M_DIV_3,
 434     M_DIV_3I,
 435     M_DIVU_3,
 436     M_DIVU_3I,
 437     M_DLA_AB,
 438     M_DLI,
 439     M_DMUL,
 440     M_DMUL_I,
 441     M_DMULO,
 442     M_DMULO_I,
 443     M_DMULOU,
 444     M_DMULOU_I,
 445     M_DREM_3,
 446     M_DREM_3I,
 447     M_DREMU_3,
 448     M_DREMU_3I,
 449     M_DSUB_I,
 450     M_DSUBU_I,
 451     M_DSUBU_I_2,
 452     M_J_A,
 453     M_JAL_1,
 454     M_JAL_2,
 455     M_JAL_A,
 456     M_L_DOB,
 457     M_L_DAB,
 458     M_LA_AB,
 459     M_LB_A,
 460     M_LB_AB,
 461     M_LBU_A,
 462     M_LBU_AB,
 463     M_LD_A,
 464     M_LD_OB,
 465     M_LD_AB,
 466     M_LDC1_AB,
 467     M_LDC2_AB,
 468     M_LDC3_AB,
 469     M_LDL_AB,
 470     M_LDR_AB,
 471     M_LH_A,
 472     M_LH_AB,
 473     M_LHU_A,
 474     M_LHU_AB,
 475     M_LI,
 476     M_LI_D,
 477     M_LI_DD,
 478     M_LI_S,
 479     M_LI_SS,
 480     M_LL_AB,
 481     M_LLD_AB,
 482     M_LS_A,
 483     M_LW_A,
 484     M_LW_AB,
 485     M_LWC0_A,
 486     M_LWC0_AB,
 487     M_LWC1_A,
 488     M_LWC1_AB,
 489     M_LWC2_A,
 490     M_LWC2_AB,
 491     M_LWC3_A,
 492     M_LWC3_AB,
 493     M_LWL_A,
 494     M_LWL_AB,
 495     M_LWR_A,
 496     M_LWR_AB,
 497     M_LWU_AB,
 498     M_MUL,
 499     M_MUL_I,
 500     M_MULO,
 501     M_MULO_I,
 502     M_MULOU,
 503     M_MULOU_I,
 504     M_NOR_I,
 505     M_OR_I,
 506     M_REM_3,
 507     M_REM_3I,
 508     M_REMU_3,
 509     M_REMU_3I,
 510     M_ROL,
 511     M_ROL_I,
 512     M_ROR,
 513     M_ROR_I,
 514     M_S_DA,
 515     M_S_DOB,
 516     M_S_DAB,
 517     M_S_S,
 518     M_SC_AB,
 519     M_SCD_AB,
 520     M_SD_A,
 521     M_SD_OB,
 522     M_SD_AB,
 523     M_SDC1_AB,
 524     M_SDC2_AB,
 525     M_SDC3_AB,
 526     M_SDL_AB,
 527     M_SDR_AB,
 528     M_SEQ,
 529     M_SEQ_I,
 530     M_SGE,
 531     M_SGE_I,
 532     M_SGEU,
 533     M_SGEU_I,
 534     M_SGT,
 535     M_SGT_I,
 536     M_SGTU,
 537     M_SGTU_I,
 538     M_SLE,
 539     M_SLE_I,
 540     M_SLEU,
 541     M_SLEU_I,
 542     M_SLT_I,
 543     M_SLTU_I,
 544     M_SNE,
 545     M_SNE_I,
 546     M_SB_A,
 547     M_SB_AB,
 548     M_SH_A,
 549     M_SH_AB,
 550     M_SW_A,
 551     M_SW_AB,
 552     M_SWC0_A,
 553     M_SWC0_AB,
 554     M_SWC1_A,
 555     M_SWC1_AB,
 556     M_SWC2_A,
 557     M_SWC2_AB,
 558     M_SWC3_A,
 559     M_SWC3_AB,
 560     M_SWL_A,
 561     M_SWL_AB,
 562     M_SWR_A,
 563     M_SWR_AB,
 564     M_SUB_I,
 565     M_SUBU_I,
 566     M_SUBU_I_2,
 567     M_TEQ_I,
 568     M_TGE_I,
 569     M_TGEU_I,
 570     M_TLT_I,
 571     M_TLTU_I,
 572     M_TNE_I,
 573     M_TRUNCWD,
 574     M_TRUNCWS,
 575     M_ULD,
 576     M_ULD_A,
 577     M_ULH,
 578     M_ULH_A,
 579     M_ULHU,
 580     M_ULHU_A,
 581     M_ULW,
 582     M_ULW_A,
 583     M_USH,
 584     M_USH_A,
 585     M_USW,
 586     M_USW_A,
 587     M_USD,
 588     M_USD_A,
 589     M_XOR_I,
 590     M_COP0,
 591     M_COP1,
 592     M_COP2,
 593     M_COP3,
 594     M_NUM_MACROS
 595 };
 596
 597
 598 /* The order of overloaded instructions matters.  Label arguments and
 599    register arguments look the same. Instructions that can have either
 600    for arguments must apear in the correct order in this table for the
 601    assembler to pick the right one. In other words, entries with
 602    immediate operands must apear after the same instruction with
 603    registers.
 604
 605    Many instructions are short hand for other instructions (i.e., The
 606    jal <register> instruction is short for jalr <register>).  */
 607
 608 extern const struct mips_opcode mips_builtin_opcodes[];
 609 extern const int bfd_mips_num_builtin_opcodes;
 610 extern struct mips_opcode *mips_opcodes;
 611 extern int bfd_mips_num_opcodes;
 612 #define NUMOPCODES bfd_mips_num_opcodes
 613
 614 \f
 615 /* The rest of this file adds definitions for the mips16 TinyRISC
 616    processor.  */
 617
 618 /* These are the bitmasks and shift counts used for the different
 619    fields in the instruction formats.  Other than OP, no masks are
 620    provided for the fixed portions of an instruction, since they are
 621    not needed.
 622
 623    The I format uses IMM11.
 624
 625    The RI format uses RX and IMM8.
 626
 627    The RR format uses RX, and RY.
 628
 629    The RRI format uses RX, RY, and IMM5.
 630
 631    The RRR format uses RX, RY, and RZ.
 632
 633    The RRI_A format uses RX, RY, and IMM4.
 634
 635    The SHIFT format uses RX, RY, and SHAMT.
 636
 637    The I8 format uses IMM8.
 638
 639    The I8_MOVR32 format uses RY and REGR32.
 640
 641    The IR_MOV32R format uses REG32R and MOV32Z.
 642
 643    The I64 format uses IMM8.
 644
 645    The RI64 format uses RY and IMM5.
 646    */
 647
 648 #define MIPS16OP_MASK_OP        0x1f
 649 #define MIPS16OP_SH_OP          11
 650 #define MIPS16OP_MASK_IMM11     0x7ff
 651 #define MIPS16OP_SH_IMM11       0
 652 #define MIPS16OP_MASK_RX        0x7
 653 #define MIPS16OP_SH_RX          8
 654 #define MIPS16OP_MASK_IMM8      0xff
 655 #define MIPS16OP_SH_IMM8        0
 656 #define MIPS16OP_MASK_RY        0x7
 657 #define MIPS16OP_SH_RY          5
 658 #define MIPS16OP_MASK_IMM5      0x1f
 659 #define MIPS16OP_SH_IMM5        0
 660 #define MIPS16OP_MASK_RZ        0x7
 661 #define MIPS16OP_SH_RZ          2
 662 #define MIPS16OP_MASK_IMM4      0xf
 663 #define MIPS16OP_SH_IMM4        0
 664 #define MIPS16OP_MASK_REGR32    0x1f
 665 #define MIPS16OP_SH_REGR32      0
 666 #define MIPS16OP_MASK_REG32R    0x1f
 667 #define MIPS16OP_SH_REG32R      3
 668 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 669 #define MIPS16OP_MASK_MOVE32Z   0x7
 670 #define MIPS16OP_SH_MOVE32Z     0
 671 #define MIPS16OP_MASK_IMM6      0x3f
 672 #define MIPS16OP_SH_IMM6        5
 673
 674 /* These are the characters which may appears in the args field of an
 675    instruction.  They appear in the order in which the fields appear
 676    when the instruction is used.  Commas and parentheses in the args
 677    string are ignored when assembling, and written into the output
 678    when disassembling.
 679
 680    "y" 3 bit register (MIPS16OP_*_RY)
 681    "x" 3 bit register (MIPS16OP_*_RX)
 682    "z" 3 bit register (MIPS16OP_*_RZ)
 683    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 684    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 685    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 686    "0" zero register ($0)
 687    "S" stack pointer ($sp or $29)
 688    "P" program counter
 689    "R" return address register ($ra or $31)
 690    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 691    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 692    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 693    "a" 26 bit jump address
 694    "e" 11 bit extension value
 695    "l" register list for entry instruction
 696    "L" register list for exit instruction
 697
 698    The remaining codes may be extended.  Except as otherwise noted,
 699    the full extended operand is a 16 bit signed value.
 700    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 701    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 702    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 703    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 704    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 705    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 706    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 707    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 708    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 709    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 710    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 711    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 712    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 713    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 714    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 715    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 716    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 717    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 718    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 719    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
 720    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
 721    */
 722
 723 /* For the mips16, we use the same opcode table format and a few of
 724    the same flags.  However, most of the flags are different.  */
 725
 726 /* Modifies the register in MIPS16OP_*_RX.  */
 727 #define MIPS16_INSN_WRITE_X                 0x00000001
 728 /* Modifies the register in MIPS16OP_*_RY.  */
 729 #define MIPS16_INSN_WRITE_Y                 0x00000002
 730 /* Modifies the register in MIPS16OP_*_RZ.  */
 731 #define MIPS16_INSN_WRITE_Z                 0x00000004
 732 /* Modifies the T ($24) register.  */
 733 #define MIPS16_INSN_WRITE_T                 0x00000008
 734 /* Modifies the SP ($29) register.  */
 735 #define MIPS16_INSN_WRITE_SP                0x00000010
 736 /* Modifies the RA ($31) register.  */
 737 #define MIPS16_INSN_WRITE_31                0x00000020
 738 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
 739 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
 740 /* Reads the register in MIPS16OP_*_RX.  */
 741 #define MIPS16_INSN_READ_X                  0x00000080
 742 /* Reads the register in MIPS16OP_*_RY.  */
 743 #define MIPS16_INSN_READ_Y                  0x00000100
 744 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
 745 #define MIPS16_INSN_READ_Z                  0x00000200
 746 /* Reads the T ($24) register.  */
 747 #define MIPS16_INSN_READ_T                  0x00000400
 748 /* Reads the SP ($29) register.  */
 749 #define MIPS16_INSN_READ_SP                 0x00000800
 750 /* Reads the RA ($31) register.  */
 751 #define MIPS16_INSN_READ_31                 0x00001000
 752 /* Reads the program counter.  */
 753 #define MIPS16_INSN_READ_PC                 0x00002000
 754 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 755 #define MIPS16_INSN_READ_GPR_X              0x00004000
 756
 757 /* The following flags have the same value for the mips16 opcode
 758    table:
 759    INSN_UNCOND_BRANCH_DELAY
 760    INSN_COND_BRANCH_DELAY
 761    INSN_COND_BRANCH_LIKELY (never used)
 762    INSN_READ_HI
 763    INSN_READ_LO
 764    INSN_WRITE_HI
 765    INSN_WRITE_LO
 766    INSN_TRAP
 767    INSN_ISA3
 768    */
 769
 770 extern const struct mips_opcode mips16_opcodes[];
 771 extern const int bfd_mips16_num_opcodes;
 772
 773 #endif /* _MIPS_H_ */