include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  21
  22 /* These are bit masks and shift counts to use to access the various
  23    fields of an instruction.  To retrieve the X field of an
  24    instruction, use the expression
  25         (i >> OP_SH_X) & OP_MASK_X
  26    To set the same field (to j), use
  27         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  28
  29    Make sure you use fields that are appropriate for the instruction,
  30    of course.
  31
  32    The 'i' format uses OP, RS, RT and IMMEDIATE.
  33
  34    The 'j' format uses OP and TARGET.
  35
  36    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  37
  38    The 'b' format uses OP, RS, RT and DELTA.
  39
  40    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  41
  42    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  43
  44    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  45    breakpoint instruction are not defined; Kane says the breakpoint
  46    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  47    only use ten bits).
  48
  49    The syscall instruction uses SYSCALL.
  50
  51    The general coprocessor instructions use COPZ.  */
  52
  53 #define OP_MASK_OP              0x3f
  54 #define OP_SH_OP                26
  55 #define OP_MASK_RS              0x1f
  56 #define OP_SH_RS                21
  57 #define OP_MASK_FMT             0x1f
  58 #define OP_SH_FMT               21
  59 #define OP_MASK_CODE            0x3ff
  60 #define OP_SH_CODE              16
  61 #define OP_MASK_RT              0x1f
  62 #define OP_SH_RT                16
  63 #define OP_MASK_FT              0x1f
  64 #define OP_SH_FT                16
  65 #define OP_MASK_RD              0x1f
  66 #define OP_SH_RD                11
  67 #define OP_MASK_FS              0x1f
  68 #define OP_SH_FS                11
  69 #define OP_MASK_SYSCALL         0xfffff
  70 #define OP_SH_SYSCALL           6
  71 #define OP_MASK_SHAMT           0x1f
  72 #define OP_SH_SHAMT             6
  73 #define OP_MASK_FD              0x1f
  74 #define OP_SH_FD                6
  75 #define OP_MASK_TARGET          0x3ffffff
  76 #define OP_SH_TARGET            0
  77 #define OP_MASK_COPZ            0x1ffffff
  78 #define OP_SH_COPZ              0
  79 #define OP_MASK_IMMEDIATE       0xffff
  80 #define OP_SH_IMMEDIATE         0
  81 #define OP_MASK_DELTA           0xffff
  82 #define OP_SH_DELTA             0
  83 #define OP_MASK_FUNCT           0x3f
  84 #define OP_SH_FUNCT             0
  85 #define OP_MASK_SPEC            0x3f
  86 #define OP_SH_SPEC              0
  87
  88 /* This structure holds information for a particular instruction.  */
  89
  90 struct mips_opcode
  91 {
  92   /* The name of the instruction.  */
  93   const char *name;
  94   /* A string describing the arguments for this instruction.  */
  95   const char *args;
  96   /* The basic opcode for the instruction.  When assembling, this
  97      opcode is modified by the arguments to produce the actual opcode
  98      that is used.  If pinfo is INSN_MACRO, then this is instead the
  99      ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
 100      etc.).  */
 101   unsigned long match;
 102   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 103      relevant portions of the opcode when disassembling.  If the
 104      actual opcode anded with the match field equals the opcode field,
 105      then we have found the correct instruction.  If pinfo is
 106      INSN_MACRO, then this field is the macro identifier.  */
 107   unsigned long mask;
 108   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 109      of bits describing the instruction, notably any relevant hazard
 110      information.  */
 111   unsigned long pinfo;
 112 };
 113
 114 /* These are the characters which may appears in the args field of an
 115    instruction.  They appear in the order in which the fields appear
 116    when the instruction is used.  Commas and parentheses in the args
 117    string are ignored when assembling, and written into the output
 118    when disassembling.
 119
 120    Each of these characters corresponds to a mask field defined above.
 121
 122    "<" 5 bit shift amount (OP_*_SHAMT)
 123    "a" 26 bit target address (OP_*_TARGET)
 124    "b" 5 bit base register (OP_*_RS)
 125    "c" 10 bit breakpoint code (OP_*_CODE)
 126    "d" 5 bit destination register specifier (OP_*_RD)
 127    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 128    "j" 16 bit signed immediate (OP_*_DELTA)
 129    "o" 16 bit signed offset (OP_*_DELTA)
 130    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 131    "r" 5 bit same register used as both source and target (OP_*_RS)
 132    "s" 5 bit source register specifier (OP_*_RS)
 133    "t" 5 bit target register (OP_*_RT)
 134    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 135    "v" 5 bit same register used as both source and destination (OP_*_RS)
 136    "w" 5 bit same register used as both target and destination (OP_*_RT)
 137    "C" 25 bit coprocessor function code (OP_*_COPZ)
 138    "B" 20 bit syscall function code (OP_*_SYSCALL)
 139    "x" accept and ignore register name
 140
 141    Floating point instructions:
 142    "D" 5 bit destination register (OP_*_FD)
 143    "S" 5 bit fs source 1 register (OP_*_FS)
 144    "T" 5 bit ft source 2 register (OP_*_FT)
 145    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 146    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 147
 148    Coprocessor instructions:
 149    "E" 5 bit target register (OP_*_RT)
 150    "G" 5 bit destination register (OP_*_RD)
 151
 152    Macro instructions:
 153    "A" General 32 bit expression
 154    "I" 32 bit immediate
 155    "F" 64 bit floating point constant in .rdata
 156    "L" 64 bit floating point constant in .lit8
 157    "f" 32 bit floating point constant
 158    "l" 32 bit floating point constant in .lit4
 159 */
 160
 161 /* These are the bits which may be set in the pinfo field of an
 162    instructions, if it is not equal to INSN_MACRO.  */
 163
 164 /* Modifies the general purpose register in OP_*_RD.  */
 165 #define INSN_WRITE_GPR_D            0x00000001
 166 /* Modifies the general purpose register in OP_*_RT.  */
 167 #define INSN_WRITE_GPR_T            0x00000002
 168 /* Modifies general purpose register 31.  */
 169 #define INSN_WRITE_GPR_31           0x00000004
 170 /* Modifies the floating point register in OP_*_FD.  */
 171 #define INSN_WRITE_FPR_D            0x00000008
 172 /* Modifies the floating point register in OP_*_FS.  */
 173 #define INSN_WRITE_FPR_S            0x00000010
 174 /* Modifies the floating point register in OP_*_FT.  */
 175 #define INSN_WRITE_FPR_T            0x00000020
 176 /* Reads the general purpose register in OP_*_RS.  */
 177 #define INSN_READ_GPR_S             0x00000040
 178 /* Reads the general purpose register in OP_*_RT.  */
 179 #define INSN_READ_GPR_T             0x00000080
 180 /* Reads the floating point register in OP_*_FS.  */
 181 #define INSN_READ_FPR_S             0x00000100
 182 /* Reads the floating point register in OP_*_FT.  */
 183 #define INSN_READ_FPR_T             0x00000200
 184 /* Modifies coprocessor condition code.  */
 185 #define INSN_WRITE_COND_CODE        0x00000400
 186 /* Reads coprocessor condition code.  */
 187 #define INSN_READ_COND_CODE         0x00000800
 188 /* TLB operation.  */
 189 #define INSN_TLB                    0x00001000
 190 /* RFE (return from exception) instruction.  */
 191 #define INSN_RFE                    0x00002000
 192 /* Reads coprocessor register other than floating point register.  */
 193 #define INSN_COP                    0x00004000
 194 /* Instruction loads value from memory, requiring delay.  */
 195 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 196 /* Instruction loads value from coprocessor, requiring delay.  */
 197 #define INSN_LOAD_COPROC_DELAY      0x00010000
 198 /* Instruction has unconditional branch delay slot.  */
 199 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 200 /* Instruction has conditional branch delay slot.  */
 201 #define INSN_COND_BRANCH_DELAY      0x00040000
 202 /* Conditional branch likely: if branch not taken, insn nullified.  */
 203 #define INSN_COND_BRANCH_LIKELY     0x00080000
 204 /* Moves to coprocessor register, requiring delay.  */
 205 #define INSN_COPROC_MOVE_DELAY      0x00100000
 206 /* Loads coprocessor register from memory, requiring delay.  */
 207 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 208 /* Reads the HI register.  */
 209 #define INSN_READ_HI                0x00400000
 210 /* Reads the LO register.  */
 211 #define INSN_READ_LO                0x00800000
 212 /* Modifies the HI register.  */
 213 #define INSN_WRITE_HI               0x01000000
 214 /* Modifies the LO register.  */
 215 #define INSN_WRITE_LO               0x02000000
 216 /* Takes a trap (FIXME: why is this interesting?).  */
 217 #define INSN_TRAP                   0x04000000
 218 /* MIPS ISA 2 instruction (R6000 or R4000).  */
 219 #define INSN_ISA2                   0x10000000
 220 /* MIPS ISA 3 instruction (R4000).  */
 221 #define INSN_ISA3                   0x20000000
 222
 223 /* Instruction is actually a macro.  It should be ignored by the
 224    disassembler, and requires special treatment by the assembler.  */
 225 #define INSN_MACRO                  0xffffffff
 226
 227 /* This is a list of macro expanded instructions.
 228  *
 229  * _I appended means immediate
 230  * _A appended means address
 231  * _AB appended means address with base register
 232  * _D appended means 64 bit floating point constant
 233  * _S appended means 32 bit floating point constant
 234  */
 235 enum {
 236     M_ABS,
 237     M_ABSU,
 238     M_ADD_I,
 239     M_ADDU_I,
 240     M_AND_I,
 241     M_BEQ_I,
 242     M_BEQL_I,
 243     M_BGE,
 244     M_BGEL,
 245     M_BGE_I,
 246     M_BGEL_I,
 247     M_BGEU,
 248     M_BGEUL,
 249     M_BGEU_I,
 250     M_BGEUL_I,
 251     M_BGT,
 252     M_BGTL,
 253     M_BGT_I,
 254     M_BGTL_I,
 255     M_BGTU,
 256     M_BGTUL,
 257     M_BGTU_I,
 258     M_BGTUL_I,
 259     M_BLE,
 260     M_BLEL,
 261     M_BLE_I,
 262     M_BLEL_I,
 263     M_BLEU,
 264     M_BLEUL,
 265     M_BLEU_I,
 266     M_BLEUL_I,
 267     M_BLT,
 268     M_BLTL,
 269     M_BLT_I,
 270     M_BLTL_I,
 271     M_BLTU,
 272     M_BLTUL,
 273     M_BLTU_I,
 274     M_BLTUL_I,
 275     M_BNE_I,
 276     M_BNEL_I,
 277     M_DADD_I,
 278     M_DADDU_I,
 279     M_DDIV_3,
 280     M_DDIV_3I,
 281     M_DDIVU_3,
 282     M_DDIVU_3I,
 283     M_DIV_3,
 284     M_DIV_3I,
 285     M_DIVU_3,
 286     M_DIVU_3I,
 287     M_DMUL,
 288     M_DMUL_I,
 289     M_DMULO,
 290     M_DMULO_I,
 291     M_DMULOU,
 292     M_DMULOU_I,
 293     M_DREM_3,
 294     M_DREM_3I,
 295     M_DREMU_3,
 296     M_DREMU_3I,
 297     M_DSUB_I,
 298     M_DSUBU_I,
 299     M_L_DOB,
 300     M_L_DAB,
 301     M_LA,
 302     M_LA_AB,
 303     M_LB_A,
 304     M_LB_AB,
 305     M_LBU_A,
 306     M_LBU_AB,
 307     M_LD_A,
 308     M_LD_OB,
 309     M_LD_AB,
 310     M_LDC1_AB,
 311     M_LDC2_AB,
 312     M_LDC3_AB,
 313     M_LDL_AB,
 314     M_LDR_AB,
 315     M_LH_A,
 316     M_LH_AB,
 317     M_LHU_A,
 318     M_LHU_AB,
 319     M_LI,
 320     M_LI_D,
 321     M_LI_DD,
 322     M_LI_S,
 323     M_LI_SS,
 324     M_LL_AB,
 325     M_LLD_AB,
 326     M_LS_A,
 327     M_LW_A,
 328     M_LW_AB,
 329     M_LWC0_A,
 330     M_LWC0_AB,
 331     M_LWC1_A,
 332     M_LWC1_AB,
 333     M_LWC2_A,
 334     M_LWC2_AB,
 335     M_LWC3_A,
 336     M_LWC3_AB,
 337     M_LWL_A,
 338     M_LWL_AB,
 339     M_LWR_A,
 340     M_LWR_AB,
 341     M_LWU_AB,
 342     M_MUL,
 343     M_MUL_I,
 344     M_MULO,
 345     M_MULO_I,
 346     M_MULOU,
 347     M_MULOU_I,
 348     M_NOR_I,
 349     M_OR_I,
 350     M_REM_3,
 351     M_REM_3I,
 352     M_REMU_3,
 353     M_REMU_3I,
 354     M_ROL,
 355     M_ROL_I,
 356     M_ROR,
 357     M_ROR_I,
 358     M_S_DA,
 359     M_S_DOB,
 360     M_S_DAB,
 361     M_S_S,
 362     M_SC_AB,
 363     M_SCD_AB,
 364     M_SD_A,
 365     M_SD_OB,
 366     M_SD_AB,
 367     M_SDC1_AB,
 368     M_SDC2_AB,
 369     M_SDC3_AB,
 370     M_SDL_AB,
 371     M_SDR_AB,
 372     M_SEQ,
 373     M_SEQ_I,
 374     M_SGE,
 375     M_SGE_I,
 376     M_SGEU,
 377     M_SGEU_I,
 378     M_SGT,
 379     M_SGT_I,
 380     M_SGTU,
 381     M_SGTU_I,
 382     M_SLE,
 383     M_SLE_I,
 384     M_SLEU,
 385     M_SLEU_I,
 386     M_SLT_I,
 387     M_SLTU_I,
 388     M_SNE,
 389     M_SNE_I,
 390     M_SB_A,
 391     M_SB_AB,
 392     M_SH_A,
 393     M_SH_AB,
 394     M_SW_A,
 395     M_SW_AB,
 396     M_SWC0_A,
 397     M_SWC0_AB,
 398     M_SWC1_A,
 399     M_SWC1_AB,
 400     M_SWC2_A,
 401     M_SWC2_AB,
 402     M_SWC3_A,
 403     M_SWC3_AB,
 404     M_SWL_A,
 405     M_SWL_AB,
 406     M_SWR_A,
 407     M_SWR_AB,
 408     M_SUB_I,
 409     M_SUBU_I,
 410     M_TEQ_I,
 411     M_TGE_I,
 412     M_TGEU_I,
 413     M_TLT_I,
 414     M_TLTU_I,
 415     M_TNE_I,
 416     M_TRUNCWD,
 417     M_TRUNCWS,
 418     M_ULH,
 419     M_ULH_A,
 420     M_ULHU,
 421     M_ULHU_A,
 422     M_ULW,
 423     M_ULW_A,
 424     M_USH,
 425     M_USH_A,
 426     M_USW,
 427     M_USW_A,
 428     M_XOR_I
 429 };
 430
 431 /* The order of overloaded instructions matters.  Label arguments and
 432    register arguments look the same. Instructions that can have either
 433    for arguments must apear in the correct order in this table for the
 434    assembler to pick the right one. In other words, entries with
 435    immediate operands must apear after the same instruction with
 436    registers.
 437
 438    Many instructions are short hand for other instructions (i.e., The
 439    jal <register> instruction is short for jalr <register>).  */
 440
 441 extern const struct mips_opcode mips_opcodes[];
 442 extern const int bfd_mips_num_opcodes;
 443 #define NUMOPCODES bfd_mips_num_opcodes