include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   3    2003, 2004, 2005, 2008, 2009, 2010, 2013
   4    Free Software Foundation, Inc.
   5    Contributed by Ralph Campbell and OSF
   6    Commented and modified by Ian Lance Taylor, Cygnus Support
   7
   8    This file is part of GDB, GAS, and the GNU binutils.
   9
  10    GDB, GAS, and the GNU binutils are free software; you can redistribute
  11    them and/or modify them under the terms of the GNU General Public
  12    License as published by the Free Software Foundation; either version 3,
  13    or (at your option) any later version.
  14
  15    GDB, GAS, and the GNU binutils are distributed in the hope that they
  16    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  17    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  18    the GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this file; see the file COPYING3.  If not, write to the Free
  22    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  23    MA 02110-1301, USA.  */
  24
  25 #ifndef _MIPS_H_
  26 #define _MIPS_H_
  27
  28 #include "bfd.h"
  29
  30 /* These are bit masks and shift counts to use to access the various
  31    fields of an instruction.  To retrieve the X field of an
  32    instruction, use the expression
  33         (i >> OP_SH_X) & OP_MASK_X
  34    To set the same field (to j), use
  35         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  36
  37    Make sure you use fields that are appropriate for the instruction,
  38    of course.
  39
  40    The 'i' format uses OP, RS, RT and IMMEDIATE.
  41
  42    The 'j' format uses OP and TARGET.
  43
  44    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  45
  46    The 'b' format uses OP, RS, RT and DELTA.
  47
  48    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  49
  50    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  51
  52    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  53    breakpoint instruction are not defined; Kane says the breakpoint
  54    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  55    only use ten bits).  An optional two-operand form of break/sdbbp
  56    allows the lower ten bits to be set too, and MIPS32 and later
  57    architectures allow 20 bits to be set with a signal operand
  58    (using CODE20).
  59
  60    The syscall instruction uses CODE20.
  61
  62    The general coprocessor instructions use COPZ.  */
  63
  64 #define OP_MASK_OP              0x3f
  65 #define OP_SH_OP                26
  66 #define OP_MASK_RS              0x1f
  67 #define OP_SH_RS                21
  68 #define OP_MASK_FR              0x1f
  69 #define OP_SH_FR                21
  70 #define OP_MASK_FMT             0x1f
  71 #define OP_SH_FMT               21
  72 #define OP_MASK_BCC             0x7
  73 #define OP_SH_BCC               18
  74 #define OP_MASK_CODE            0x3ff
  75 #define OP_SH_CODE              16
  76 #define OP_MASK_CODE2           0x3ff
  77 #define OP_SH_CODE2             6
  78 #define OP_MASK_RT              0x1f
  79 #define OP_SH_RT                16
  80 #define OP_MASK_FT              0x1f
  81 #define OP_SH_FT                16
  82 #define OP_MASK_CACHE           0x1f
  83 #define OP_SH_CACHE             16
  84 #define OP_MASK_RD              0x1f
  85 #define OP_SH_RD                11
  86 #define OP_MASK_FS              0x1f
  87 #define OP_SH_FS                11
  88 #define OP_MASK_PREFX           0x1f
  89 #define OP_SH_PREFX             11
  90 #define OP_MASK_CCC             0x7
  91 #define OP_SH_CCC               8
  92 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  93 #define OP_SH_CODE20            6
  94 #define OP_MASK_SHAMT           0x1f
  95 #define OP_SH_SHAMT             6
  96 #define OP_MASK_EXTLSB          OP_MASK_SHAMT
  97 #define OP_SH_EXTLSB            OP_SH_SHAMT
  98 #define OP_MASK_STYPE           OP_MASK_SHAMT
  99 #define OP_SH_STYPE             OP_SH_SHAMT
 100 #define OP_MASK_FD              0x1f
 101 #define OP_SH_FD                6
 102 #define OP_MASK_TARGET          0x3ffffff
 103 #define OP_SH_TARGET            0
 104 #define OP_MASK_COPZ            0x1ffffff
 105 #define OP_SH_COPZ              0
 106 #define OP_MASK_IMMEDIATE       0xffff
 107 #define OP_SH_IMMEDIATE         0
 108 #define OP_MASK_DELTA           0xffff
 109 #define OP_SH_DELTA             0
 110 #define OP_MASK_FUNCT           0x3f
 111 #define OP_SH_FUNCT             0
 112 #define OP_MASK_SPEC            0x3f
 113 #define OP_SH_SPEC              0
 114 #define OP_SH_LOCC              8       /* FP condition code.  */
 115 #define OP_SH_HICC              18      /* FP condition code.  */
 116 #define OP_MASK_CC              0x7
 117 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 118 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 119 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 120 #define OP_MASK_COP1SPEC        0xf
 121 #define OP_MASK_COP1SCLR        0x4
 122 #define OP_MASK_COP1CMP         0x3
 123 #define OP_SH_COP1CMP           4
 124 #define OP_SH_FORMAT            21      /* FP short format field.  */
 125 #define OP_MASK_FORMAT          0x7
 126 #define OP_SH_TRUE              16
 127 #define OP_MASK_TRUE            0x1
 128 #define OP_SH_GE                17
 129 #define OP_MASK_GE              0x01
 130 #define OP_SH_UNSIGNED          16
 131 #define OP_MASK_UNSIGNED        0x1
 132 #define OP_SH_HINT              16
 133 #define OP_MASK_HINT            0x1f
 134 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 135 #define OP_MASK_MMI             0x3f
 136 #define OP_SH_MMISUB            6
 137 #define OP_MASK_MMISUB          0x1f
 138 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 139 #define OP_SH_PERFREG           1
 140 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 141 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 142 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 143 #define OP_MASK_CODE19          0x7ffff
 144 #define OP_SH_ALN               21
 145 #define OP_MASK_ALN             0x7
 146 #define OP_SH_VSEL              21
 147 #define OP_MASK_VSEL            0x1f
 148 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 149                                            but 0x8-0xf don't select bytes.  */
 150 #define OP_SH_VECBYTE           22
 151 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 152 #define OP_SH_VECALIGN          21
 153 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 154 #define OP_SH_INSMSB            11
 155 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 156 #define OP_SH_EXTMSBD           11
 157
 158 /* MIPS DSP ASE */
 159 #define OP_SH_DSPACC            11
 160 #define OP_MASK_DSPACC          0x3
 161 #define OP_SH_DSPACC_S          21
 162 #define OP_MASK_DSPACC_S        0x3
 163 #define OP_SH_DSPSFT            20
 164 #define OP_MASK_DSPSFT          0x3f
 165 #define OP_SH_DSPSFT_7          19
 166 #define OP_MASK_DSPSFT_7        0x7f
 167 #define OP_SH_SA3               21
 168 #define OP_MASK_SA3             0x7
 169 #define OP_SH_SA4               21
 170 #define OP_MASK_SA4             0xf
 171 #define OP_SH_IMM8              16
 172 #define OP_MASK_IMM8            0xff
 173 #define OP_SH_IMM10             16
 174 #define OP_MASK_IMM10           0x3ff
 175 #define OP_SH_WRDSP             11
 176 #define OP_MASK_WRDSP           0x3f
 177 #define OP_SH_RDDSP             16
 178 #define OP_MASK_RDDSP           0x3f
 179 #define OP_SH_BP                11
 180 #define OP_MASK_BP              0x3
 181
 182 /* MIPS MT ASE */
 183 #define OP_SH_MT_U              5
 184 #define OP_MASK_MT_U            0x1
 185 #define OP_SH_MT_H              4
 186 #define OP_MASK_MT_H            0x1
 187 #define OP_SH_MTACC_T           18
 188 #define OP_MASK_MTACC_T         0x3
 189 #define OP_SH_MTACC_D           13
 190 #define OP_MASK_MTACC_D         0x3
 191
 192 /* MIPS MCU ASE */
 193 #define OP_MASK_3BITPOS         0x7
 194 #define OP_SH_3BITPOS           12
 195 #define OP_MASK_OFFSET12        0xfff
 196 #define OP_SH_OFFSET12          0
 197
 198 #define OP_OP_COP0              0x10
 199 #define OP_OP_COP1              0x11
 200 #define OP_OP_COP2              0x12
 201 #define OP_OP_COP3              0x13
 202 #define OP_OP_LWC1              0x31
 203 #define OP_OP_LWC2              0x32
 204 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 205 #define OP_OP_LDC1              0x35
 206 #define OP_OP_LDC2              0x36
 207 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 208 #define OP_OP_SWC1              0x39
 209 #define OP_OP_SWC2              0x3a
 210 #define OP_OP_SWC3              0x3b
 211 #define OP_OP_SDC1              0x3d
 212 #define OP_OP_SDC2              0x3e
 213 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 214
 215 /* MIPS VIRT ASE */
 216 #define OP_MASK_CODE10          0x3ff
 217 #define OP_SH_CODE10            11
 218
 219 /* Values in the 'VSEL' field.  */
 220 #define MDMX_FMTSEL_IMM_QH      0x1d
 221 #define MDMX_FMTSEL_IMM_OB      0x1e
 222 #define MDMX_FMTSEL_VEC_QH      0x15
 223 #define MDMX_FMTSEL_VEC_OB      0x16
 224
 225 /* UDI */
 226 #define OP_SH_UDI1              6
 227 #define OP_MASK_UDI1            0x1f
 228 #define OP_SH_UDI2              6
 229 #define OP_MASK_UDI2            0x3ff
 230 #define OP_SH_UDI3              6
 231 #define OP_MASK_UDI3            0x7fff
 232 #define OP_SH_UDI4              6
 233 #define OP_MASK_UDI4            0xfffff
 234
 235 /* Octeon */
 236 #define OP_SH_BBITIND           16
 237 #define OP_MASK_BBITIND         0x1f
 238 #define OP_SH_CINSPOS           6
 239 #define OP_MASK_CINSPOS         0x1f
 240 #define OP_SH_CINSLM1           11
 241 #define OP_MASK_CINSLM1         0x1f
 242 #define OP_SH_SEQI              6
 243 #define OP_MASK_SEQI            0x3ff
 244
 245 /* Loongson */
 246 #define OP_SH_OFFSET_A          6
 247 #define OP_MASK_OFFSET_A        0xff
 248 #define OP_SH_OFFSET_B          3
 249 #define OP_MASK_OFFSET_B        0xff
 250 #define OP_SH_OFFSET_C          6
 251 #define OP_MASK_OFFSET_C        0x1ff
 252 #define OP_SH_RZ                0
 253 #define OP_MASK_RZ              0x1f
 254 #define OP_SH_FZ                0
 255 #define OP_MASK_FZ              0x1f
 256
 257 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
 258    definition, and vice versa.  This simplifies various parts
 259    of the operand handling in GAS.  The fields below only exist
 260    in the microMIPS encoding, so define each one to have an empty
 261    range.  */
 262 #define OP_MASK_TRAP            0
 263 #define OP_SH_TRAP              0
 264 #define OP_MASK_OFFSET10        0
 265 #define OP_SH_OFFSET10          0
 266 #define OP_MASK_RS3             0
 267 #define OP_SH_RS3               0
 268 #define OP_MASK_MB              0
 269 #define OP_SH_MB                0
 270 #define OP_MASK_MC              0
 271 #define OP_SH_MC                0
 272 #define OP_MASK_MD              0
 273 #define OP_SH_MD                0
 274 #define OP_MASK_ME              0
 275 #define OP_SH_ME                0
 276 #define OP_MASK_MF              0
 277 #define OP_SH_MF                0
 278 #define OP_MASK_MG              0
 279 #define OP_SH_MG                0
 280 #define OP_MASK_MH              0
 281 #define OP_SH_MH                0
 282 #define OP_MASK_MJ              0
 283 #define OP_SH_MJ                0
 284 #define OP_MASK_ML              0
 285 #define OP_SH_ML                0
 286 #define OP_MASK_MM              0
 287 #define OP_SH_MM                0
 288 #define OP_MASK_MN              0
 289 #define OP_SH_MN                0
 290 #define OP_MASK_MP              0
 291 #define OP_SH_MP                0
 292 #define OP_MASK_MQ              0
 293 #define OP_SH_MQ                0
 294 #define OP_MASK_IMMA            0
 295 #define OP_SH_IMMA              0
 296 #define OP_MASK_IMMB            0
 297 #define OP_SH_IMMB              0
 298 #define OP_MASK_IMMC            0
 299 #define OP_SH_IMMC              0
 300 #define OP_MASK_IMMF            0
 301 #define OP_SH_IMMF              0
 302 #define OP_MASK_IMMG            0
 303 #define OP_SH_IMMG              0
 304 #define OP_MASK_IMMH            0
 305 #define OP_SH_IMMH              0
 306 #define OP_MASK_IMMI            0
 307 #define OP_SH_IMMI              0
 308 #define OP_MASK_IMMJ            0
 309 #define OP_SH_IMMJ              0
 310 #define OP_MASK_IMML            0
 311 #define OP_SH_IMML              0
 312 #define OP_MASK_IMMM            0
 313 #define OP_SH_IMMM              0
 314 #define OP_MASK_IMMN            0
 315 #define OP_SH_IMMN              0
 316 #define OP_MASK_IMMO            0
 317 #define OP_SH_IMMO              0
 318 #define OP_MASK_IMMP            0
 319 #define OP_SH_IMMP              0
 320 #define OP_MASK_IMMQ            0
 321 #define OP_SH_IMMQ              0
 322 #define OP_MASK_IMMU            0
 323 #define OP_SH_IMMU              0
 324 #define OP_MASK_IMMW            0
 325 #define OP_SH_IMMW              0
 326 #define OP_MASK_IMMX            0
 327 #define OP_SH_IMMX              0
 328 #define OP_MASK_IMMY            0
 329 #define OP_SH_IMMY              0
 330
 331 /* Enhanced VA Scheme */
 332 #define OP_SH_EVAOFFSET         7
 333 #define OP_MASK_EVAOFFSET       0x1ff
 334
 335 /* This structure holds information for a particular instruction.  */
 336
 337 struct mips_opcode
 338 {
 339   /* The name of the instruction.  */
 340   const char *name;
 341   /* A string describing the arguments for this instruction.  */
 342   const char *args;
 343   /* The basic opcode for the instruction.  When assembling, this
 344      opcode is modified by the arguments to produce the actual opcode
 345      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 346   unsigned long match;
 347   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 348      relevant portions of the opcode when disassembling.  If the
 349      actual opcode anded with the match field equals the opcode field,
 350      then we have found the correct instruction.  If pinfo is
 351      INSN_MACRO, then this field is the macro identifier.  */
 352   unsigned long mask;
 353   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 354      of bits describing the instruction, notably any relevant hazard
 355      information.  */
 356   unsigned long pinfo;
 357   /* A collection of additional bits describing the instruction. */
 358   unsigned long pinfo2;
 359   /* A collection of bits describing the instruction sets of which this
 360      instruction or macro is a member. */
 361   unsigned long membership;
 362   /* A collection of bits describing the ASE of which this instruction
 363      or macro is a member.  */
 364   unsigned long ase;
 365   /* A collection of bits describing the instruction sets of which this
 366      instruction or macro is not a member.  */
 367   unsigned long exclusions;
 368 };
 369
 370 /* These are the characters which may appear in the args field of an
 371    instruction.  They appear in the order in which the fields appear
 372    when the instruction is used.  Commas and parentheses in the args
 373    string are ignored when assembling, and written into the output
 374    when disassembling.
 375
 376    Each of these characters corresponds to a mask field defined above.
 377
 378    "1" 5 bit sync type (OP_*_STYPE)
 379    "<" 5 bit shift amount (OP_*_SHAMT)
 380    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 381    "a" 26 bit target address (OP_*_TARGET)
 382    "+i" likewise, but flips bit 0
 383    "b" 5 bit base register (OP_*_RS)
 384    "c" 10 bit breakpoint code (OP_*_CODE)
 385    "d" 5 bit destination register specifier (OP_*_RD)
 386    "h" 5 bit prefx hint (OP_*_PREFX)
 387    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 388    "j" 16 bit signed immediate (OP_*_DELTA)
 389    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 390        Also used for immediate operands in vr5400 vector insns.
 391    "o" 16 bit signed offset (OP_*_DELTA)
 392    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 393    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 394    "r" 5 bit same register used as both source and target (OP_*_RS)
 395    "s" 5 bit source register specifier (OP_*_RS)
 396    "t" 5 bit target register (OP_*_RT)
 397    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 398    "v" 5 bit same register used as both source and destination (OP_*_RS)
 399    "w" 5 bit same register used as both target and destination (OP_*_RT)
 400    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 401        (used by clo and clz)
 402    "C" 25 bit coprocessor function code (OP_*_COPZ)
 403    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 404    "J" 19 bit wait function code (OP_*_CODE19)
 405    "x" accept and ignore register name
 406    "z" must be zero register
 407    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 408    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 409         LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
 410         microMIPS compatibility).
 411         Enforces: 0 <= pos < 32.
 412    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 413         Requires that "+A" or "+E" occur first to set position.
 414         Enforces: 0 < (pos+size) <= 32.
 415    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 416         Requires that "+A" or "+E" occur first to set position.
 417         Enforces: 0 < (pos+size) <= 32.
 418         (Also used by "dext" w/ different limits, but limits for
 419         that are checked by the M_DEXT macro.)
 420    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 421         Enforces: 32 <= pos < 64.
 422    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 423         Requires that "+A" or "+E" occur first to set position.
 424         Enforces: 32 < (pos+size) <= 64.
 425    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 426         Requires that "+A" or "+E" occur first to set position.
 427         Enforces: 32 < (pos+size) <= 64.
 428    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 429         Requires that "+A" or "+E" occur first to set position.
 430         Enforces: 32 < (pos+size) <= 64.
 431
 432    Floating point instructions:
 433    "D" 5 bit destination register (OP_*_FD)
 434    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 435    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 436    "S" 5 bit fs source 1 register (OP_*_FS)
 437    "T" 5 bit ft source 2 register (OP_*_FT)
 438    "R" 5 bit fr source 3 register (OP_*_FR)
 439    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 440    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 441
 442    Coprocessor instructions:
 443    "E" 5 bit target register (OP_*_RT)
 444    "G" 5 bit destination register (OP_*_RD)
 445    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 446    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 447    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 448    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 449    see also "k" above
 450
 451    Macro instructions:
 452    "A" General 32 bit expression
 453    "I" 32 bit immediate (value placed in imm_expr).
 454    "+I" 32 bit immediate (value placed in imm2_expr).
 455    "F" 64 bit floating point constant in .rdata
 456    "L" 64 bit floating point constant in .lit8
 457    "f" 32 bit floating point constant
 458    "l" 32 bit floating point constant in .lit4
 459
 460    MDMX instruction operands (note that while these use the FP register
 461    fields, they accept both $fN and $vN names for the registers):
 462    "O"  MDMX alignment offset (OP_*_ALN)
 463    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 464    "X"  MDMX destination register (OP_*_FD)
 465    "Y"  MDMX source register (OP_*_FS)
 466    "Z"  MDMX source register (OP_*_FT)
 467
 468    DSP ASE usage:
 469    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 470    "3" 3 bit unsigned immediate (OP_*_SA3)
 471    "4" 4 bit unsigned immediate (OP_*_SA4)
 472    "5" 8 bit unsigned immediate (OP_*_IMM8)
 473    "6" 5 bit unsigned immediate (OP_*_RS)
 474    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 475    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 476    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 477    "0" 6 bit signed immediate (OP_*_DSPSFT)
 478    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 479    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 480    "@" 10 bit signed immediate (OP_*_IMM10)
 481
 482    MT ASE usage:
 483    "!" 1 bit usermode flag (OP_*_MT_U)
 484    "$" 1 bit load high flag (OP_*_MT_H)
 485    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 486    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 487    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 488    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 489
 490    MCU ASE usage:
 491    "~" 12 bit offset (OP_*_OFFSET12)
 492    "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
 493
 494    VIRT ASE usage:
 495    "+J" 10-bit hypcall code (OP_*CODE10)
 496
 497    UDI immediates:
 498    "+1" UDI immediate bits 6-10
 499    "+2" UDI immediate bits 6-15
 500    "+3" UDI immediate bits 6-20
 501    "+4" UDI immediate bits 6-25
 502
 503    Octeon:
 504    "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
 505    "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
 506         otherwise skips to next candidate.
 507    "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
 508    "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
 509         32 <= pos < 64, otherwise skips to next candidate.
 510    "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
 511    "+s" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.
 512    "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
 513         cint32/exts32.  Enforces non-negative value and that
 514         pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
 515         position field is "+p" or "+P".
 516
 517    Loongson-3A:
 518    "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
 519    "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
 520    "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
 521    "+z" 5-bit rz register (OP_*_RZ)
 522    "+Z" 5-bit fz register (OP_*_FZ)
 523
 524    Enhanced VA Scheme:
 525    "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
 526
 527    Other:
 528    "()" parens surrounding optional value
 529    ","  separates operands
 530    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 531    "+"  Start of extension sequence.
 532
 533    Characters used so far, for quick reference when adding more:
 534    "1234567890"
 535    "%[]<>(),+:'@!$*&\~"
 536    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 537    "abcdefghijklopqrstuvwxz"
 538
 539    Extension character sequences used so far ("+" followed by the
 540    following), for quick reference when adding more:
 541    "1234"
 542    "ABCEFGHIJPQSXZ"
 543    "abcijpstxz"
 544 */
 545
 546 /* These are the bits which may be set in the pinfo field of an
 547    instructions, if it is not equal to INSN_MACRO.  */
 548
 549 /* Modifies the general purpose register in OP_*_RD.  */
 550 #define INSN_WRITE_GPR_D            0x00000001
 551 /* Modifies the general purpose register in OP_*_RT.  */
 552 #define INSN_WRITE_GPR_T            0x00000002
 553 /* Modifies general purpose register 31.  */
 554 #define INSN_WRITE_GPR_31           0x00000004
 555 /* Modifies the floating point register in OP_*_FD.  */
 556 #define INSN_WRITE_FPR_D            0x00000008
 557 /* Modifies the floating point register in OP_*_FS.  */
 558 #define INSN_WRITE_FPR_S            0x00000010
 559 /* Modifies the floating point register in OP_*_FT.  */
 560 #define INSN_WRITE_FPR_T            0x00000020
 561 /* Reads the general purpose register in OP_*_RS.  */
 562 #define INSN_READ_GPR_S             0x00000040
 563 /* Reads the general purpose register in OP_*_RT.  */
 564 #define INSN_READ_GPR_T             0x00000080
 565 /* Reads the floating point register in OP_*_FS.  */
 566 #define INSN_READ_FPR_S             0x00000100
 567 /* Reads the floating point register in OP_*_FT.  */
 568 #define INSN_READ_FPR_T             0x00000200
 569 /* Reads the floating point register in OP_*_FR.  */
 570 #define INSN_READ_FPR_R             0x00000400
 571 /* Modifies coprocessor condition code.  */
 572 #define INSN_WRITE_COND_CODE        0x00000800
 573 /* Reads coprocessor condition code.  */
 574 #define INSN_READ_COND_CODE         0x00001000
 575 /* TLB operation.  */
 576 #define INSN_TLB                    0x00002000
 577 /* Reads coprocessor register other than floating point register.  */
 578 #define INSN_COP                    0x00004000
 579 /* Instruction loads value from memory, requiring delay.  */
 580 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 581 /* Instruction loads value from coprocessor, requiring delay.  */
 582 #define INSN_LOAD_COPROC_DELAY      0x00010000
 583 /* Instruction has unconditional branch delay slot.  */
 584 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 585 /* Instruction has conditional branch delay slot.  */
 586 #define INSN_COND_BRANCH_DELAY      0x00040000
 587 /* Conditional branch likely: if branch not taken, insn nullified.  */
 588 #define INSN_COND_BRANCH_LIKELY     0x00080000
 589 /* Moves to coprocessor register, requiring delay.  */
 590 #define INSN_COPROC_MOVE_DELAY      0x00100000
 591 /* Loads coprocessor register from memory, requiring delay.  */
 592 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 593 /* Reads the HI register.  */
 594 #define INSN_READ_HI                0x00400000
 595 /* Reads the LO register.  */
 596 #define INSN_READ_LO                0x00800000
 597 /* Modifies the HI register.  */
 598 #define INSN_WRITE_HI               0x01000000
 599 /* Modifies the LO register.  */
 600 #define INSN_WRITE_LO               0x02000000
 601 /* Not to be placed in a branch delay slot, either architecturally
 602    or for ease of handling (such as with instructions that take a trap).  */
 603 #define INSN_NO_DELAY_SLOT          0x04000000
 604 /* Instruction stores value into memory.  */
 605 #define INSN_STORE_MEMORY           0x08000000
 606 /* Instruction uses single precision floating point.  */
 607 #define FP_S                        0x10000000
 608 /* Instruction uses double precision floating point.  */
 609 #define FP_D                        0x20000000
 610 /* Instruction is part of the tx39's integer multiply family.    */
 611 #define INSN_MULT                   0x40000000
 612 /* Modifies the general purpose register in MICROMIPSOP_*_RS.  */
 613 #define INSN_WRITE_GPR_S            0x80000000
 614 /* Instruction is actually a macro.  It should be ignored by the
 615    disassembler, and requires special treatment by the assembler.  */
 616 #define INSN_MACRO                  0xffffffff
 617
 618 /* These are the bits which may be set in the pinfo2 field of an
 619    instruction. */
 620
 621 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 622 #define INSN2_ALIAS                 0x00000001
 623 /* Instruction reads MDMX accumulator. */
 624 #define INSN2_READ_MDMX_ACC         0x00000002
 625 /* Instruction writes MDMX accumulator. */
 626 #define INSN2_WRITE_MDMX_ACC        0x00000004
 627 /* Macro uses single-precision floating-point instructions.  This should
 628    only be set for macros.  For instructions, FP_S in pinfo carries the
 629    same information.  */
 630 #define INSN2_M_FP_S                0x00000008
 631 /* Macro uses double-precision floating-point instructions.  This should
 632    only be set for macros.  For instructions, FP_D in pinfo carries the
 633    same information.  */
 634 #define INSN2_M_FP_D                0x00000010
 635 /* Modifies the general purpose register in OP_*_RZ.  */
 636 #define INSN2_WRITE_GPR_Z           0x00000020
 637 /* Modifies the floating point register in OP_*_FZ.  */
 638 #define INSN2_WRITE_FPR_Z           0x00000040
 639 /* Reads the general purpose register in OP_*_RZ.  */
 640 #define INSN2_READ_GPR_Z            0x00000080
 641 /* Reads the floating point register in OP_*_FZ.  */
 642 #define INSN2_READ_FPR_Z            0x00000100
 643 /* Reads the general purpose register in OP_*_RD.  */
 644 #define INSN2_READ_GPR_D            0x00000200
 645
 646
 647 /* Instruction has a branch delay slot that requires a 16-bit instruction.  */
 648 #define INSN2_BRANCH_DELAY_16BIT    0x00000400
 649 /* Instruction has a branch delay slot that requires a 32-bit instruction.  */
 650 #define INSN2_BRANCH_DELAY_32BIT    0x00000800
 651 /* Reads the floating point register in MICROMIPSOP_*_FD.  */
 652 #define INSN2_READ_FPR_D            0x00001000
 653 /* Modifies the general purpose register in MICROMIPSOP_*_MB.  */
 654 #define INSN2_WRITE_GPR_MB          0x00002000
 655 /* Reads the general purpose register in MICROMIPSOP_*_MC.  */
 656 #define INSN2_READ_GPR_MC           0x00004000
 657 /* Reads/writes the general purpose register in MICROMIPSOP_*_MD.  */
 658 #define INSN2_MOD_GPR_MD            0x00008000
 659 /* Reads the general purpose register in MICROMIPSOP_*_ME.  */
 660 #define INSN2_READ_GPR_ME           0x00010000
 661 /* Reads/writes the general purpose register in MICROMIPSOP_*_MF.  */
 662 #define INSN2_MOD_GPR_MF            0x00020000
 663 /* Reads the general purpose register in MICROMIPSOP_*_MG.  */
 664 #define INSN2_READ_GPR_MG           0x00040000
 665 /* Reads the general purpose register in MICROMIPSOP_*_MJ.  */
 666 #define INSN2_READ_GPR_MJ           0x00080000
 667 /* Modifies the general purpose register in MICROMIPSOP_*_MJ.  */
 668 #define INSN2_WRITE_GPR_MJ          0x00100000
 669 /* Reads the general purpose register in MICROMIPSOP_*_MP.  */
 670 #define INSN2_READ_GPR_MP           0x00200000
 671 /* Modifies the general purpose register in MICROMIPSOP_*_MP.  */
 672 #define INSN2_WRITE_GPR_MP          0x00400000
 673 /* Reads the general purpose register in MICROMIPSOP_*_MQ.  */
 674 #define INSN2_READ_GPR_MQ           0x00800000
 675 /* Reads/Writes the stack pointer ($29).  */
 676 #define INSN2_MOD_SP                0x01000000
 677 /* Reads the RA ($31) register.  */
 678 #define INSN2_READ_GPR_31           0x02000000
 679 /* Reads the global pointer ($28).  */
 680 #define INSN2_READ_GP               0x04000000
 681 /* Reads the program counter ($pc).  */
 682 #define INSN2_READ_PC               0x08000000
 683 /* Is an unconditional branch insn. */
 684 #define INSN2_UNCOND_BRANCH         0x10000000
 685 /* Is a conditional branch insn. */
 686 #define INSN2_COND_BRANCH           0x20000000
 687 /* Modifies the general purpose registers in MICROMIPSOP_*_MH.  */
 688 #define INSN2_WRITE_GPR_MH          0x40000000
 689 /* Reads the general purpose registers in MICROMIPSOP_*_MM/N.  */
 690 #define INSN2_READ_GPR_MMN          0x80000000
 691
 692 /* Masks used to mark instructions to indicate which MIPS ISA level
 693    they were introduced in.  INSN_ISA_MASK masks an enumeration that
 694    specifies the base ISA level(s).  The remainder of a 32-bit
 695    word constructed using these macros is a bitmask of the remaining
 696    INSN_* values below.  */
 697
 698 #define INSN_ISA_MASK             0x0000000ful
 699
 700 /* We cannot start at zero due to ISA_UNKNOWN below.  */
 701 #define INSN_ISA1                 1
 702 #define INSN_ISA2                 2
 703 #define INSN_ISA3                 3
 704 #define INSN_ISA4                 4
 705 #define INSN_ISA5                 5
 706 #define INSN_ISA32                6
 707 #define INSN_ISA32R2              7
 708 #define INSN_ISA64                8
 709 #define INSN_ISA64R2              9
 710 /* Below this point the INSN_* values correspond to combinations of ISAs.
 711    They are only for use in the opcodes table to indicate membership of
 712    a combination of ISAs that cannot be expressed using the usual inclusion
 713    ordering on the above INSN_* values.  */
 714 #define INSN_ISA3_32              10
 715 #define INSN_ISA3_32R2            11
 716 #define INSN_ISA4_32              12
 717 #define INSN_ISA4_32R2            13
 718 #define INSN_ISA5_32R2            14
 719
 720 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
 721    INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
 722    this table describes whether at least one of the ISAs described by X
 723    is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
 724    a particular core and X as the ISA level(s) at which a certain instruction
 725    is defined.)  The ISA(s) described by X is/are implemented by Y iff
 726    (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
 727    is non-zero.  */
 728 static const unsigned int mips_isa_table[] =
 729   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 730
 731 /* Masks used for Chip specific instructions.  */
 732 #define INSN_CHIP_MASK            0xc3ff0f20
 733
 734 /* Cavium Networks Octeon instructions.  */
 735 #define INSN_OCTEON               0x00000800
 736 #define INSN_OCTEONP              0x00000200
 737 #define INSN_OCTEON2              0x00000100
 738
 739 /* MIPS R5900 instruction */
 740 #define INSN_5900                 0x00004000
 741
 742 /* MIPS R4650 instruction.  */
 743 #define INSN_4650                 0x00010000
 744 /* LSI R4010 instruction.  */
 745 #define INSN_4010                 0x00020000
 746 /* NEC VR4100 instruction.  */
 747 #define INSN_4100                 0x00040000
 748 /* Toshiba R3900 instruction.  */
 749 #define INSN_3900                 0x00080000
 750 /* MIPS R10000 instruction.  */
 751 #define INSN_10000                0x00100000
 752 /* Broadcom SB-1 instruction.  */
 753 #define INSN_SB1                  0x00200000
 754 /* NEC VR4111/VR4181 instruction.  */
 755 #define INSN_4111                 0x00400000
 756 /* NEC VR4120 instruction.  */
 757 #define INSN_4120                 0x00800000
 758 /* NEC VR5400 instruction.  */
 759 #define INSN_5400                 0x01000000
 760 /* NEC VR5500 instruction.  */
 761 #define INSN_5500                 0x02000000
 762
 763 /* ST Microelectronics Loongson 2E.  */
 764 #define INSN_LOONGSON_2E          0x40000000
 765 /* ST Microelectronics Loongson 2F.  */
 766 #define INSN_LOONGSON_2F          0x80000000
 767 /* Loongson 3A.  */
 768 #define INSN_LOONGSON_3A          0x00000400
 769 /* RMI Xlr instruction */
 770 #define INSN_XLR                 0x00000020
 771
 772 /* DSP ASE */
 773 #define ASE_DSP                 0x00000001
 774 #define ASE_DSP64               0x00000002
 775 /* DSP R2 ASE  */
 776 #define ASE_DSPR2               0x00000004
 777 /* Enhanced VA Scheme */
 778 #define ASE_EVA                 0x00000008
 779 /* MCU (MicroController) ASE */
 780 #define ASE_MCU                 0x00000010
 781 /* MDMX ASE */
 782 #define ASE_MDMX                0x00000020
 783 /* MIPS-3D ASE */
 784 #define ASE_MIPS3D              0x00000040
 785 /* MT ASE */
 786 #define ASE_MT                  0x00000080
 787 /* SmartMIPS ASE  */
 788 #define ASE_SMARTMIPS           0x00000100
 789 /* Virtualization ASE */
 790 #define ASE_VIRT                0x00000200
 791 #define ASE_VIRT64              0x00000400
 792
 793 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 794
 795 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 796 #define       ISA_MIPS1       INSN_ISA1
 797 #define       ISA_MIPS2       INSN_ISA2
 798 #define       ISA_MIPS3       INSN_ISA3
 799 #define       ISA_MIPS4       INSN_ISA4
 800 #define       ISA_MIPS5       INSN_ISA5
 801
 802 #define       ISA_MIPS32      INSN_ISA32
 803 #define       ISA_MIPS64      INSN_ISA64
 804
 805 #define       ISA_MIPS32R2    INSN_ISA32R2
 806 #define       ISA_MIPS64R2    INSN_ISA64R2
 807
 808
 809 /* CPU defines, use instead of hardcoding processor number. Keep this
 810    in sync with bfd/archures.c in order for machine selection to work.  */
 811 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 812 #define CPU_R3000       3000
 813 #define CPU_R3900       3900
 814 #define CPU_R4000       4000
 815 #define CPU_R4010       4010
 816 #define CPU_VR4100      4100
 817 #define CPU_R4111       4111
 818 #define CPU_VR4120      4120
 819 #define CPU_R4300       4300
 820 #define CPU_R4400       4400
 821 #define CPU_R4600       4600
 822 #define CPU_R4650       4650
 823 #define CPU_R5000       5000
 824 #define CPU_VR5400      5400
 825 #define CPU_VR5500      5500
 826 #define CPU_R5900       5900
 827 #define CPU_R6000       6000
 828 #define CPU_RM7000      7000
 829 #define CPU_R8000       8000
 830 #define CPU_RM9000      9000
 831 #define CPU_R10000      10000
 832 #define CPU_R12000      12000
 833 #define CPU_R14000      14000
 834 #define CPU_R16000      16000
 835 #define CPU_MIPS16      16
 836 #define CPU_MIPS32      32
 837 #define CPU_MIPS32R2    33
 838 #define CPU_MIPS5       5
 839 #define CPU_MIPS64      64
 840 #define CPU_MIPS64R2    65
 841 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 842 #define CPU_LOONGSON_2E 3001
 843 #define CPU_LOONGSON_2F 3002
 844 #define CPU_LOONGSON_3A 3003
 845 #define CPU_OCTEON      6501
 846 #define CPU_OCTEONP     6601
 847 #define CPU_OCTEON2     6502
 848 #define CPU_XLR         887682          /* decimal 'XLR'   */
 849
 850 /* Return true if the given CPU is included in INSN_* mask MASK.  */
 851
 852 static inline bfd_boolean
 853 cpu_is_member (int cpu, unsigned int mask)
 854 {
 855   switch (cpu)
 856     {
 857     case CPU_R4650:
 858     case CPU_RM7000:
 859     case CPU_RM9000:
 860       return (mask & INSN_4650) != 0;
 861
 862     case CPU_R4010:
 863       return (mask & INSN_4010) != 0;
 864
 865     case CPU_VR4100:
 866       return (mask & INSN_4100) != 0;
 867
 868     case CPU_R3900:
 869       return (mask & INSN_3900) != 0;
 870
 871     case CPU_R10000:
 872     case CPU_R12000:
 873     case CPU_R14000:
 874     case CPU_R16000:
 875       return (mask & INSN_10000) != 0;
 876
 877     case CPU_SB1:
 878       return (mask & INSN_SB1) != 0;
 879
 880     case CPU_R4111:
 881       return (mask & INSN_4111) != 0;
 882
 883     case CPU_VR4120:
 884       return (mask & INSN_4120) != 0;
 885
 886     case CPU_VR5400:
 887       return (mask & INSN_5400) != 0;
 888
 889     case CPU_VR5500:
 890       return (mask & INSN_5500) != 0;
 891
 892     case CPU_R5900:
 893       return (mask & INSN_5900) != 0;
 894
 895     case CPU_LOONGSON_2E:
 896       return (mask & INSN_LOONGSON_2E) != 0;
 897
 898     case CPU_LOONGSON_2F:
 899       return (mask & INSN_LOONGSON_2F) != 0;
 900
 901     case CPU_LOONGSON_3A:
 902       return (mask & INSN_LOONGSON_3A) != 0;
 903
 904     case CPU_OCTEON:
 905       return (mask & INSN_OCTEON) != 0;
 906
 907     case CPU_OCTEONP:
 908       return (mask & INSN_OCTEONP) != 0;
 909
 910     case CPU_OCTEON2:
 911       return (mask & INSN_OCTEON2) != 0;
 912
 913     case CPU_XLR:
 914       return (mask & INSN_XLR) != 0;
 915
 916     default:
 917       return FALSE;
 918     }
 919 }
 920
 921 /* Test for membership in an ISA including chip specific ISAs.  INSN
 922    is pointer to an element of the opcode table; ISA is the specified
 923    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 924    test, or zero if no CPU specific ISA test is desired.  Return true
 925    if instruction INSN is available to the given ISA and CPU. */
 926
 927 static inline bfd_boolean
 928 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
 929 {
 930   if (!cpu_is_member (cpu, insn->exclusions))
 931     {
 932       /* Test for ISA level compatibility.  */
 933       if ((isa & INSN_ISA_MASK) != 0
 934           && (insn->membership & INSN_ISA_MASK) != 0
 935           && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
 936                >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
 937         return TRUE;
 938
 939       /* Test for ASE compatibility.  */
 940       if ((ase & insn->ase) != 0)
 941         return TRUE;
 942
 943       /* Test for processor-specific extensions.  */
 944       if (cpu_is_member (cpu, insn->membership))
 945         return TRUE;
 946     }
 947   return FALSE;
 948 }
 949
 950 /* This is a list of macro expanded instructions.
 951
 952    _I appended means immediate
 953    _A appended means address
 954    _AB appended means address with base register
 955    _D appended means 64 bit floating point constant
 956    _S appended means 32 bit floating point constant.  */
 957
 958 enum
 959 {
 960   M_ABS,
 961   M_ACLR_AB,
 962   M_ACLR_OB,
 963   M_ADD_I,
 964   M_ADDU_I,
 965   M_AND_I,
 966   M_ASET_AB,
 967   M_ASET_OB,
 968   M_BALIGN,
 969   M_BC1FL,
 970   M_BC1TL,
 971   M_BC2FL,
 972   M_BC2TL,
 973   M_BEQ,
 974   M_BEQ_I,
 975   M_BEQL,
 976   M_BEQL_I,
 977   M_BGE,
 978   M_BGEL,
 979   M_BGE_I,
 980   M_BGEL_I,
 981   M_BGEU,
 982   M_BGEUL,
 983   M_BGEU_I,
 984   M_BGEUL_I,
 985   M_BGEZ,
 986   M_BGEZL,
 987   M_BGEZALL,
 988   M_BGT,
 989   M_BGTL,
 990   M_BGT_I,
 991   M_BGTL_I,
 992   M_BGTU,
 993   M_BGTUL,
 994   M_BGTU_I,
 995   M_BGTUL_I,
 996   M_BGTZ,
 997   M_BGTZL,
 998   M_BLE,
 999   M_BLEL,
1000   M_BLE_I,
1001   M_BLEL_I,
1002   M_BLEU,
1003   M_BLEUL,
1004   M_BLEU_I,
1005   M_BLEUL_I,
1006   M_BLEZ,
1007   M_BLEZL,
1008   M_BLT,
1009   M_BLTL,
1010   M_BLT_I,
1011   M_BLTL_I,
1012   M_BLTU,
1013   M_BLTUL,
1014   M_BLTU_I,
1015   M_BLTUL_I,
1016   M_BLTZ,
1017   M_BLTZL,
1018   M_BLTZALL,
1019   M_BNE,
1020   M_BNEL,
1021   M_BNE_I,
1022   M_BNEL_I,
1023   M_CACHE_AB,
1024   M_CACHE_OB,
1025   M_CACHEE_AB,
1026   M_CACHEE_OB,
1027   M_DABS,
1028   M_DADD_I,
1029   M_DADDU_I,
1030   M_DDIV_3,
1031   M_DDIV_3I,
1032   M_DDIVU_3,
1033   M_DDIVU_3I,
1034   M_DEXT,
1035   M_DINS,
1036   M_DIV_3,
1037   M_DIV_3I,
1038   M_DIVU_3,
1039   M_DIVU_3I,
1040   M_DLA_AB,
1041   M_DLCA_AB,
1042   M_DLI,
1043   M_DMUL,
1044   M_DMUL_I,
1045   M_DMULO,
1046   M_DMULO_I,
1047   M_DMULOU,
1048   M_DMULOU_I,
1049   M_DREM_3,
1050   M_DREM_3I,
1051   M_DREMU_3,
1052   M_DREMU_3I,
1053   M_DSUB_I,
1054   M_DSUBU_I,
1055   M_DSUBU_I_2,
1056   M_J_A,
1057   M_JAL_1,
1058   M_JAL_2,
1059   M_JAL_A,
1060   M_JALS_1,
1061   M_JALS_2,
1062   M_JALS_A,
1063   M_JRADDIUSP,
1064   M_JRC,
1065   M_L_DOB,
1066   M_L_DAB,
1067   M_LA_AB,
1068   M_LB_A,
1069   M_LB_AB,
1070   M_LBE_OB,
1071   M_LBE_AB,
1072   M_LBU_A,
1073   M_LBU_AB,
1074   M_LBUE_OB,
1075   M_LBUE_AB,
1076   M_LCA_AB,
1077   M_LD_A,
1078   M_LD_OB,
1079   M_LD_AB,
1080   M_LDC1_AB,
1081   M_LDC2_AB,
1082   M_LDC2_OB,
1083   M_LQC2_AB,
1084   M_LDC3_AB,
1085   M_LDL_AB,
1086   M_LDL_OB,
1087   M_LDM_AB,
1088   M_LDM_OB,
1089   M_LDP_AB,
1090   M_LDP_OB,
1091   M_LDR_AB,
1092   M_LDR_OB,
1093   M_LH_A,
1094   M_LH_AB,
1095   M_LHE_OB,
1096   M_LHE_AB,
1097   M_LHU_A,
1098   M_LHU_AB,
1099   M_LHUE_OB,
1100   M_LHUE_AB,
1101   M_LI,
1102   M_LI_D,
1103   M_LI_DD,
1104   M_LI_S,
1105   M_LI_SS,
1106   M_LL_AB,
1107   M_LL_OB,
1108   M_LLD_AB,
1109   M_LLD_OB,
1110   M_LLE_AB,
1111   M_LLE_OB,
1112   M_LQ_AB,
1113   M_LS_A,
1114   M_LW_A,
1115   M_LW_AB,
1116   M_LWE_OB,
1117   M_LWE_AB,
1118   M_LWC0_A,
1119   M_LWC0_AB,
1120   M_LWC1_A,
1121   M_LWC1_AB,
1122   M_LWC2_A,
1123   M_LWC2_AB,
1124   M_LWC2_OB,
1125   M_LWC3_A,
1126   M_LWC3_AB,
1127   M_LWL_A,
1128   M_LWL_AB,
1129   M_LWL_OB,
1130   M_LWLE_AB,
1131   M_LWLE_OB,
1132   M_LWM_AB,
1133   M_LWM_OB,
1134   M_LWP_AB,
1135   M_LWP_OB,
1136   M_LWR_A,
1137   M_LWR_AB,
1138   M_LWR_OB,
1139   M_LWRE_AB,
1140   M_LWRE_OB,
1141   M_LWU_AB,
1142   M_LWU_OB,
1143   M_MSGSND,
1144   M_MSGLD,
1145   M_MSGLD_T,
1146   M_MSGWAIT,
1147   M_MSGWAIT_T,
1148   M_MOVE,
1149   M_MOVEP,
1150   M_MUL,
1151   M_MUL_I,
1152   M_MULO,
1153   M_MULO_I,
1154   M_MULOU,
1155   M_MULOU_I,
1156   M_NOR_I,
1157   M_OR_I,
1158   M_PREF_AB,
1159   M_PREF_OB,
1160   M_PREFE_AB,
1161   M_PREFE_OB,
1162   M_REM_3,
1163   M_REM_3I,
1164   M_REMU_3,
1165   M_REMU_3I,
1166   M_DROL,
1167   M_ROL,
1168   M_DROL_I,
1169   M_ROL_I,
1170   M_DROR,
1171   M_ROR,
1172   M_DROR_I,
1173   M_ROR_I,
1174   M_S_DA,
1175   M_S_DOB,
1176   M_S_DAB,
1177   M_S_S,
1178   M_SAA_AB,
1179   M_SAA_OB,
1180   M_SAAD_AB,
1181   M_SAAD_OB,
1182   M_SC_AB,
1183   M_SC_OB,
1184   M_SCD_AB,
1185   M_SCD_OB,
1186   M_SCE_AB,
1187   M_SCE_OB,
1188   M_SD_A,
1189   M_SD_OB,
1190   M_SD_AB,
1191   M_SDC1_AB,
1192   M_SDC2_AB,
1193   M_SDC2_OB,
1194   M_SQC2_AB,
1195   M_SDC3_AB,
1196   M_SDL_AB,
1197   M_SDL_OB,
1198   M_SDM_AB,
1199   M_SDM_OB,
1200   M_SDP_AB,
1201   M_SDP_OB,
1202   M_SDR_AB,
1203   M_SDR_OB,
1204   M_SEQ,
1205   M_SEQ_I,
1206   M_SGE,
1207   M_SGE_I,
1208   M_SGEU,
1209   M_SGEU_I,
1210   M_SGT,
1211   M_SGT_I,
1212   M_SGTU,
1213   M_SGTU_I,
1214   M_SLE,
1215   M_SLE_I,
1216   M_SLEU,
1217   M_SLEU_I,
1218   M_SLT_I,
1219   M_SLTU_I,
1220   M_SNE,
1221   M_SNE_I,
1222   M_SB_A,
1223   M_SB_AB,
1224   M_SBE_OB,
1225   M_SBE_AB,
1226   M_SH_A,
1227   M_SH_AB,
1228   M_SHE_OB,
1229   M_SHE_AB,
1230   M_SQ_AB,
1231   M_SW_A,
1232   M_SW_AB,
1233   M_SWE_OB,
1234   M_SWE_AB,
1235   M_SWC0_A,
1236   M_SWC0_AB,
1237   M_SWC1_A,
1238   M_SWC1_AB,
1239   M_SWC2_A,
1240   M_SWC2_AB,
1241   M_SWC2_OB,
1242   M_SWC3_A,
1243   M_SWC3_AB,
1244   M_SWL_A,
1245   M_SWL_AB,
1246   M_SWL_OB,
1247   M_SWLE_AB,
1248   M_SWLE_OB,
1249   M_SWM_AB,
1250   M_SWM_OB,
1251   M_SWP_AB,
1252   M_SWP_OB,
1253   M_SWR_A,
1254   M_SWR_AB,
1255   M_SWR_OB,
1256   M_SWRE_AB,
1257   M_SWRE_OB,
1258   M_SUB_I,
1259   M_SUBU_I,
1260   M_SUBU_I_2,
1261   M_TEQ_I,
1262   M_TGE_I,
1263   M_TGEU_I,
1264   M_TLT_I,
1265   M_TLTU_I,
1266   M_TNE_I,
1267   M_TRUNCWD,
1268   M_TRUNCWS,
1269   M_ULD,
1270   M_ULD_A,
1271   M_ULH,
1272   M_ULH_A,
1273   M_ULHU,
1274   M_ULHU_A,
1275   M_ULW,
1276   M_ULW_A,
1277   M_USH,
1278   M_USH_A,
1279   M_USW,
1280   M_USW_A,
1281   M_USD,
1282   M_USD_A,
1283   M_XOR_I,
1284   M_COP0,
1285   M_COP1,
1286   M_COP2,
1287   M_COP3,
1288   M_NUM_MACROS
1289 };
1290
1291
1292 /* The order of overloaded instructions matters.  Label arguments and
1293    register arguments look the same. Instructions that can have either
1294    for arguments must apear in the correct order in this table for the
1295    assembler to pick the right one. In other words, entries with
1296    immediate operands must apear after the same instruction with
1297    registers.
1298
1299    Many instructions are short hand for other instructions (i.e., The
1300    jal <register> instruction is short for jalr <register>).  */
1301
1302 extern const struct mips_opcode mips_builtin_opcodes[];
1303 extern const int bfd_mips_num_builtin_opcodes;
1304 extern struct mips_opcode *mips_opcodes;
1305 extern int bfd_mips_num_opcodes;
1306 #define NUMOPCODES bfd_mips_num_opcodes
1307
1308 \f
1309 /* The rest of this file adds definitions for the mips16 TinyRISC
1310    processor.  */
1311
1312 /* These are the bitmasks and shift counts used for the different
1313    fields in the instruction formats.  Other than OP, no masks are
1314    provided for the fixed portions of an instruction, since they are
1315    not needed.
1316
1317    The I format uses IMM11.
1318
1319    The RI format uses RX and IMM8.
1320
1321    The RR format uses RX, and RY.
1322
1323    The RRI format uses RX, RY, and IMM5.
1324
1325    The RRR format uses RX, RY, and RZ.
1326
1327    The RRI_A format uses RX, RY, and IMM4.
1328
1329    The SHIFT format uses RX, RY, and SHAMT.
1330
1331    The I8 format uses IMM8.
1332
1333    The I8_MOVR32 format uses RY and REGR32.
1334
1335    The IR_MOV32R format uses REG32R and MOV32Z.
1336
1337    The I64 format uses IMM8.
1338
1339    The RI64 format uses RY and IMM5.
1340    */
1341
1342 #define MIPS16OP_MASK_OP        0x1f
1343 #define MIPS16OP_SH_OP          11
1344 #define MIPS16OP_MASK_IMM11     0x7ff
1345 #define MIPS16OP_SH_IMM11       0
1346 #define MIPS16OP_MASK_RX        0x7
1347 #define MIPS16OP_SH_RX          8
1348 #define MIPS16OP_MASK_IMM8      0xff
1349 #define MIPS16OP_SH_IMM8        0
1350 #define MIPS16OP_MASK_RY        0x7
1351 #define MIPS16OP_SH_RY          5
1352 #define MIPS16OP_MASK_IMM5      0x1f
1353 #define MIPS16OP_SH_IMM5        0
1354 #define MIPS16OP_MASK_RZ        0x7
1355 #define MIPS16OP_SH_RZ          2
1356 #define MIPS16OP_MASK_IMM4      0xf
1357 #define MIPS16OP_SH_IMM4        0
1358 #define MIPS16OP_MASK_REGR32    0x1f
1359 #define MIPS16OP_SH_REGR32      0
1360 #define MIPS16OP_MASK_REG32R    0x1f
1361 #define MIPS16OP_SH_REG32R      3
1362 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1363 #define MIPS16OP_MASK_MOVE32Z   0x7
1364 #define MIPS16OP_SH_MOVE32Z     0
1365 #define MIPS16OP_MASK_IMM6      0x3f
1366 #define MIPS16OP_SH_IMM6        5
1367
1368 /* These are the characters which may appears in the args field of a MIPS16
1369    instruction.  They appear in the order in which the fields appear when the
1370    instruction is used.  Commas and parentheses in the args string are ignored
1371    when assembling, and written into the output when disassembling.
1372
1373    "y" 3 bit register (MIPS16OP_*_RY)
1374    "x" 3 bit register (MIPS16OP_*_RX)
1375    "z" 3 bit register (MIPS16OP_*_RZ)
1376    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1377    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1378    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1379    "0" zero register ($0)
1380    "S" stack pointer ($sp or $29)
1381    "P" program counter
1382    "R" return address register ($ra or $31)
1383    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1384    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1385    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1386    "a" 26 bit jump address
1387    "i" likewise, but flips bit 0
1388    "e" 11 bit extension value
1389    "l" register list for entry instruction
1390    "L" register list for exit instruction
1391
1392    The remaining codes may be extended.  Except as otherwise noted,
1393    the full extended operand is a 16 bit signed value.
1394    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1395    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1396    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1397    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1398    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1399    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1400    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1401    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1402    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1403    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1404    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1405    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1406    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1407    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1408    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1409    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1410    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1411    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1412    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1413    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1414    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1415    "m" 7 bit register list for save instruction (18 bit extended)
1416    "M" 7 bit register list for restore instruction (18 bit extended)
1417   */
1418
1419 /* Save/restore encoding for the args field when all 4 registers are
1420    either saved as arguments or saved/restored as statics.  */
1421 #define MIPS16_ALL_ARGS    0xe
1422 #define MIPS16_ALL_STATICS 0xb
1423
1424 /* For the mips16, we use the same opcode table format and a few of
1425    the same flags.  However, most of the flags are different.  */
1426
1427 /* Modifies the register in MIPS16OP_*_RX.  */
1428 #define MIPS16_INSN_WRITE_X                 0x00000001
1429 /* Modifies the register in MIPS16OP_*_RY.  */
1430 #define MIPS16_INSN_WRITE_Y                 0x00000002
1431 /* Modifies the register in MIPS16OP_*_RZ.  */
1432 #define MIPS16_INSN_WRITE_Z                 0x00000004
1433 /* Modifies the T ($24) register.  */
1434 #define MIPS16_INSN_WRITE_T                 0x00000008
1435 /* Modifies the SP ($29) register.  */
1436 #define MIPS16_INSN_WRITE_SP                0x00000010
1437 /* Modifies the RA ($31) register.  */
1438 #define MIPS16_INSN_WRITE_31                0x00000020
1439 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1440 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1441 /* Reads the register in MIPS16OP_*_RX.  */
1442 #define MIPS16_INSN_READ_X                  0x00000080
1443 /* Reads the register in MIPS16OP_*_RY.  */
1444 #define MIPS16_INSN_READ_Y                  0x00000100
1445 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1446 #define MIPS16_INSN_READ_Z                  0x00000200
1447 /* Reads the T ($24) register.  */
1448 #define MIPS16_INSN_READ_T                  0x00000400
1449 /* Reads the SP ($29) register.  */
1450 #define MIPS16_INSN_READ_SP                 0x00000800
1451 /* Reads the RA ($31) register.  */
1452 #define MIPS16_INSN_READ_31                 0x00001000
1453 /* Reads the program counter.  */
1454 #define MIPS16_INSN_READ_PC                 0x00002000
1455 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1456 #define MIPS16_INSN_READ_GPR_X              0x00004000
1457 /* Is an unconditional branch insn. */
1458 #define MIPS16_INSN_UNCOND_BRANCH           0x00008000
1459 /* Is a conditional branch insn. */
1460 #define MIPS16_INSN_COND_BRANCH             0x00010000
1461
1462 /* The following flags have the same value for the mips16 opcode
1463    table:
1464
1465    INSN_ISA3
1466
1467    INSN_UNCOND_BRANCH_DELAY
1468    INSN_COND_BRANCH_DELAY
1469    INSN_COND_BRANCH_LIKELY (never used)
1470    INSN_READ_HI
1471    INSN_READ_LO
1472    INSN_WRITE_HI
1473    INSN_WRITE_LO
1474    INSN_TRAP
1475    FP_D (never used)
1476    */
1477
1478 extern const struct mips_opcode mips16_opcodes[];
1479 extern const int bfd_mips16_num_opcodes;
1480
1481 /* These are the bit masks and shift counts used for the different fields
1482    in the microMIPS instruction formats.  No masks are provided for the
1483    fixed portions of an instruction, since they are not needed.  */
1484
1485 #define MICROMIPSOP_MASK_IMMEDIATE      0xffff
1486 #define MICROMIPSOP_SH_IMMEDIATE        0
1487 #define MICROMIPSOP_MASK_DELTA          0xffff
1488 #define MICROMIPSOP_SH_DELTA            0
1489 #define MICROMIPSOP_MASK_CODE10         0x3ff
1490 #define MICROMIPSOP_SH_CODE10           16      /* 10-bit wait code.  */
1491 #define MICROMIPSOP_MASK_TRAP           0xf
1492 #define MICROMIPSOP_SH_TRAP             12      /* 4-bit trap code.  */
1493 #define MICROMIPSOP_MASK_SHAMT          0x1f
1494 #define MICROMIPSOP_SH_SHAMT            11
1495 #define MICROMIPSOP_MASK_TARGET         0x3ffffff
1496 #define MICROMIPSOP_SH_TARGET           0
1497 #define MICROMIPSOP_MASK_EXTLSB         0x1f    /* "ext" LSB.  */
1498 #define MICROMIPSOP_SH_EXTLSB           6
1499 #define MICROMIPSOP_MASK_EXTMSBD        0x1f    /* "ext" MSBD.  */
1500 #define MICROMIPSOP_SH_EXTMSBD          11
1501 #define MICROMIPSOP_MASK_INSMSB         0x1f    /* "ins" MSB.  */
1502 #define MICROMIPSOP_SH_INSMSB           11
1503 #define MICROMIPSOP_MASK_CODE           0x3ff
1504 #define MICROMIPSOP_SH_CODE             16      /* 10-bit higher break code. */
1505 #define MICROMIPSOP_MASK_CODE2          0x3ff
1506 #define MICROMIPSOP_SH_CODE2            6       /* 10-bit lower break code.  */
1507 #define MICROMIPSOP_MASK_CACHE          0x1f
1508 #define MICROMIPSOP_SH_CACHE            21      /* 5-bit cache op.  */
1509 #define MICROMIPSOP_MASK_SEL            0x7
1510 #define MICROMIPSOP_SH_SEL              11
1511 #define MICROMIPSOP_MASK_OFFSET12       0xfff
1512 #define MICROMIPSOP_SH_OFFSET12         0
1513 #define MICROMIPSOP_MASK_3BITPOS        0x7
1514 #define MICROMIPSOP_SH_3BITPOS          21
1515 #define MICROMIPSOP_MASK_STYPE          0x1f
1516 #define MICROMIPSOP_SH_STYPE            16
1517 #define MICROMIPSOP_MASK_OFFSET10       0x3ff
1518 #define MICROMIPSOP_SH_OFFSET10         6
1519 #define MICROMIPSOP_MASK_RS             0x1f
1520 #define MICROMIPSOP_SH_RS               16
1521 #define MICROMIPSOP_MASK_RT             0x1f
1522 #define MICROMIPSOP_SH_RT               21
1523 #define MICROMIPSOP_MASK_RD             0x1f
1524 #define MICROMIPSOP_SH_RD               11
1525 #define MICROMIPSOP_MASK_FS             0x1f
1526 #define MICROMIPSOP_SH_FS               16
1527 #define MICROMIPSOP_MASK_FT             0x1f
1528 #define MICROMIPSOP_SH_FT               21
1529 #define MICROMIPSOP_MASK_FD             0x1f
1530 #define MICROMIPSOP_SH_FD               11
1531 #define MICROMIPSOP_MASK_FR             0x1f
1532 #define MICROMIPSOP_SH_FR               6
1533 #define MICROMIPSOP_MASK_RS3            0x1f
1534 #define MICROMIPSOP_SH_RS3              6
1535 #define MICROMIPSOP_MASK_PREFX          0x1f
1536 #define MICROMIPSOP_SH_PREFX            11
1537 #define MICROMIPSOP_MASK_BCC            0x7
1538 #define MICROMIPSOP_SH_BCC              18
1539 #define MICROMIPSOP_MASK_CCC            0x7
1540 #define MICROMIPSOP_SH_CCC              13
1541 #define MICROMIPSOP_MASK_COPZ           0x7fffff
1542 #define MICROMIPSOP_SH_COPZ             3
1543
1544 #define MICROMIPSOP_MASK_MB             0x7
1545 #define MICROMIPSOP_SH_MB               23
1546 #define MICROMIPSOP_MASK_MC             0x7
1547 #define MICROMIPSOP_SH_MC               4
1548 #define MICROMIPSOP_MASK_MD             0x7
1549 #define MICROMIPSOP_SH_MD               7
1550 #define MICROMIPSOP_MASK_ME             0x7
1551 #define MICROMIPSOP_SH_ME               1
1552 #define MICROMIPSOP_MASK_MF             0x7
1553 #define MICROMIPSOP_SH_MF               3
1554 #define MICROMIPSOP_MASK_MG             0x7
1555 #define MICROMIPSOP_SH_MG               0
1556 #define MICROMIPSOP_MASK_MH             0x7
1557 #define MICROMIPSOP_SH_MH               7
1558 #define MICROMIPSOP_MASK_MJ             0x1f
1559 #define MICROMIPSOP_SH_MJ               0
1560 #define MICROMIPSOP_MASK_ML             0x7
1561 #define MICROMIPSOP_SH_ML               4
1562 #define MICROMIPSOP_MASK_MM             0x7
1563 #define MICROMIPSOP_SH_MM               1
1564 #define MICROMIPSOP_MASK_MN             0x7
1565 #define MICROMIPSOP_SH_MN               4
1566 #define MICROMIPSOP_MASK_MP             0x1f
1567 #define MICROMIPSOP_SH_MP               5
1568 #define MICROMIPSOP_MASK_MQ             0x7
1569 #define MICROMIPSOP_SH_MQ               7
1570
1571 #define MICROMIPSOP_MASK_IMMA           0x7f
1572 #define MICROMIPSOP_SH_IMMA             0
1573 #define MICROMIPSOP_MASK_IMMB           0x7
1574 #define MICROMIPSOP_SH_IMMB             1
1575 #define MICROMIPSOP_MASK_IMMC           0xf
1576 #define MICROMIPSOP_SH_IMMC             0
1577 #define MICROMIPSOP_MASK_IMMD           0x3ff
1578 #define MICROMIPSOP_SH_IMMD             0
1579 #define MICROMIPSOP_MASK_IMME           0x7f
1580 #define MICROMIPSOP_SH_IMME             0
1581 #define MICROMIPSOP_MASK_IMMF           0xf
1582 #define MICROMIPSOP_SH_IMMF             0
1583 #define MICROMIPSOP_MASK_IMMG           0xf
1584 #define MICROMIPSOP_SH_IMMG             0
1585 #define MICROMIPSOP_MASK_IMMH           0xf
1586 #define MICROMIPSOP_SH_IMMH             0
1587 #define MICROMIPSOP_MASK_IMMI           0x7f
1588 #define MICROMIPSOP_SH_IMMI             0
1589 #define MICROMIPSOP_MASK_IMMJ           0xf
1590 #define MICROMIPSOP_SH_IMMJ             0
1591 #define MICROMIPSOP_MASK_IMML           0xf
1592 #define MICROMIPSOP_SH_IMML             0
1593 #define MICROMIPSOP_MASK_IMMM           0x7
1594 #define MICROMIPSOP_SH_IMMM             1
1595 #define MICROMIPSOP_MASK_IMMN           0x3
1596 #define MICROMIPSOP_SH_IMMN             4
1597 #define MICROMIPSOP_MASK_IMMO           0xf
1598 #define MICROMIPSOP_SH_IMMO             0
1599 #define MICROMIPSOP_MASK_IMMP           0x1f
1600 #define MICROMIPSOP_SH_IMMP             0
1601 #define MICROMIPSOP_MASK_IMMQ           0x7fffff
1602 #define MICROMIPSOP_SH_IMMQ             0
1603 #define MICROMIPSOP_MASK_IMMU           0x1f
1604 #define MICROMIPSOP_SH_IMMU             0
1605 #define MICROMIPSOP_MASK_IMMW           0x3f
1606 #define MICROMIPSOP_SH_IMMW             1
1607 #define MICROMIPSOP_MASK_IMMX           0xf
1608 #define MICROMIPSOP_SH_IMMX             1
1609 #define MICROMIPSOP_MASK_IMMY           0x1ff
1610 #define MICROMIPSOP_SH_IMMY             1
1611
1612 /* MIPS DSP ASE */
1613 #define MICROMIPSOP_MASK_DSPACC         0x3
1614 #define MICROMIPSOP_SH_DSPACC           14
1615 #define MICROMIPSOP_MASK_DSPSFT         0x3f
1616 #define MICROMIPSOP_SH_DSPSFT           16
1617 #define MICROMIPSOP_MASK_SA3            0x7
1618 #define MICROMIPSOP_SH_SA3              13
1619 #define MICROMIPSOP_MASK_SA4            0xf
1620 #define MICROMIPSOP_SH_SA4              12
1621 #define MICROMIPSOP_MASK_IMM8           0xff
1622 #define MICROMIPSOP_SH_IMM8             13
1623 #define MICROMIPSOP_MASK_IMM10          0x3ff
1624 #define MICROMIPSOP_SH_IMM10            16
1625 #define MICROMIPSOP_MASK_WRDSP          0x3f
1626 #define MICROMIPSOP_SH_WRDSP            14
1627 #define MICROMIPSOP_MASK_BP             0x3
1628 #define MICROMIPSOP_SH_BP               14
1629
1630 /* Placeholders for fields that only exist in the traditional 32-bit
1631    instruction encoding; see the comment above for details.  */
1632 #define MICROMIPSOP_MASK_CODE20         0
1633 #define MICROMIPSOP_SH_CODE20           0
1634 #define MICROMIPSOP_MASK_PERFREG        0
1635 #define MICROMIPSOP_SH_PERFREG          0
1636 #define MICROMIPSOP_MASK_CODE19         0
1637 #define MICROMIPSOP_SH_CODE19           0
1638 #define MICROMIPSOP_MASK_ALN            0
1639 #define MICROMIPSOP_SH_ALN              0
1640 #define MICROMIPSOP_MASK_VECBYTE        0
1641 #define MICROMIPSOP_SH_VECBYTE          0
1642 #define MICROMIPSOP_MASK_VECALIGN       0
1643 #define MICROMIPSOP_SH_VECALIGN         0
1644 #define MICROMIPSOP_MASK_DSPACC_S       0
1645 #define MICROMIPSOP_SH_DSPACC_S         0
1646 #define MICROMIPSOP_MASK_DSPSFT_7       0
1647 #define MICROMIPSOP_SH_DSPSFT_7         0
1648 #define MICROMIPSOP_MASK_RDDSP          0
1649 #define MICROMIPSOP_SH_RDDSP            0
1650 #define MICROMIPSOP_MASK_MT_U           0
1651 #define MICROMIPSOP_SH_MT_U             0
1652 #define MICROMIPSOP_MASK_MT_H           0
1653 #define MICROMIPSOP_SH_MT_H             0
1654 #define MICROMIPSOP_MASK_MTACC_T        0
1655 #define MICROMIPSOP_SH_MTACC_T          0
1656 #define MICROMIPSOP_MASK_MTACC_D        0
1657 #define MICROMIPSOP_SH_MTACC_D          0
1658 #define MICROMIPSOP_MASK_BBITIND        0
1659 #define MICROMIPSOP_SH_BBITIND          0
1660 #define MICROMIPSOP_MASK_CINSPOS        0
1661 #define MICROMIPSOP_SH_CINSPOS          0
1662 #define MICROMIPSOP_MASK_CINSLM1        0
1663 #define MICROMIPSOP_SH_CINSLM1          0
1664 #define MICROMIPSOP_MASK_SEQI           0
1665 #define MICROMIPSOP_SH_SEQI             0
1666 #define MICROMIPSOP_SH_OFFSET_A         0
1667 #define MICROMIPSOP_MASK_OFFSET_A       0
1668 #define MICROMIPSOP_SH_OFFSET_B         0
1669 #define MICROMIPSOP_MASK_OFFSET_B       0
1670 #define MICROMIPSOP_SH_OFFSET_C         0
1671 #define MICROMIPSOP_MASK_OFFSET_C       0
1672 #define MICROMIPSOP_SH_RZ               0
1673 #define MICROMIPSOP_MASK_RZ             0
1674 #define MICROMIPSOP_SH_FZ               0
1675 #define MICROMIPSOP_MASK_FZ             0
1676
1677 /* microMIPS Enhanced VA Scheme */
1678 #define MICROMIPSOP_SH_EVAOFFSET        0
1679 #define MICROMIPSOP_MASK_EVAOFFSET      0x1ff
1680
1681 /* These are the characters which may appears in the args field of a microMIPS
1682    instruction.  They appear in the order in which the fields appear
1683    when the instruction is used.  Commas and parentheses in the args
1684    string are ignored when assembling, and written into the output
1685    when disassembling.
1686
1687    The followings are for 16-bit microMIPS instructions.
1688
1689    "ma" must be $28
1690    "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1691         The same register used as both source and target.
1692    "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1693    "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1694         The same register used as both source and target.
1695    "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1696    "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1697    "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
1698    "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1699    "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1700    "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1701    "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1702    "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1703    "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1704    "mr" must be program counter
1705    "ms" must be $29
1706    "mt" must be the same as the previous register
1707    "mx" must be the same as the destination register
1708    "my" must be $31
1709    "mz" must be $0
1710
1711    "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1712    "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1713    "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1714         32768, 65535) (MICROMIPSOP_*_IMMC)
1715    "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1716    "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1717    "mF" 4-bit immediate (0 .. 15)  (MICROMIPSOP_*_IMMF)
1718    "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1719    "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1720    "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1721    "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1722    "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1723    "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1724    "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1725    "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1726    "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1727    "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1728    "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1729    "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1730    "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1731    "mZ" must be zero
1732
1733    In most cases 32-bit microMIPS instructions use the same characters
1734    as MIPS (with ADDIUPC being a notable exception, but there are some
1735    others too).
1736
1737    "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1738    "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
1739    "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1740    ">" shift amount between 32 and 63, stored after subtracting 32
1741        (MICROMIPSOP_*_SHAMT)
1742    "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1743    "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1744    "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1745    "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1746    "+i" likewise, but flips bit 0
1747    "b" 5-bit base register (MICROMIPSOP_*_RS)
1748    "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1749    "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1750    "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1751    "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1752    "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1753    "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1754    "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1755    "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1756    "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1757    "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1758    "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1759    "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1760    "t" 5-bit target register (MICROMIPSOP_*_RT)
1761    "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1762    "v" 5-bit same register used as both source and destination
1763        (MICROMIPSOP_*_RS)
1764    "w" 5-bit same register used as both target and destination
1765        (MICROMIPSOP_*_RT)
1766    "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1767    "z" must be zero register
1768    "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1769    "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1770    "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1771
1772    "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1773         LSB (MICROMIPSOP_*_EXTLSB).
1774         Enforces: 0 <= pos < 32.
1775    "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1776         Requires that "+A" or "+E" occur first to set position.
1777         Enforces: 0 < (pos+size) <= 32.
1778    "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1779         Requires that "+A" or "+E" occur first to set position.
1780         Enforces: 0 < (pos+size) <= 32.
1781         (Also used by DEXT w/ different limits, but limits for
1782         that are checked by the M_DEXT macro.)
1783    "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1784         Enforces: 32 <= pos < 64.
1785    "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1786         Requires that "+A" or "+E" occur first to set position.
1787         Enforces: 32 < (pos+size) <= 64.
1788    "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1789         Requires that "+A" or "+E" occur first to set position.
1790         Enforces: 32 < (pos+size) <= 64.
1791    "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1792         Requires that "+A" or "+E" occur first to set position.
1793         Enforces: 32 < (pos+size) <= 64.
1794
1795    PC-relative addition (ADDIUPC) instruction:
1796    "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1797    "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1798
1799    Floating point instructions:
1800    "D" 5-bit destination register (MICROMIPSOP_*_FD)
1801    "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1802    "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1803    "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1804    "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1805    "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1806    "V" 5-bit same register used as floating source and destination or target
1807        (MICROMIPSOP_*_FS)
1808
1809    Coprocessor instructions:
1810    "E" 5-bit target register (MICROMIPSOP_*_RT)
1811    "G" 5-bit source register (MICROMIPSOP_*_RS)
1812    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1813
1814    Macro instructions:
1815    "A" general 32 bit expression
1816    "I" 32-bit immediate (value placed in imm_expr).
1817    "+I" 32-bit immediate (value placed in imm2_expr).
1818    "F" 64-bit floating point constant in .rdata
1819    "L" 64-bit floating point constant in .lit8
1820    "f" 32-bit floating point constant
1821    "l" 32-bit floating point constant in .lit4
1822
1823    DSP ASE usage:
1824    "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
1825    "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
1826    "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
1827    "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
1828    "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
1829    "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
1830    "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
1831    "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
1832    "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
1833    "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
1834
1835    microMIPS Enhanced VA Scheme:
1836    "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
1837
1838    Other:
1839    "()" parens surrounding optional value
1840    ","  separates operands
1841    "+"  start of extension sequence
1842    "m"  start of microMIPS extension sequence
1843
1844    Characters used so far, for quick reference when adding more:
1845    "12345678 0"
1846    "<>(),+.@\^|~"
1847    "ABCDEFGHI KLMN   RST V    "
1848    "abcd f hijklmnopqrstuvw yz"
1849
1850    Extension character sequences used so far ("+" followed by the
1851    following), for quick reference when adding more:
1852    ""
1853    ""
1854    "ABCEFGHI"
1855    "ij"
1856
1857    Extension character sequences used so far ("m" followed by the
1858    following), for quick reference when adding more:
1859    ""
1860    ""
1861    " BCDEFGHIJ LMNOPQ   U WXYZ"
1862    " bcdefghij lmn pq st   xyz"
1863 */
1864
1865 extern const struct mips_opcode micromips_opcodes[];
1866 extern const int bfd_micromips_num_opcodes;
1867
1868 /* A NOP insn impemented as "or at,at,zero".
1869    Used to implement -mfix-loongson2f.  */
1870 #define LOONGSON2F_NOP_INSN     0x00200825
1871
1872 #endif /* _MIPS_H_ */