include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Contributed by Ralph Campbell and OSF
   5    Commented and modified by Ian Lance Taylor, Cygnus Support
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 GDB, GAS, and the GNU binutils are free software; you can redistribute
  10 them and/or modify them under the terms of the GNU General Public
  11 License as published by the Free Software Foundation; either version
  12 1, or (at your option) any later version.
  13
  14 GDB, GAS, and the GNU binutils are distributed in the hope that they
  15 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  16 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  17 the GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this file; see the file COPYING.  If not, write to the Free
  21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef _MIPS_H_
  24 #define _MIPS_H_
  25
  26 /* These are bit masks and shift counts to use to access the various
  27    fields of an instruction.  To retrieve the X field of an
  28    instruction, use the expression
  29         (i >> OP_SH_X) & OP_MASK_X
  30    To set the same field (to j), use
  31         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  32
  33    Make sure you use fields that are appropriate for the instruction,
  34    of course.
  35
  36    The 'i' format uses OP, RS, RT and IMMEDIATE.
  37
  38    The 'j' format uses OP and TARGET.
  39
  40    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  41
  42    The 'b' format uses OP, RS, RT and DELTA.
  43
  44    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  45
  46    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  47
  48    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  49    breakpoint instruction are not defined; Kane says the breakpoint
  50    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  51    only use ten bits).  An optional two-operand form of break/sdbbp
  52    allows the lower ten bits to be set too, and MIPS32 and later
  53    architectures allow 20 bits to be set with a signal operand
  54    (using CODE20).
  55
  56    The syscall instruction uses CODE20.
  57
  58    The general coprocessor instructions use COPZ.  */
  59
  60 #define OP_MASK_OP              0x3f
  61 #define OP_SH_OP                26
  62 #define OP_MASK_RS              0x1f
  63 #define OP_SH_RS                21
  64 #define OP_MASK_FR              0x1f
  65 #define OP_SH_FR                21
  66 #define OP_MASK_FMT             0x1f
  67 #define OP_SH_FMT               21
  68 #define OP_MASK_BCC             0x7
  69 #define OP_SH_BCC               18
  70 #define OP_MASK_CODE            0x3ff
  71 #define OP_SH_CODE              16
  72 #define OP_MASK_CODE2           0x3ff
  73 #define OP_SH_CODE2             6
  74 #define OP_MASK_RT              0x1f
  75 #define OP_SH_RT                16
  76 #define OP_MASK_FT              0x1f
  77 #define OP_SH_FT                16
  78 #define OP_MASK_CACHE           0x1f
  79 #define OP_SH_CACHE             16
  80 #define OP_MASK_RD              0x1f
  81 #define OP_SH_RD                11
  82 #define OP_MASK_FS              0x1f
  83 #define OP_SH_FS                11
  84 #define OP_MASK_PREFX           0x1f
  85 #define OP_SH_PREFX             11
  86 #define OP_MASK_CCC             0x7
  87 #define OP_SH_CCC               8
  88 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  89 #define OP_SH_CODE20            6
  90 #define OP_MASK_SHAMT           0x1f
  91 #define OP_SH_SHAMT             6
  92 #define OP_MASK_FD              0x1f
  93 #define OP_SH_FD                6
  94 #define OP_MASK_TARGET          0x3ffffff
  95 #define OP_SH_TARGET            0
  96 #define OP_MASK_COPZ            0x1ffffff
  97 #define OP_SH_COPZ              0
  98 #define OP_MASK_IMMEDIATE       0xffff
  99 #define OP_SH_IMMEDIATE         0
 100 #define OP_MASK_DELTA           0xffff
 101 #define OP_SH_DELTA             0
 102 #define OP_MASK_FUNCT           0x3f
 103 #define OP_SH_FUNCT             0
 104 #define OP_MASK_SPEC            0x3f
 105 #define OP_SH_SPEC              0
 106 #define OP_SH_LOCC              8       /* FP condition code.  */
 107 #define OP_SH_HICC              18      /* FP condition code.  */
 108 #define OP_MASK_CC              0x7
 109 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 110 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 111 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 112 #define OP_MASK_COP1SPEC        0xf
 113 #define OP_MASK_COP1SCLR        0x4
 114 #define OP_MASK_COP1CMP         0x3
 115 #define OP_SH_COP1CMP           4
 116 #define OP_SH_FORMAT            21      /* FP short format field.  */
 117 #define OP_MASK_FORMAT          0x7
 118 #define OP_SH_TRUE              16
 119 #define OP_MASK_TRUE            0x1
 120 #define OP_SH_GE                17
 121 #define OP_MASK_GE              0x01
 122 #define OP_SH_UNSIGNED          16
 123 #define OP_MASK_UNSIGNED        0x1
 124 #define OP_SH_HINT              16
 125 #define OP_MASK_HINT            0x1f
 126 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 127 #define OP_MASK_MMI             0x3f
 128 #define OP_SH_MMISUB            6
 129 #define OP_MASK_MMISUB          0x1f
 130 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 131 #define OP_SH_PERFREG           1
 132 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 133 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 134 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 135 #define OP_MASK_CODE19          0x7ffff
 136
 137 /* This structure holds information for a particular instruction.  */
 138
 139 struct mips_opcode
 140 {
 141   /* The name of the instruction.  */
 142   const char *name;
 143   /* A string describing the arguments for this instruction.  */
 144   const char *args;
 145   /* The basic opcode for the instruction.  When assembling, this
 146      opcode is modified by the arguments to produce the actual opcode
 147      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 148   unsigned long match;
 149   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 150      relevant portions of the opcode when disassembling.  If the
 151      actual opcode anded with the match field equals the opcode field,
 152      then we have found the correct instruction.  If pinfo is
 153      INSN_MACRO, then this field is the macro identifier.  */
 154   unsigned long mask;
 155   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 156      of bits describing the instruction, notably any relevant hazard
 157      information.  */
 158   unsigned long pinfo;
 159   /* A collection of bits describing the instruction sets of which this
 160      instruction or macro is a member. */
 161   unsigned long membership;
 162 };
 163
 164 /* These are the characters which may appears in the args field of an
 165    instruction.  They appear in the order in which the fields appear
 166    when the instruction is used.  Commas and parentheses in the args
 167    string are ignored when assembling, and written into the output
 168    when disassembling.
 169
 170    Each of these characters corresponds to a mask field defined above.
 171
 172    "<" 5 bit shift amount (OP_*_SHAMT)
 173    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 174    "a" 26 bit target address (OP_*_TARGET)
 175    "b" 5 bit base register (OP_*_RS)
 176    "c" 10 bit breakpoint code (OP_*_CODE)
 177    "d" 5 bit destination register specifier (OP_*_RD)
 178    "h" 5 bit prefx hint (OP_*_PREFX)
 179    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 180    "j" 16 bit signed immediate (OP_*_DELTA)
 181    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 182    "o" 16 bit signed offset (OP_*_DELTA)
 183    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 184    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 185    "r" 5 bit same register used as both source and target (OP_*_RS)
 186    "s" 5 bit source register specifier (OP_*_RS)
 187    "t" 5 bit target register (OP_*_RT)
 188    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 189    "v" 5 bit same register used as both source and destination (OP_*_RS)
 190    "w" 5 bit same register used as both target and destination (OP_*_RT)
 191    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 192        (used by clo and clz)
 193    "C" 25 bit coprocessor function code (OP_*_COPZ)
 194    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 195    "J" 19 bit wait function code (OP_*_CODE19)
 196    "x" accept and ignore register name
 197    "z" must be zero register
 198
 199    Floating point instructions:
 200    "D" 5 bit destination register (OP_*_FD)
 201    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 202    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 203    "S" 5 bit fs source 1 register (OP_*_FS)
 204    "T" 5 bit ft source 2 register (OP_*_FT)
 205    "R" 5 bit fr source 3 register (OP_*_FR)
 206    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 207    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 208
 209    Coprocessor instructions:
 210    "E" 5 bit target register (OP_*_RT)
 211    "G" 5 bit destination register (OP_*_RD)
 212    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 213    "H" 3 bit sel field (OP_*_SEL)
 214
 215    Macro instructions:
 216    "A" General 32 bit expression
 217    "I" 32 bit immediate
 218    "F" 64 bit floating point constant in .rdata
 219    "L" 64 bit floating point constant in .lit8
 220    "f" 32 bit floating point constant
 221    "l" 32 bit floating point constant in .lit4
 222
 223    Other:
 224    "()" parens surrounding optional value
 225    ","  separates operands
 226
 227    Characters used so far, for quick reference when adding more:
 228    "<>(),"
 229    "ABCDEFGHIJLMNPRSTUVW"
 230    "abcdfhijklopqrstuvwxz"
 231 */
 232
 233 /* These are the bits which may be set in the pinfo field of an
 234    instructions, if it is not equal to INSN_MACRO.  */
 235
 236 /* Modifies the general purpose register in OP_*_RD.  */
 237 #define INSN_WRITE_GPR_D            0x00000001
 238 /* Modifies the general purpose register in OP_*_RT.  */
 239 #define INSN_WRITE_GPR_T            0x00000002
 240 /* Modifies general purpose register 31.  */
 241 #define INSN_WRITE_GPR_31           0x00000004
 242 /* Modifies the floating point register in OP_*_FD.  */
 243 #define INSN_WRITE_FPR_D            0x00000008
 244 /* Modifies the floating point register in OP_*_FS.  */
 245 #define INSN_WRITE_FPR_S            0x00000010
 246 /* Modifies the floating point register in OP_*_FT.  */
 247 #define INSN_WRITE_FPR_T            0x00000020
 248 /* Reads the general purpose register in OP_*_RS.  */
 249 #define INSN_READ_GPR_S             0x00000040
 250 /* Reads the general purpose register in OP_*_RT.  */
 251 #define INSN_READ_GPR_T             0x00000080
 252 /* Reads the floating point register in OP_*_FS.  */
 253 #define INSN_READ_FPR_S             0x00000100
 254 /* Reads the floating point register in OP_*_FT.  */
 255 #define INSN_READ_FPR_T             0x00000200
 256 /* Reads the floating point register in OP_*_FR.  */
 257 #define INSN_READ_FPR_R             0x00000400
 258 /* Modifies coprocessor condition code.  */
 259 #define INSN_WRITE_COND_CODE        0x00000800
 260 /* Reads coprocessor condition code.  */
 261 #define INSN_READ_COND_CODE         0x00001000
 262 /* TLB operation.  */
 263 #define INSN_TLB                    0x00002000
 264 /* Reads coprocessor register other than floating point register.  */
 265 #define INSN_COP                    0x00004000
 266 /* Instruction loads value from memory, requiring delay.  */
 267 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 268 /* Instruction loads value from coprocessor, requiring delay.  */
 269 #define INSN_LOAD_COPROC_DELAY      0x00010000
 270 /* Instruction has unconditional branch delay slot.  */
 271 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 272 /* Instruction has conditional branch delay slot.  */
 273 #define INSN_COND_BRANCH_DELAY      0x00040000
 274 /* Conditional branch likely: if branch not taken, insn nullified.  */
 275 #define INSN_COND_BRANCH_LIKELY     0x00080000
 276 /* Moves to coprocessor register, requiring delay.  */
 277 #define INSN_COPROC_MOVE_DELAY      0x00100000
 278 /* Loads coprocessor register from memory, requiring delay.  */
 279 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 280 /* Reads the HI register.  */
 281 #define INSN_READ_HI                0x00400000
 282 /* Reads the LO register.  */
 283 #define INSN_READ_LO                0x00800000
 284 /* Modifies the HI register.  */
 285 #define INSN_WRITE_HI               0x01000000
 286 /* Modifies the LO register.  */
 287 #define INSN_WRITE_LO               0x02000000
 288 /* Takes a trap (easier to keep out of delay slot).  */
 289 #define INSN_TRAP                   0x04000000
 290 /* Instruction stores value into memory.  */
 291 #define INSN_STORE_MEMORY           0x08000000
 292 /* Instruction uses single precision floating point.  */
 293 #define FP_S                        0x10000000
 294 /* Instruction uses double precision floating point.  */
 295 #define FP_D                        0x20000000
 296 /* Instruction is part of the tx39's integer multiply family.    */
 297 #define INSN_MULT                   0x40000000
 298 /* Instruction synchronize shared memory.  */
 299 #define INSN_SYNC                   0x80000000
 300
 301 /* Instruction is actually a macro.  It should be ignored by the
 302    disassembler, and requires special treatment by the assembler.  */
 303 #define INSN_MACRO                  0xffffffff
 304
 305 /* Masks used to mark instructions to indicate which MIPS ISA level
 306    they were introduced in.  ISAs, as defined below, are logical
 307    ORs of these bits, indicatingthat they support the instructions
 308    defined at the given level.  */
 309
 310 #define INSN_ISA_MASK             0x00000fff
 311 #define INSN_ISA1                 0x00000010
 312 #define INSN_ISA2                 0x00000020
 313 #define INSN_ISA3                 0x00000040
 314 #define INSN_ISA4                 0x00000080
 315 #define INSN_ISA5                 0x00000100
 316 #define INSN_ISA32                0x00000200
 317 #define INSN_ISA64                0x00000400
 318
 319 /* Chip specific instructions.  These are bitmasks.  */
 320
 321 /* MIPS R4650 instruction.  */
 322 #define INSN_4650                 0x00010000
 323 /* LSI R4010 instruction.  */
 324 #define INSN_4010                 0x00020000
 325 /* NEC VR4100 instruction.  */
 326 #define INSN_4100                 0x00040000
 327 /* Toshiba R3900 instruction.  */
 328 #define INSN_3900                 0x00080000
 329 /* MIPS R10000 instruction.  */
 330 #define INSN_10000                0x00100000
 331
 332 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 333
 334 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 335 #define       ISA_MIPS1       (INSN_ISA1)
 336 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 337 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 338 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 339 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 340 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 341 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 342
 343 /* CPU defines, use instead of hardcoding processor number. Keep this
 344    in sync with bfd/archures.c in order for machine selection to work.  */
 345 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 346 #define CPU_R2000       2000
 347 #define CPU_R3000       3000
 348 #define CPU_R3900       3900
 349 #define CPU_R4000       4000
 350 #define CPU_R4010       4010
 351 #define CPU_VR4100      4100
 352 #define CPU_R4111       4111
 353 #define CPU_R4300       4300
 354 #define CPU_R4400       4400
 355 #define CPU_R4600       4600
 356 #define CPU_R4650       4650
 357 #define CPU_R5000       5000
 358 #define CPU_R6000       6000
 359 #define CPU_R8000       8000
 360 #define CPU_R10000      10000
 361 #define CPU_R12000      12000
 362 #define CPU_MIPS16      16
 363 #define CPU_MIPS32      32
 364 #define CPU_MIPS5       5
 365 #define CPU_MIPS64      64
 366 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 367
 368 /* Test for membership in an ISA including chip specific ISAs.
 369    INSN is pointer to an element of the opcode table; ISA is the
 370    specified ISA to test against; and CPU is the CPU specific ISA
 371    to test, or zero if no CPU specific ISA test is desired.  */
 372
 373 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 374     (((insn)->membership & isa) != 0                                    \
 375      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 376      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 377      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)                        \
 378          && ((insn)->membership & INSN_4100) != 0)                      \
 379      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 380      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 381          && ((insn)->membership & INSN_10000) != 0))
 382
 383 /* This is a list of macro expanded instructions.
 384
 385    _I appended means immediate
 386    _A appended means address
 387    _AB appended means address with base register
 388    _D appended means 64 bit floating point constant
 389    _S appended means 32 bit floating point constant.  */
 390
 391 enum
 392 {
 393   M_ABS,
 394   M_ADD_I,
 395   M_ADDU_I,
 396   M_AND_I,
 397   M_BEQ,
 398   M_BEQ_I,
 399   M_BEQL_I,
 400   M_BGE,
 401   M_BGEL,
 402   M_BGE_I,
 403   M_BGEL_I,
 404   M_BGEU,
 405   M_BGEUL,
 406   M_BGEU_I,
 407   M_BGEUL_I,
 408   M_BGT,
 409   M_BGTL,
 410   M_BGT_I,
 411   M_BGTL_I,
 412   M_BGTU,
 413   M_BGTUL,
 414   M_BGTU_I,
 415   M_BGTUL_I,
 416   M_BLE,
 417   M_BLEL,
 418   M_BLE_I,
 419   M_BLEL_I,
 420   M_BLEU,
 421   M_BLEUL,
 422   M_BLEU_I,
 423   M_BLEUL_I,
 424   M_BLT,
 425   M_BLTL,
 426   M_BLT_I,
 427   M_BLTL_I,
 428   M_BLTU,
 429   M_BLTUL,
 430   M_BLTU_I,
 431   M_BLTUL_I,
 432   M_BNE,
 433   M_BNE_I,
 434   M_BNEL_I,
 435   M_DABS,
 436   M_DADD_I,
 437   M_DADDU_I,
 438   M_DDIV_3,
 439   M_DDIV_3I,
 440   M_DDIVU_3,
 441   M_DDIVU_3I,
 442   M_DIV_3,
 443   M_DIV_3I,
 444   M_DIVU_3,
 445   M_DIVU_3I,
 446   M_DLA_AB,
 447   M_DLI,
 448   M_DMUL,
 449   M_DMUL_I,
 450   M_DMULO,
 451   M_DMULO_I,
 452   M_DMULOU,
 453   M_DMULOU_I,
 454   M_DREM_3,
 455   M_DREM_3I,
 456   M_DREMU_3,
 457   M_DREMU_3I,
 458   M_DSUB_I,
 459   M_DSUBU_I,
 460   M_DSUBU_I_2,
 461   M_J_A,
 462   M_JAL_1,
 463   M_JAL_2,
 464   M_JAL_A,
 465   M_L_DOB,
 466   M_L_DAB,
 467   M_LA_AB,
 468   M_LB_A,
 469   M_LB_AB,
 470   M_LBU_A,
 471   M_LBU_AB,
 472   M_LD_A,
 473   M_LD_OB,
 474   M_LD_AB,
 475   M_LDC1_AB,
 476   M_LDC2_AB,
 477   M_LDC3_AB,
 478   M_LDL_AB,
 479   M_LDR_AB,
 480   M_LH_A,
 481   M_LH_AB,
 482   M_LHU_A,
 483   M_LHU_AB,
 484   M_LI,
 485   M_LI_D,
 486   M_LI_DD,
 487   M_LI_S,
 488   M_LI_SS,
 489   M_LL_AB,
 490   M_LLD_AB,
 491   M_LS_A,
 492   M_LW_A,
 493   M_LW_AB,
 494   M_LWC0_A,
 495   M_LWC0_AB,
 496   M_LWC1_A,
 497   M_LWC1_AB,
 498   M_LWC2_A,
 499   M_LWC2_AB,
 500   M_LWC3_A,
 501   M_LWC3_AB,
 502   M_LWL_A,
 503   M_LWL_AB,
 504   M_LWR_A,
 505   M_LWR_AB,
 506   M_LWU_AB,
 507   M_MOVE,
 508   M_MUL,
 509   M_MUL_I,
 510   M_MULO,
 511   M_MULO_I,
 512   M_MULOU,
 513   M_MULOU_I,
 514   M_NOR_I,
 515   M_OR_I,
 516   M_REM_3,
 517   M_REM_3I,
 518   M_REMU_3,
 519   M_REMU_3I,
 520   M_ROL,
 521   M_ROL_I,
 522   M_ROR,
 523   M_ROR_I,
 524   M_S_DA,
 525   M_S_DOB,
 526   M_S_DAB,
 527   M_S_S,
 528   M_SC_AB,
 529   M_SCD_AB,
 530   M_SD_A,
 531   M_SD_OB,
 532   M_SD_AB,
 533   M_SDC1_AB,
 534   M_SDC2_AB,
 535   M_SDC3_AB,
 536   M_SDL_AB,
 537   M_SDR_AB,
 538   M_SEQ,
 539   M_SEQ_I,
 540   M_SGE,
 541   M_SGE_I,
 542   M_SGEU,
 543   M_SGEU_I,
 544   M_SGT,
 545   M_SGT_I,
 546   M_SGTU,
 547   M_SGTU_I,
 548   M_SLE,
 549   M_SLE_I,
 550   M_SLEU,
 551   M_SLEU_I,
 552   M_SLT_I,
 553   M_SLTU_I,
 554   M_SNE,
 555   M_SNE_I,
 556   M_SB_A,
 557   M_SB_AB,
 558   M_SH_A,
 559   M_SH_AB,
 560   M_SW_A,
 561   M_SW_AB,
 562   M_SWC0_A,
 563   M_SWC0_AB,
 564   M_SWC1_A,
 565   M_SWC1_AB,
 566   M_SWC2_A,
 567   M_SWC2_AB,
 568   M_SWC3_A,
 569   M_SWC3_AB,
 570   M_SWL_A,
 571   M_SWL_AB,
 572   M_SWR_A,
 573   M_SWR_AB,
 574   M_SUB_I,
 575   M_SUBU_I,
 576   M_SUBU_I_2,
 577   M_TEQ_I,
 578   M_TGE_I,
 579   M_TGEU_I,
 580   M_TLT_I,
 581   M_TLTU_I,
 582   M_TNE_I,
 583   M_TRUNCWD,
 584   M_TRUNCWS,
 585   M_ULD,
 586   M_ULD_A,
 587   M_ULH,
 588   M_ULH_A,
 589   M_ULHU,
 590   M_ULHU_A,
 591   M_ULW,
 592   M_ULW_A,
 593   M_USH,
 594   M_USH_A,
 595   M_USW,
 596   M_USW_A,
 597   M_USD,
 598   M_USD_A,
 599   M_XOR_I,
 600   M_COP0,
 601   M_COP1,
 602   M_COP2,
 603   M_COP3,
 604   M_NUM_MACROS
 605 };
 606
 607
 608 /* The order of overloaded instructions matters.  Label arguments and
 609    register arguments look the same. Instructions that can have either
 610    for arguments must apear in the correct order in this table for the
 611    assembler to pick the right one. In other words, entries with
 612    immediate operands must apear after the same instruction with
 613    registers.
 614
 615    Many instructions are short hand for other instructions (i.e., The
 616    jal <register> instruction is short for jalr <register>).  */
 617
 618 extern const struct mips_opcode mips_builtin_opcodes[];
 619 extern const int bfd_mips_num_builtin_opcodes;
 620 extern struct mips_opcode *mips_opcodes;
 621 extern int bfd_mips_num_opcodes;
 622 #define NUMOPCODES bfd_mips_num_opcodes
 623
 624 \f
 625 /* The rest of this file adds definitions for the mips16 TinyRISC
 626    processor.  */
 627
 628 /* These are the bitmasks and shift counts used for the different
 629    fields in the instruction formats.  Other than OP, no masks are
 630    provided for the fixed portions of an instruction, since they are
 631    not needed.
 632
 633    The I format uses IMM11.
 634
 635    The RI format uses RX and IMM8.
 636
 637    The RR format uses RX, and RY.
 638
 639    The RRI format uses RX, RY, and IMM5.
 640
 641    The RRR format uses RX, RY, and RZ.
 642
 643    The RRI_A format uses RX, RY, and IMM4.
 644
 645    The SHIFT format uses RX, RY, and SHAMT.
 646
 647    The I8 format uses IMM8.
 648
 649    The I8_MOVR32 format uses RY and REGR32.
 650
 651    The IR_MOV32R format uses REG32R and MOV32Z.
 652
 653    The I64 format uses IMM8.
 654
 655    The RI64 format uses RY and IMM5.
 656    */
 657
 658 #define MIPS16OP_MASK_OP        0x1f
 659 #define MIPS16OP_SH_OP          11
 660 #define MIPS16OP_MASK_IMM11     0x7ff
 661 #define MIPS16OP_SH_IMM11       0
 662 #define MIPS16OP_MASK_RX        0x7
 663 #define MIPS16OP_SH_RX          8
 664 #define MIPS16OP_MASK_IMM8      0xff
 665 #define MIPS16OP_SH_IMM8        0
 666 #define MIPS16OP_MASK_RY        0x7
 667 #define MIPS16OP_SH_RY          5
 668 #define MIPS16OP_MASK_IMM5      0x1f
 669 #define MIPS16OP_SH_IMM5        0
 670 #define MIPS16OP_MASK_RZ        0x7
 671 #define MIPS16OP_SH_RZ          2
 672 #define MIPS16OP_MASK_IMM4      0xf
 673 #define MIPS16OP_SH_IMM4        0
 674 #define MIPS16OP_MASK_REGR32    0x1f
 675 #define MIPS16OP_SH_REGR32      0
 676 #define MIPS16OP_MASK_REG32R    0x1f
 677 #define MIPS16OP_SH_REG32R      3
 678 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 679 #define MIPS16OP_MASK_MOVE32Z   0x7
 680 #define MIPS16OP_SH_MOVE32Z     0
 681 #define MIPS16OP_MASK_IMM6      0x3f
 682 #define MIPS16OP_SH_IMM6        5
 683
 684 /* These are the characters which may appears in the args field of an
 685    instruction.  They appear in the order in which the fields appear
 686    when the instruction is used.  Commas and parentheses in the args
 687    string are ignored when assembling, and written into the output
 688    when disassembling.
 689
 690    "y" 3 bit register (MIPS16OP_*_RY)
 691    "x" 3 bit register (MIPS16OP_*_RX)
 692    "z" 3 bit register (MIPS16OP_*_RZ)
 693    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 694    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 695    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 696    "0" zero register ($0)
 697    "S" stack pointer ($sp or $29)
 698    "P" program counter
 699    "R" return address register ($ra or $31)
 700    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 701    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 702    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 703    "a" 26 bit jump address
 704    "e" 11 bit extension value
 705    "l" register list for entry instruction
 706    "L" register list for exit instruction
 707
 708    The remaining codes may be extended.  Except as otherwise noted,
 709    the full extended operand is a 16 bit signed value.
 710    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 711    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 712    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 713    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 714    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 715    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 716    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 717    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 718    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 719    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 720    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 721    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 722    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 723    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 724    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 725    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 726    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 727    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 728    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 729    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
 730    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
 731    */
 732
 733 /* For the mips16, we use the same opcode table format and a few of
 734    the same flags.  However, most of the flags are different.  */
 735
 736 /* Modifies the register in MIPS16OP_*_RX.  */
 737 #define MIPS16_INSN_WRITE_X                 0x00000001
 738 /* Modifies the register in MIPS16OP_*_RY.  */
 739 #define MIPS16_INSN_WRITE_Y                 0x00000002
 740 /* Modifies the register in MIPS16OP_*_RZ.  */
 741 #define MIPS16_INSN_WRITE_Z                 0x00000004
 742 /* Modifies the T ($24) register.  */
 743 #define MIPS16_INSN_WRITE_T                 0x00000008
 744 /* Modifies the SP ($29) register.  */
 745 #define MIPS16_INSN_WRITE_SP                0x00000010
 746 /* Modifies the RA ($31) register.  */
 747 #define MIPS16_INSN_WRITE_31                0x00000020
 748 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
 749 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
 750 /* Reads the register in MIPS16OP_*_RX.  */
 751 #define MIPS16_INSN_READ_X                  0x00000080
 752 /* Reads the register in MIPS16OP_*_RY.  */
 753 #define MIPS16_INSN_READ_Y                  0x00000100
 754 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
 755 #define MIPS16_INSN_READ_Z                  0x00000200
 756 /* Reads the T ($24) register.  */
 757 #define MIPS16_INSN_READ_T                  0x00000400
 758 /* Reads the SP ($29) register.  */
 759 #define MIPS16_INSN_READ_SP                 0x00000800
 760 /* Reads the RA ($31) register.  */
 761 #define MIPS16_INSN_READ_31                 0x00001000
 762 /* Reads the program counter.  */
 763 #define MIPS16_INSN_READ_PC                 0x00002000
 764 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 765 #define MIPS16_INSN_READ_GPR_X              0x00004000
 766 /* Is a branch insn. */
 767 #define MIPS16_INSN_BRANCH                  0x00010000
 768
 769 /* The following flags have the same value for the mips16 opcode
 770    table:
 771    INSN_UNCOND_BRANCH_DELAY
 772    INSN_COND_BRANCH_DELAY
 773    INSN_COND_BRANCH_LIKELY (never used)
 774    INSN_READ_HI
 775    INSN_READ_LO
 776    INSN_WRITE_HI
 777    INSN_WRITE_LO
 778    INSN_TRAP
 779    INSN_ISA3
 780    */
 781
 782 extern const struct mips_opcode mips16_opcodes[];
 783 extern const int bfd_mips16_num_opcodes;
 784
 785 #endif /* _MIPS_H_ */