include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef _MIPS_H_
  23 #define _MIPS_H_
  24
  25 /* These are bit masks and shift counts to use to access the various
  26    fields of an instruction.  To retrieve the X field of an
  27    instruction, use the expression
  28         (i >> OP_SH_X) & OP_MASK_X
  29    To set the same field (to j), use
  30         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  31
  32    Make sure you use fields that are appropriate for the instruction,
  33    of course.
  34
  35    The 'i' format uses OP, RS, RT and IMMEDIATE.
  36
  37    The 'j' format uses OP and TARGET.
  38
  39    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  40
  41    The 'b' format uses OP, RS, RT and DELTA.
  42
  43    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  44
  45    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  46
  47    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  48    breakpoint instruction are not defined; Kane says the breakpoint
  49    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  50    only use ten bits).
  51
  52    The syscall instruction uses SYSCALL.
  53
  54    The general coprocessor instructions use COPZ.  */
  55
  56 #define OP_MASK_OP              0x3f
  57 #define OP_SH_OP                26
  58 #define OP_MASK_RS              0x1f
  59 #define OP_SH_RS                21
  60 #define OP_MASK_FR              0x1f
  61 #define OP_SH_FR                21
  62 #define OP_MASK_FMT             0x1f
  63 #define OP_SH_FMT               21
  64 #define OP_MASK_BCC             0x7
  65 #define OP_SH_BCC               18
  66 #define OP_MASK_CODE            0x3ff
  67 #define OP_SH_CODE              16
  68 #define OP_MASK_RT              0x1f
  69 #define OP_SH_RT                16
  70 #define OP_MASK_FT              0x1f
  71 #define OP_SH_FT                16
  72 #define OP_MASK_CACHE           0x1f
  73 #define OP_SH_CACHE             16
  74 #define OP_MASK_RD              0x1f
  75 #define OP_SH_RD                11
  76 #define OP_MASK_FS              0x1f
  77 #define OP_SH_FS                11
  78 #define OP_MASK_PREFX           0x1f
  79 #define OP_SH_PREFX             11
  80 #define OP_MASK_CCC             0x7
  81 #define OP_SH_CCC               8
  82 #define OP_MASK_SYSCALL         0xfffff
  83 #define OP_SH_SYSCALL           6
  84 #define OP_MASK_SHAMT           0x1f
  85 #define OP_SH_SHAMT             6
  86 #define OP_MASK_FD              0x1f
  87 #define OP_SH_FD                6
  88 #define OP_MASK_TARGET          0x3ffffff
  89 #define OP_SH_TARGET            0
  90 #define OP_MASK_COPZ            0x1ffffff
  91 #define OP_SH_COPZ              0
  92 #define OP_MASK_IMMEDIATE       0xffff
  93 #define OP_SH_IMMEDIATE         0
  94 #define OP_MASK_DELTA           0xffff
  95 #define OP_SH_DELTA             0
  96 #define OP_MASK_FUNCT           0x3f
  97 #define OP_SH_FUNCT             0
  98 #define OP_MASK_SPEC            0x3f
  99 #define OP_SH_SPEC              0
 100 #define OP_SH_LOCC              8       /* FP condition code */
 101 #define OP_SH_HICC              18      /* FP condition code */
 102 #define OP_MASK_CC              0x7
 103 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding */
 104 #define OP_MASK_COP1NORM        0x1     /* a single bit */
 105 #define OP_SH_COP1SPEC          21      /* COP1 encodings */
 106 #define OP_MASK_COP1SPEC        0xf
 107 #define OP_MASK_COP1SCLR        0x4
 108 #define OP_MASK_COP1CMP         0x3
 109 #define OP_SH_COP1CMP           4
 110 #define OP_SH_FORMAT            21      /* FP short format field */
 111 #define OP_MASK_FORMAT          0x7
 112 #define OP_SH_TRUE              16
 113 #define OP_MASK_TRUE            0x1
 114 #define OP_SH_GE                17
 115 #define OP_MASK_GE              0x01
 116 #define OP_SH_UNSIGNED          16
 117 #define OP_MASK_UNSIGNED        0x1
 118 #define OP_SH_HINT              16
 119 #define OP_MASK_HINT            0x1f
 120 #define OP_SH_MMI               0       /* Multimedia (parallel) op */
 121 #define OP_MASK_MMI             0x3f
 122 #define OP_SH_MMISUB            6
 123 #define OP_MASK_MMISUB          0x1f
 124 /* start-sanitize-vr5400 */
 125 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring */
 126 #define OP_SH_PERFREG           1
 127 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 128                                            but 0x8-0xf don't select bytes.  */
 129 #define OP_SH_VECBYTE           22
 130 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 131 #define OP_SH_VECALIGN          21
 132 /* end-sanitize-vr5400 */
 133
 134 /* This structure holds information for a particular instruction.  */
 135
 136 struct mips_opcode
 137 {
 138   /* The name of the instruction.  */
 139   const char *name;
 140   /* A string describing the arguments for this instruction.  */
 141   const char *args;
 142   /* The basic opcode for the instruction.  When assembling, this
 143      opcode is modified by the arguments to produce the actual opcode
 144      that is used.  If pinfo is INSN_MACRO, then this is instead the
 145      ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
 146      etc.).  */
 147   unsigned long match;
 148   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 149      relevant portions of the opcode when disassembling.  If the
 150      actual opcode anded with the match field equals the opcode field,
 151      then we have found the correct instruction.  If pinfo is
 152      INSN_MACRO, then this field is the macro identifier.  */
 153   unsigned long mask;
 154   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 155      of bits describing the instruction, notably any relevant hazard
 156      information.  */
 157   unsigned long pinfo;
 158   /* A collection of bits describing the instruction sets of which this
 159      instruction is a member. */
 160   unsigned long membership;
 161 };
 162
 163 /* These are the characters which may appears in the args field of an
 164    instruction.  They appear in the order in which the fields appear
 165    when the instruction is used.  Commas and parentheses in the args
 166    string are ignored when assembling, and written into the output
 167    when disassembling.
 168
 169    Each of these characters corresponds to a mask field defined above.
 170
 171    "<" 5 bit shift amount (OP_*_SHAMT)
 172    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 173    "a" 26 bit target address (OP_*_TARGET)
 174    "b" 5 bit base register (OP_*_RS)
 175    "c" 10 bit breakpoint code (OP_*_CODE)
 176    "d" 5 bit destination register specifier (OP_*_RD)
 177    "h" 5 bit prefx hint (OP_*_PREFX)
 178    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 179    "j" 16 bit signed immediate (OP_*_DELTA)
 180    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 181 start-sanitize-vr5400
 182              also vr5400 vector ops immediate operand
 183 end-sanitize-vr5400
 184    "o" 16 bit signed offset (OP_*_DELTA)
 185    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 186    "r" 5 bit same register used as both source and target (OP_*_RS)
 187    "s" 5 bit source register specifier (OP_*_RS)
 188    "t" 5 bit target register (OP_*_RT)
 189    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 190    "v" 5 bit same register used as both source and destination (OP_*_RS)
 191    "w" 5 bit same register used as both target and destination (OP_*_RT)
 192    "C" 25 bit coprocessor function code (OP_*_COPZ)
 193    "B" 20 bit syscall function code (OP_*_SYSCALL)
 194    "x" accept and ignore register name
 195    "z" must be zero register
 196
 197    Floating point instructions:
 198    "D" 5 bit destination register (OP_*_FD)
 199    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 200    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 201    "S" 5 bit fs source 1 register (OP_*_FS)
 202    "T" 5 bit ft source 2 register (OP_*_FT)
 203    "R" 5 bit fr source 3 register (OP_*_FR)
 204    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 205    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 206
 207    Coprocessor instructions:
 208    "E" 5 bit target register (OP_*_RT)
 209    "G" 5 bit destination register (OP_*_RD)
 210 start-sanitize-vr5400
 211    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 212    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 213    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 214    see also "k" above
 215 end-sanitize-vr5400
 216
 217    Macro instructions:
 218    "A" General 32 bit expression
 219    "I" 32 bit immediate
 220    "F" 64 bit floating point constant in .rdata
 221    "L" 64 bit floating point constant in .lit8
 222    "f" 32 bit floating point constant
 223    "l" 32 bit floating point constant in .lit4
 224
 225    Other:
 226    "()" parens surrounding optional value
 227    ","  separates operands
 228 start-sanitize-vr5400
 229    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 230 end-sanitize-vr5400
 231
 232    Characters used so far, for quick reference when adding more:
 233 start-sanitize-vr5400
 234    "Pe%[]" plus...
 235 end-sanitize-vr5400
 236    "<>(),"
 237    "ABCDEFGILMNSTRVW"
 238    "abcdfhijkloprstuvwxz"
 239 */
 240
 241 /* These are the bits which may be set in the pinfo field of an
 242    instructions, if it is not equal to INSN_MACRO.  */
 243
 244 /* Modifies the general purpose register in OP_*_RD.  */
 245 #define INSN_WRITE_GPR_D            0x00000001
 246 /* Modifies the general purpose register in OP_*_RT.  */
 247 #define INSN_WRITE_GPR_T            0x00000002
 248 /* Modifies general purpose register 31.  */
 249 #define INSN_WRITE_GPR_31           0x00000004
 250 /* Modifies the floating point register in OP_*_FD.  */
 251 #define INSN_WRITE_FPR_D            0x00000008
 252 /* Modifies the floating point register in OP_*_FS.  */
 253 #define INSN_WRITE_FPR_S            0x00000010
 254 /* Modifies the floating point register in OP_*_FT.  */
 255 #define INSN_WRITE_FPR_T            0x00000020
 256 /* Reads the general purpose register in OP_*_RS.  */
 257 #define INSN_READ_GPR_S             0x00000040
 258 /* Reads the general purpose register in OP_*_RT.  */
 259 #define INSN_READ_GPR_T             0x00000080
 260 /* Reads the floating point register in OP_*_FS.  */
 261 #define INSN_READ_FPR_S             0x00000100
 262 /* Reads the floating point register in OP_*_FT.  */
 263 #define INSN_READ_FPR_T             0x00000200
 264 /* Reads the floating point register in OP_*_FR.  */
 265 #define INSN_READ_FPR_R             0x00000400
 266 /* Modifies coprocessor condition code.  */
 267 #define INSN_WRITE_COND_CODE        0x00000800
 268 /* Reads coprocessor condition code.  */
 269 #define INSN_READ_COND_CODE         0x00001000
 270 /* TLB operation.  */
 271 #define INSN_TLB                    0x00002000
 272 /* Reads coprocessor register other than floating point register.  */
 273 #define INSN_COP                    0x00004000
 274 /* Instruction loads value from memory, requiring delay.  */
 275 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 276 /* Instruction loads value from coprocessor, requiring delay.  */
 277 #define INSN_LOAD_COPROC_DELAY      0x00010000
 278 /* Instruction has unconditional branch delay slot.  */
 279 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 280 /* Instruction has conditional branch delay slot.  */
 281 #define INSN_COND_BRANCH_DELAY      0x00040000
 282 /* Conditional branch likely: if branch not taken, insn nullified.  */
 283 #define INSN_COND_BRANCH_LIKELY     0x00080000
 284 /* Moves to coprocessor register, requiring delay.  */
 285 #define INSN_COPROC_MOVE_DELAY      0x00100000
 286 /* Loads coprocessor register from memory, requiring delay.  */
 287 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 288 /* Reads the HI register.  */
 289 #define INSN_READ_HI                0x00400000
 290 /* Reads the LO register.  */
 291 #define INSN_READ_LO                0x00800000
 292 /* Modifies the HI register.  */
 293 #define INSN_WRITE_HI               0x01000000
 294 /* Modifies the LO register.  */
 295 #define INSN_WRITE_LO               0x02000000
 296 /* Takes a trap (easier to keep out of delay slot).  */
 297 #define INSN_TRAP                   0x04000000
 298 /* Instruction stores value into memory.  */
 299 #define INSN_STORE_MEMORY           0x08000000
 300 /* Instruction uses single precision floating point.  */
 301 #define FP_S                        0x10000000
 302 /* Instruction uses double precision floating point.  */
 303 #define FP_D                        0x20000000
 304
 305 /* As yet unused bits:              0x40000000 */
 306
 307 /* Instruction is actually a macro.  It should be ignored by the
 308    disassembler, and requires special treatment by the assembler.  */
 309 #define INSN_MACRO                  0xffffffff
 310
 311
 312
 313
 314
 315 /* MIPS ISA field--CPU level at which insn is supported.  */
 316 #define INSN_ISA                    0x0000000F
 317 /* An instruction which is not part of any basic MIPS ISA.
 318    (ie it is a chip specific instruction)  */
 319 #define INSN_NO_ISA                 0x00000000
 320 /* MIPS ISA 1 instruction.  */
 321 #define INSN_ISA1                   0x00000001
 322 /* MIPS ISA 2 instruction (R6000 or R4000).  */
 323 #define INSN_ISA2                   0x00000002
 324 /* MIPS ISA 3 instruction (R4000).  */
 325 #define INSN_ISA3                   0x00000003
 326 /* MIPS ISA 4 instruction (R8000).  */
 327 #define INSN_ISA4                   0x00000004
 328
 329 /* Chip specific instructions.  These are bitmasks.  */
 330 /* MIPS R4650 instruction.  */
 331 #define INSN_4650                   0x00000010
 332 /* LSI R4010 instruction.  */
 333 #define INSN_4010                   0x00000020
 334 /* NEC VR4100 instruction. */
 335 #define INSN_4100                   0x00000040
 336 /* Toshiba R3900 instruction.  */
 337 #define INSN_3900                   0x00000080
 338 /* start-sanitize-vr5400 */
 339 /* NEC VR5400 instruction.  */
 340 #define INSN_5400                   0x00001000
 341 /* end-sanitize-vr5400 */
 342 /* start-sanitize-r5900 */
 343 /* Toshiba R5900 instruction */
 344 #define INSN_5900                   0x00000100
 345 /* end-sanitize-r5900 */
 346 /* start-sanitize-tx49 */
 347 #define INSN_4900                   0x00000200
 348 /* end-sanitize-tx49 */
 349
 350
 351 /* This is a list of macro expanded instructions.
 352  *
 353  * _I appended means immediate
 354  * _A appended means address
 355  * _AB appended means address with base register
 356  * _D appended means 64 bit floating point constant
 357  * _S appended means 32 bit floating point constant
 358  */
 359 enum {
 360     M_ABS,
 361     M_ADD_I,
 362     M_ADDU_I,
 363     M_AND_I,
 364     M_BEQ,
 365     M_BEQ_I,
 366     M_BEQL_I,
 367     M_BGE,
 368     M_BGEL,
 369     M_BGE_I,
 370     M_BGEL_I,
 371     M_BGEU,
 372     M_BGEUL,
 373     M_BGEU_I,
 374     M_BGEUL_I,
 375     M_BGT,
 376     M_BGTL,
 377     M_BGT_I,
 378     M_BGTL_I,
 379     M_BGTU,
 380     M_BGTUL,
 381     M_BGTU_I,
 382     M_BGTUL_I,
 383     M_BLE,
 384     M_BLEL,
 385     M_BLE_I,
 386     M_BLEL_I,
 387     M_BLEU,
 388     M_BLEUL,
 389     M_BLEU_I,
 390     M_BLEUL_I,
 391     M_BLT,
 392     M_BLTL,
 393     M_BLT_I,
 394     M_BLTL_I,
 395     M_BLTU,
 396     M_BLTUL,
 397     M_BLTU_I,
 398     M_BLTUL_I,
 399     M_BNE,
 400     M_BNE_I,
 401     M_BNEL_I,
 402     M_DABS,
 403     M_DADD_I,
 404     M_DADDU_I,
 405     M_DDIV_3,
 406     M_DDIV_3I,
 407     M_DDIVU_3,
 408     M_DDIVU_3I,
 409     M_DIV_3,
 410     M_DIV_3I,
 411     M_DIVU_3,
 412     M_DIVU_3I,
 413     M_DLA_AB,
 414     M_DLI,
 415     M_DMUL,
 416     M_DMUL_I,
 417     M_DMULO,
 418     M_DMULO_I,
 419     M_DMULOU,
 420     M_DMULOU_I,
 421     M_DREM_3,
 422     M_DREM_3I,
 423     M_DREMU_3,
 424     M_DREMU_3I,
 425     M_DSUB_I,
 426     M_DSUBU_I,
 427     M_DSUBU_I_2,
 428     M_J_A,
 429     M_JAL_1,
 430     M_JAL_2,
 431     M_JAL_A,
 432     M_L_DOB,
 433     M_L_DAB,
 434     M_LA_AB,
 435     M_LB_A,
 436     M_LB_AB,
 437     M_LBU_A,
 438     M_LBU_AB,
 439     M_LD_A,
 440     M_LD_OB,
 441     M_LD_AB,
 442     M_LDC1_AB,
 443     M_LDC2_AB,
 444     M_LDC3_AB,
 445     M_LDL_AB,
 446     M_LDR_AB,
 447     M_LH_A,
 448     M_LH_AB,
 449     M_LHU_A,
 450     M_LHU_AB,
 451     M_LI,
 452     M_LI_D,
 453     M_LI_DD,
 454     M_LI_S,
 455     M_LI_SS,
 456     M_LL_AB,
 457     M_LLD_AB,
 458     M_LS_A,
 459     M_LW_A,
 460     M_LW_AB,
 461     M_LWC0_A,
 462     M_LWC0_AB,
 463     M_LWC1_A,
 464     M_LWC1_AB,
 465     M_LWC2_A,
 466     M_LWC2_AB,
 467     M_LWC3_A,
 468     M_LWC3_AB,
 469     M_LWL_A,
 470     M_LWL_AB,
 471     M_LWR_A,
 472     M_LWR_AB,
 473     M_LWU_AB,
 474     M_MUL,
 475     M_MUL_I,
 476     M_MULO,
 477     M_MULO_I,
 478     M_MULOU,
 479     M_MULOU_I,
 480     M_NOR_I,
 481     M_OR_I,
 482     M_REM_3,
 483     M_REM_3I,
 484     M_REMU_3,
 485     M_REMU_3I,
 486     M_ROL,
 487     M_ROL_I,
 488     M_ROR,
 489     M_ROR_I,
 490     M_S_DA,
 491     M_S_DOB,
 492     M_S_DAB,
 493     M_S_S,
 494     M_SC_AB,
 495     M_SCD_AB,
 496     M_SD_A,
 497     M_SD_OB,
 498     M_SD_AB,
 499     M_SDC1_AB,
 500     M_SDC2_AB,
 501     M_SDC3_AB,
 502     M_SDL_AB,
 503     M_SDR_AB,
 504     M_SEQ,
 505     M_SEQ_I,
 506     M_SGE,
 507     M_SGE_I,
 508     M_SGEU,
 509     M_SGEU_I,
 510     M_SGT,
 511     M_SGT_I,
 512     M_SGTU,
 513     M_SGTU_I,
 514     M_SLE,
 515     M_SLE_I,
 516     M_SLEU,
 517     M_SLEU_I,
 518     M_SLT_I,
 519     M_SLTU_I,
 520     M_SNE,
 521     M_SNE_I,
 522     M_SB_A,
 523     M_SB_AB,
 524     M_SH_A,
 525     M_SH_AB,
 526     M_SW_A,
 527     M_SW_AB,
 528     M_SWC0_A,
 529     M_SWC0_AB,
 530     M_SWC1_A,
 531     M_SWC1_AB,
 532     M_SWC2_A,
 533     M_SWC2_AB,
 534     M_SWC3_A,
 535     M_SWC3_AB,
 536     M_SWL_A,
 537     M_SWL_AB,
 538     M_SWR_A,
 539     M_SWR_AB,
 540     M_SUB_I,
 541     M_SUBU_I,
 542     M_SUBU_I_2,
 543     M_TEQ_I,
 544     M_TGE_I,
 545     M_TGEU_I,
 546     M_TLT_I,
 547     M_TLTU_I,
 548     M_TNE_I,
 549     M_TRUNCWD,
 550     M_TRUNCWS,
 551     M_ULD,
 552     M_ULD_A,
 553     M_ULH,
 554     M_ULH_A,
 555     M_ULHU,
 556     M_ULHU_A,
 557     M_ULW,
 558     M_ULW_A,
 559     M_USH,
 560     M_USH_A,
 561     M_USW,
 562     M_USW_A,
 563     M_USD,
 564     M_USD_A,
 565     M_XOR_I,
 566     M_COP0,
 567     M_COP1,
 568     M_COP2,
 569     M_COP3,
 570     M_NUM_MACROS
 571 };
 572
 573
 574 /* The order of overloaded instructions matters.  Label arguments and
 575    register arguments look the same. Instructions that can have either
 576    for arguments must apear in the correct order in this table for the
 577    assembler to pick the right one. In other words, entries with
 578    immediate operands must apear after the same instruction with
 579    registers.
 580
 581    Many instructions are short hand for other instructions (i.e., The
 582    jal <register> instruction is short for jalr <register>).  */
 583
 584 extern const struct mips_opcode mips_builtin_opcodes[];
 585 extern const int bfd_mips_num_builtin_opcodes;
 586 extern struct mips_opcode *mips_opcodes;
 587 extern int bfd_mips_num_opcodes;
 588 #define NUMOPCODES bfd_mips_num_opcodes
 589
 590 \f
 591 /* The rest of this file adds definitions for the mips16 TinyRISC
 592    processor.  */
 593
 594 /* These are the bitmasks and shift counts used for the different
 595    fields in the instruction formats.  Other than OP, no masks are
 596    provided for the fixed portions of an instruction, since they are
 597    not needed.
 598
 599    The I format uses IMM11.
 600
 601    The RI format uses RX and IMM8.
 602
 603    The RR format uses RX, and RY.
 604
 605    The RRI format uses RX, RY, and IMM5.
 606
 607    The RRR format uses RX, RY, and RZ.
 608
 609    The RRI_A format uses RX, RY, and IMM4.
 610
 611    The SHIFT format uses RX, RY, and SHAMT.
 612
 613    The I8 format uses IMM8.
 614
 615    The I8_MOVR32 format uses RY and REGR32.
 616
 617    The IR_MOV32R format uses REG32R and MOV32Z.
 618
 619    The I64 format uses IMM8.
 620
 621    The RI64 format uses RY and IMM5.
 622    */
 623
 624 #define MIPS16OP_MASK_OP        0x1f
 625 #define MIPS16OP_SH_OP          11
 626 #define MIPS16OP_MASK_IMM11     0x7ff
 627 #define MIPS16OP_SH_IMM11       0
 628 #define MIPS16OP_MASK_RX        0x7
 629 #define MIPS16OP_SH_RX          8
 630 #define MIPS16OP_MASK_IMM8      0xff
 631 #define MIPS16OP_SH_IMM8        0
 632 #define MIPS16OP_MASK_RY        0x7
 633 #define MIPS16OP_SH_RY          5
 634 #define MIPS16OP_MASK_IMM5      0x1f
 635 #define MIPS16OP_SH_IMM5        0
 636 #define MIPS16OP_MASK_RZ        0x7
 637 #define MIPS16OP_SH_RZ          2
 638 #define MIPS16OP_MASK_IMM4      0xf
 639 #define MIPS16OP_SH_IMM4        0
 640 #define MIPS16OP_MASK_REGR32    0x1f
 641 #define MIPS16OP_SH_REGR32      0
 642 #define MIPS16OP_MASK_REG32R    0x1f
 643 #define MIPS16OP_SH_REG32R      3
 644 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 645 #define MIPS16OP_MASK_MOVE32Z   0x7
 646 #define MIPS16OP_SH_MOVE32Z     0
 647 #define MIPS16OP_MASK_IMM6      0x3f
 648 #define MIPS16OP_SH_IMM6        5
 649
 650 /* These are the characters which may appears in the args field of an
 651    instruction.  They appear in the order in which the fields appear
 652    when the instruction is used.  Commas and parentheses in the args
 653    string are ignored when assembling, and written into the output
 654    when disassembling.
 655
 656    "y" 3 bit register (MIPS16OP_*_RY)
 657    "x" 3 bit register (MIPS16OP_*_RX)
 658    "z" 3 bit register (MIPS16OP_*_RZ)
 659    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 660    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 661    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 662    "0" zero register ($0)
 663    "S" stack pointer ($sp or $29)
 664    "P" program counter
 665    "R" return address register ($ra or $31)
 666    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 667    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 668    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 669    "a" 26 bit jump address
 670    "e" 11 bit extension value
 671    "l" register list for entry instruction
 672    "L" register list for exit instruction
 673
 674    The remaining codes may be extended.  Except as otherwise noted,
 675    the full extended operand is a 16 bit signed value.
 676    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 677    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 678    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 679    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 680    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 681    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 682    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 683    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 684    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 685    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 686    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 687    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 688    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 689    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 690    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 691    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 692    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 693    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 694    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 695    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
 696    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
 697    */
 698
 699 /* For the mips16, we use the same opcode table format and a few of
 700    the same flags.  However, most of the flags are different.  */
 701
 702 /* Modifies the register in MIPS16OP_*_RX.  */
 703 #define MIPS16_INSN_WRITE_X                 0x00000001
 704 /* Modifies the register in MIPS16OP_*_RY.  */
 705 #define MIPS16_INSN_WRITE_Y                 0x00000002
 706 /* Modifies the register in MIPS16OP_*_RZ.  */
 707 #define MIPS16_INSN_WRITE_Z                 0x00000004
 708 /* Modifies the T ($24) register.  */
 709 #define MIPS16_INSN_WRITE_T                 0x00000008
 710 /* Modifies the SP ($29) register.  */
 711 #define MIPS16_INSN_WRITE_SP                0x00000010
 712 /* Modifies the RA ($31) register.  */
 713 #define MIPS16_INSN_WRITE_31                0x00000020
 714 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
 715 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
 716 /* Reads the register in MIPS16OP_*_RX.  */
 717 #define MIPS16_INSN_READ_X                  0x00000080
 718 /* Reads the register in MIPS16OP_*_RY.  */
 719 #define MIPS16_INSN_READ_Y                  0x00000100
 720 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
 721 #define MIPS16_INSN_READ_Z                  0x00000200
 722 /* Reads the T ($24) register.  */
 723 #define MIPS16_INSN_READ_T                  0x00000400
 724 /* Reads the SP ($29) register.  */
 725 #define MIPS16_INSN_READ_SP                 0x00000800
 726 /* Reads the RA ($31) register.  */
 727 #define MIPS16_INSN_READ_31                 0x00001000
 728 /* Reads the program counter.  */
 729 #define MIPS16_INSN_READ_PC                 0x00002000
 730 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 731 #define MIPS16_INSN_READ_GPR_X              0x00004000
 732
 733 /* The following flags have the same value for the mips16 opcode
 734    table:
 735    INSN_UNCOND_BRANCH_DELAY
 736    INSN_COND_BRANCH_DELAY
 737    INSN_COND_BRANCH_LIKELY (never used)
 738    INSN_READ_HI
 739    INSN_READ_LO
 740    INSN_WRITE_HI
 741    INSN_WRITE_LO
 742    INSN_TRAP
 743    INSN_ISA3
 744    */
 745
 746 extern const struct mips_opcode mips16_opcodes[];
 747 extern const int bfd_mips16_num_opcodes;
 748
 749 #endif /* _MIPS_H_ */