1 /* nds32.h -- Header file for nds32 opcode table
2 Copyright (C) 2012-2017 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
20 #ifndef OPCODE_NDS32_H
21 #define OPCODE_NDS32_H
38 /* Macros for extracting fields or making an instruction. */
39 static const int nds32_r45map
[] ATTRIBUTE_UNUSED
=
41 0, 1, 2, 3, 4, 5, 6, 7,
42 8, 9, 10, 11, 16, 17, 18, 19
45 static const int nds32_r54map
[] ATTRIBUTE_UNUSED
=
47 0, 1, 2, 3, 4, 5, 6, 7,
48 8, 9, 10, 11, -1, -1, -1, -1,
49 12, 13, 14, 15, -1, -1, -1, -1,
50 -1, -1, -1, -1, -1, -1, -1, -1
53 #define N32_BIT(n) (1 << (n))
54 #define __MASK(n) (N32_BIT (n) - 1)
55 #define __MF(v, off, bs) (((v) & __MASK (bs)) << (off))
56 #define __GF(v, off, bs) (((v) >> off) & __MASK (bs))
57 #define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1)))
59 /* Make nds32 instructions. */
61 #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \
62 (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \
63 | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \
64 | __MF (rd5, 5, 5) | __MF (sub5, 0, 5))
65 #define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \
66 (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \
67 | __MF (sub10, 0, 10))
68 #define N32_TYPE2(op6, rt5, ra5, imm15) \
69 (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15))
70 #define N32_TYPE1(op6, rt5, imm20) \
71 (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20))
72 #define N32_TYPE0(op6, imm25) \
73 (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25))
74 #define N32_ALU1(sub, rt, ra, rb) \
75 N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub)
76 #define N32_ALU1_SH(sub, rt, ra, rb, rd) \
77 N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub)
78 #define N32_ALU2(sub, rt, ra, rb) \
79 N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub)
80 #define N32_BR1(sub, rt, ra, imm14s) \
81 N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14)))
82 #define N32_BR2(sub, rt, imm16s) \
83 N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16)))
84 #define N32_BR3(sub, rt, imm11s, imm8s) \
85 N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \
86 | ((imm11s & __MASK (11)) << 8) \
87 | (imm8s & __MASK (8)))
88 #define N32_JI(sub, imm24s) \
89 N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24)))
90 #define N32_JREG(sub, rt, rb, dtit, hint) \
91 N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub)
92 #define N32_MEM(sub, rt, ra, rb, sv) \
93 N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub)
95 #define N16_TYPE55(op5, rt5, ra5) \
96 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
98 #define N16_TYPE45(op6, rt4, ra5) \
99 (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \
101 #define N16_TYPE333(op6, rt3, ra3, rb3) \
102 (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \
103 | __MF (ra3, 3, 3) | __MF (rb3, 0, 3))
104 #define N16_TYPE36(op6, rt3, imm6) \
105 (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \
107 #define N16_TYPE38(op4, rt3, imm8) \
108 (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \
110 #define N16_TYPE37(op4, rt3, ls, imm7) \
111 (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \
112 | __MF (imm7, 0, 7) | __MF (ls, 7, 1))
113 #define N16_TYPE5(op10, imm5) \
114 (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
115 #define N16_TYPE8(op7, imm8) \
116 (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8))
117 #define N16_TYPE9(op6, imm9) \
118 (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9))
119 #define N16_TYPE10(op5, imm10) \
120 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
121 #define N16_TYPE25(op8, re, imm5) \
122 (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \
125 #define N16_MISC33(sub, rt, ra) \
126 N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub)
127 #define N16_BFMI333(sub, rt, ra) \
128 N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub)
130 /* Get instruction fields.
132 Macros used for handling 32-bit and 16-bit instructions are
133 prefixed with N32_ and N16_ respectively. */
135 #define N32_OP6(insn) (((insn) >> 25) & 0x3f)
136 #define N32_RT5(insn) (((insn) >> 20) & 0x1f)
137 #define N32_RT53(insn) (N32_RT5 (insn) & 0x7)
138 #define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)]
139 #define N32_RA5(insn) (((insn) >> 15) & 0x1f)
140 #define N32_RA53(insn) (N32_RA5 (insn) & 0x7)
141 #define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)]
142 #define N32_RB5(insn) (((insn) >> 10) & 0x1f)
143 #define N32_UB5(insn) (((insn) >> 10) & 0x1f)
144 #define N32_RB53(insn) (N32_RB5 (insn) & 0x7)
145 #define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)]
146 #define N32_RD5(insn) (((insn) >> 5) & 0x1f)
147 #define N32_SH5(insn) (((insn) >> 5) & 0x1f)
148 #define N32_SUB5(insn) (((insn) >> 0) & 0x1f)
149 #define N32_SWID(insn) (((insn) >> 5) & 0x3ff)
150 #define N32_IMMU(insn, bs) ((insn) & __MASK (bs))
151 #define N32_IMMS(insn, bs) ((signed) __SEXT (((insn) & __MASK (bs)), bs))
152 #define N32_IMM5U(insn) N32_IMMU (insn, 5)
153 #define N32_IMM12S(insn) N32_IMMS (insn, 12)
154 #define N32_IMM14S(insn) N32_IMMS (insn, 14)
155 #define N32_IMM15U(insn) N32_IMMU (insn, 15)
156 #define N32_IMM15S(insn) N32_IMMS (insn, 15)
157 #define N32_IMM16S(insn) N32_IMMS (insn, 16)
158 #define N32_IMM17S(insn) N32_IMMS (insn, 17)
159 #define N32_IMM20S(insn) N32_IMMS (insn, 20)
160 #define N32_IMM20U(insn) N32_IMMU (insn, 20)
161 #define N32_IMM24S(insn) N32_IMMS (insn, 24)
163 #define N16_RT5(insn) (((insn) >> 5) & 0x1f)
164 #define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)]
165 #define N16_RT3(insn) (((insn) >> 6) & 0x7)
166 #define N16_RT38(insn) (((insn) >> 8) & 0x7)
167 #define N16_RT8(insn) (((insn) >> 8) & 0x7)
168 #define N16_RA5(insn) ((insn) & 0x1f)
169 #define N16_RA3(insn) (((insn) >> 3) & 0x7)
170 #define N16_RB3(insn) ((insn) & 0x7)
171 #define N16_IMM3U(insn) N32_IMMU (insn, 3)
172 #define N16_IMM5U(insn) N32_IMMU (insn, 5)
173 #define N16_IMM5S(insn) N32_IMMS (insn, 5)
174 #define N16_IMM6U(insn) N32_IMMU (insn, 6)
175 #define N16_IMM7U(insn) N32_IMMU (insn, 7)
176 #define N16_IMM8S(insn) N32_IMMS (insn, 8)
177 #define N16_IMM9U(insn) N32_IMMU (insn, 9)
178 #define N16_IMM10S(insn) N32_IMMS (insn, 10)
180 #define IS_WITHIN_U(v, n) (((v) >> n) == 0)
181 #define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n)
183 /* Get fields for specific instruction. */
184 #define N32_JREG_T(insn) (((insn) >> 8) & 0x3)
185 #define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7)
186 #define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf)
187 #define N32_COP_SUB(insn) ((insn) & 0xf)
188 #define N32_COP_CP(insn) (((insn) >> 4) & 0x3)
191 #define N32_IS_RT3(insn) (N32_RT5 (insn) < 8)
192 #define N32_IS_RA3(insn) (N32_RA5 (insn) < 8)
193 #define N32_IS_RB3(insn) (N32_RB5 (insn) < 8)
194 #define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1)
195 #define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1)
196 #define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1)
199 /* These are opcodes for Nxx_TYPE macros.
200 They are prefixed by corresponding TYPE to avoid misusing. */
204 /* Main opcodes (OP6). */
271 /* Sub-opcodes of specific opcode. */
285 N32_BR2_BGEZAL
= 0xc,
286 N32_BR2_BLTZAL
= 0xd,
300 N32_JREG_JRALNEZ
= 3,
303 N32_ALU1_ADD_SLLI
= 0x0,
341 /* bit[0:5], where bit[6:9] == 0 */
358 N32_ALU2_ADD_SC
= 0x10,
366 N32_ALU2_KADD
= 0x18,
369 N32_ALU2_MFUSR
= 0x20,
376 N32_ALU2_MULTS64
= 0x28,
384 N32_ALU2_0x30
= 0x30,
391 /* bit[0:5], where bit[6:9] != 0 */
393 N32_ALU2_FLMISM
= 0xf,
394 N32_ALU2_MULSR64
= 0x28,
395 N32_ALU2_MULR64
= 0x29,
396 N32_ALU2_MADDR32
= 0x33,
397 N32_ALU2_MSUBR32
= 0x35,
418 N32_MEM_LWS
, /* Not used. */
422 N32_MEM_LWS_BI
, /* Not used. */
423 N32_MEM_0x17
, /* Not used. */
447 N32_MISC_STANDBY
= 0,
493 N32_FPU_FS1_FADDS
= 0,
505 N32_FPU_FS1_FMULS
= 12,
508 N32_FPU_FS1_F2OP
= 15,
510 /* FS1/F2OP b[14:10] */
511 N32_FPU_FS1_F2OP_FS2D
= 0x00,
512 N32_FPU_FS1_F2OP_FSQRTS
= 0x01,
513 N32_FPU_FS1_F2OP_FABSS
= 0x05,
514 N32_FPU_FS1_F2OP_FUI2S
= 0x08,
515 N32_FPU_FS1_F2OP_FSI2S
= 0x0c,
516 N32_FPU_FS1_F2OP_FS2UI
= 0x10,
517 N32_FPU_FS1_F2OP_FS2UI_Z
= 0x14,
518 N32_FPU_FS1_F2OP_FS2SI
= 0x18,
519 N32_FPU_FS1_F2OP_FS2SI_Z
= 0x1c,
522 N32_FPU_FS2_FCMPEQS
= 0x0,
523 N32_FPU_FS2_FCMPLTS
= 0x2,
524 N32_FPU_FS2_FCMPLES
= 0x4,
525 N32_FPU_FS2_FCMPUNS
= 0x6,
526 N32_FPU_FS2_FCMPEQS_E
= 0x1,
527 N32_FPU_FS2_FCMPLTS_E
= 0x3,
528 N32_FPU_FS2_FCMPLES_E
= 0x5,
529 N32_FPU_FS2_FCMPUNS_E
= 0x7,
532 N32_FPU_FD1_FADDD
= 0,
544 N32_FPU_FD1_FMULD
= 12,
547 N32_FPU_FD1_F2OP
= 15,
549 /* FD1/F2OP b[14:10] */
550 N32_FPU_FD1_F2OP_FD2S
= 0x00,
551 N32_FPU_FD1_F2OP_FSQRTD
= 0x01,
552 N32_FPU_FD1_F2OP_FABSD
= 0x05,
553 N32_FPU_FD1_F2OP_FUI2D
= 0x08,
554 N32_FPU_FD1_F2OP_FSI2D
= 0x0c,
555 N32_FPU_FD1_F2OP_FD2UI
= 0x10,
556 N32_FPU_FD1_F2OP_FD2UI_Z
= 0x14,
557 N32_FPU_FD1_F2OP_FD2SI
= 0x18,
558 N32_FPU_FD1_F2OP_FD2SI_Z
= 0x1c,
561 N32_FPU_FD2_FCMPEQD
= 0x0,
562 N32_FPU_FD2_FCMPLTD
= 0x2,
563 N32_FPU_FD2_FCMPLED
= 0x4,
564 N32_FPU_FD2_FCMPUND
= 0x6,
565 N32_FPU_FD2_FCMPEQD_E
= 0x1,
566 N32_FPU_FD2_FCMPLTD_E
= 0x3,
567 N32_FPU_FD2_FCMPLED_E
= 0x5,
568 N32_FPU_FD2_FCMPUND_E
= 0x7,
571 N32_FPU_MFCP_FMFSR
= 0x0,
572 N32_FPU_MFCP_FMFDR
= 0x1,
573 N32_FPU_MFCP_XR
= 0xc,
575 /* MFCP/XR b[14:10] */
576 N32_FPU_MFCP_XR_FMFCFG
= 0x0,
577 N32_FPU_MFCP_XR_FMFCSR
= 0x1,
580 N32_FPU_MTCP_FMTSR
= 0x0,
581 N32_FPU_MTCP_FMTDR
= 0x1,
582 N32_FPU_MTCP_XR
= 0xc,
584 /* MTCP/XR b[14:10] */
585 N32_FPU_MTCP_XR_FMTCSR
= 0x1
591 N16_T55_MOVI55
= 0x1,
596 N16_T45_ADDI45
= 0x6,
597 N16_T45_SUBI45
= 0x7,
598 N16_T45_SRAI45
= 0x8,
599 N16_T45_SRLI45
= 0x9,
600 N16_T45_LWI45_FE
= 0x19,
601 N16_T45_LWI450
= 0x1a,
602 N16_T45_SWI450
= 0x1b,
603 N16_T45_SLTS45
= 0x30,
604 N16_T45_SLT45
= 0x31,
605 N16_T45_SLTSI45
= 0x32,
606 N16_T45_SLTI45
= 0x33,
607 N16_T45_MOVPI45
= 0x3d,
609 N15_T44_MOVD44
= 0x7d,
612 N16_T333_SLLI333
= 0xa,
613 N16_T333_BFMI333
= 0xb,
614 N16_T333_ADD333
= 0xc,
615 N16_T333_SUB333
= 0xd,
616 N16_T333_ADDI333
= 0xe,
617 N16_T333_SUBI333
= 0xf,
618 N16_T333_LWI333
= 0x10,
619 N16_T333_LWI333_BI
= 0x11,
620 N16_T333_LHI333
= 0x12,
621 N16_T333_LBI333
= 0x13,
622 N16_T333_SWI333
= 0x14,
623 N16_T333_SWI333_BI
= 0x15,
624 N16_T333_SHI333
= 0x16,
625 N16_T333_SBI333
= 0x17,
626 N16_T333_MISC33
= 0x3f,
628 N16_T36_ADDRI36_SP
= 0x18,
631 N16_T37_XWI37SP
= 0xe,
633 N16_T38_BEQZ38
= 0x8,
634 N16_T38_BNEZ38
= 0x9,
635 N16_T38_BEQS38
= 0xa,
636 N16_T38_BNES38
= 0xb,
639 N16_T5_JRAL5
= 0x2e9,
640 N16_T5_EX9IT
= 0x2ea,
641 /* 0x2eb reserved. */
643 N16_T5_ADD5PC
= 0x2ed,
644 /* 0x2e[ef] reserved. */
645 N16_T5_BREAK16
= 0x350,
648 N16_T8_BEQZS8
= 0x68,
649 N16_T8_BNEZS8
= 0x69,
651 /* N16_T9_BREAK16 = 0x35
652 Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT. */
654 N16_T9_IFCALL9
= 0x3c,
656 N16_T10_ADDI10S
= 0x1b,
658 N16_T25_PUSH25
= 0xf8,
659 N16_T25_POP25
= 0xf9,
664 N16_MISC33_NEG33
= 2,
665 N16_MISC33_NOT33
= 3,
666 N16_MISC33_MUL33
= 4,
667 N16_MISC33_XOR33
= 5,
668 N16_MISC33_AND33
= 6,
671 N16_BFMI333_ZEB33
= 0,
672 N16_BFMI333_ZEH33
= 1,
673 N16_BFMI333_SEB33
= 2,
674 N16_BFMI333_SEH33
= 3,
675 N16_BFMI333_XLSB33
= 4,
676 N16_BFMI333_X11B33
= 5,
677 N16_BFMI333_BMSKI33
= 6,
678 N16_BFMI333_FEXTI33
= 7
681 /* These macros a deprecated. DO NOT use them anymore.
682 And please help rewrite code used them. */
684 /* 32-bit instructions without operands. */
685 #define INSN_SETHI 0x46000000
686 #define INSN_ORI 0x58000000
687 #define INSN_JR 0x4a000000
688 #define INSN_RET 0x4a000020
689 #define INSN_JAL 0x49000000
690 #define INSN_J 0x48000000
691 #define INSN_JRAL 0x4a000001
692 #define INSN_BGEZAL 0x4e0c0000
693 #define INSN_BLTZAL 0x4e0d0000
694 #define INSN_BEQ 0x4c000000
695 #define INSN_BNE 0x4c004000
696 #define INSN_BEQZ 0x4e020000
697 #define INSN_BNEZ 0x4e030000
698 #define INSN_BGEZ 0x4e040000
699 #define INSN_BLTZ 0x4e050000
700 #define INSN_BGTZ 0x4e060000
701 #define INSN_BLEZ 0x4e070000
702 #define INSN_MOVI 0x44000000
703 #define INSN_ADDI 0x50000000
704 #define INSN_ANDI 0x54000000
705 #define INSN_LDI 0x06000000
706 #define INSN_SDI 0x16000000
707 #define INSN_LWI 0x04000000
708 #define INSN_LWSI 0x24000000
709 #define INSN_LWIP 0x0c000000
710 #define INSN_LHI 0x02000000
711 #define INSN_LHSI 0x22000000
712 #define INSN_LBI 0x00000000
713 #define INSN_LBSI 0x20000000
714 #define INSN_SWI 0x14000000
715 #define INSN_SWIP 0x1c000000
716 #define INSN_SHI 0x12000000
717 #define INSN_SBI 0x10000000
718 #define INSN_SLTI 0x5c000000
719 #define INSN_SLTSI 0x5e000000
720 #define INSN_ADD 0x40000000
721 #define INSN_SUB 0x40000001
722 #define INSN_SLT 0x40000006
723 #define INSN_SLTS 0x40000007
724 #define INSN_SLLI 0x40000008
725 #define INSN_SRLI 0x40000009
726 #define INSN_SRAI 0x4000000a
727 #define INSN_SEB 0x40000010
728 #define INSN_SEH 0x40000011
729 #define INSN_ZEB INSN_ANDI + 0xFF
730 #define INSN_ZEH 0x40000013
731 #define INSN_BREAK 0x6400000a
732 #define INSN_NOP 0x40000009
733 #define INSN_FLSI 0x30000000
734 #define INSN_FSSI 0x32000000
735 #define INSN_FLDI 0x34000000
736 #define INSN_FSDI 0x36000000
737 #define INSN_BEQC 0x5a000000
738 #define INSN_BNEC 0x5a080000
739 #define INSN_DSB 0x64000008
740 #define INSN_IFCALL 0x4e000000
741 #define INSN_IFRET 0x4a000060
742 #define INSN_BR1 0x4c000000
743 #define INSN_BR2 0x4e000000
745 /* 16-bit instructions without operand. */
746 #define INSN_MOV55 0x8000
747 #define INSN_MOVI55 0x8400
748 #define INSN_ADD45 0x8800
749 #define INSN_SUB45 0x8a00
750 #define INSN_ADDI45 0x8c00
751 #define INSN_SUBI45 0x8e00
752 #define INSN_SRAI45 0x9000
753 #define INSN_SRLI45 0x9200
754 #define INSN_SLLI333 0x9400
755 #define INSN_BFMI333 0x9600
756 #define INSN_ADD333 0x9800
757 #define INSN_SUB333 0x9a00
758 #define INSN_ADDI333 0x9c00
759 #define INSN_SUBI333 0x9e00
760 #define INSN_LWI333 0xa000
761 #define INSN_LWI333P 0xa200
762 #define INSN_LHI333 0xa400
763 #define INSN_LBI333 0xa600
764 #define INSN_SWI333 0xa800
765 #define INSN_SWI333P 0xaa00
766 #define INSN_SHI333 0xac00
767 #define INSN_SBI333 0xae00
768 #define INSN_RSV01 0xb000
769 #define INSN_RSV02 0xb200
770 #define INSN_LWI450 0xb400
771 #define INSN_SWI450 0xb600
772 #define INSN_LWI37 0xb800
773 #define INSN_SWI37 0xb880
774 #define INSN_BEQZ38 0xc000
775 #define INSN_BNEZ38 0xc800
776 #define INSN_BEQS38 0xd000
777 #define INSN_J8 0xd500
778 #define INSN_BNES38 0xd800
779 #define INSN_JR5 0xdd00
780 #define INSN_RET5 0xdd80
781 #define INSN_JRAL5 0xdd20
782 #define INSN_EX9_IT_2 0xdd40
783 #define INSN_SLTS45 0xe000
784 #define INSN_SLT45 0xe200
785 #define INSN_SLTSI45 0xe400
786 #define INSN_SLTI45 0xe600
787 #define INSN_BEQZS8 0xe800
788 #define INSN_BNEZS8 0xe900
789 #define INSN_BREAK16 0xea00
790 #define INSN_EX9_IT_1 0xea00
791 #define INSN_NOP16 0x9200
792 /* 16-bit version 2. */
793 #define INSN_ADDI10_SP 0xec00
794 #define INSN_LWI37SP 0xf000
795 #define INSN_SWI37SP 0xf080
796 /* 16-bit version 3. */
797 #define INSN_IFRET16 0x83ff
798 #define INSN_ADDRI36_SP 0xb000
799 #define INSN_LWI45_FE 0xb200
800 #define INSN_IFCALL9 0xf800
801 #define INSN_MISC33 0xfe00
803 /* Instruction with specific operands. */
804 #define INSN_ADDI_GP_TO_FP 0x51cd8000 /* BASELINE_V1. */
805 #define INSN_ADDIGP_TO_FP 0x3fc80000 /* BASELINE_V2. */
806 #define INSN_MOVI_TO_FP 0x45c00000
807 #define INSN_MFUSR_PC 0x420F8020
808 #define INSN_MFUSR_PC_MASK 0xFE0FFFFF
810 /* Instructions use $ta register as operand. */
811 #define INSN_SETHI_TA (INSN_SETHI | (REG_TA << 20))
812 #define INSN_ORI_TA (INSN_ORI | (REG_TA << 20) | (REG_TA << 15))
813 #define INSN_ADD_TA (INSN_ADD | (REG_TA << 20))
814 #define INSN_ADD45_TA (INSN_ADD45 | (REG_TA << 5))
815 #define INSN_JR5_TA (INSN_JR5 | (REG_TA << 0))
816 #define INSN_RET5_TA (INSN_RET5 | (REG_TA << 0))
817 #define INSN_JR_TA (INSN_JR | (REG_TA << 10))
818 #define INSN_RET_TA (INSN_RET | (REG_TA << 10))
819 #define INSN_JRAL_TA (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10))
820 #define INSN_JRAL5_TA (INSN_JRAL5 | (REG_TA << 0))
821 #define INSN_BEQZ_TA (INSN_BEQZ | (REG_TA << 20))
822 #define INSN_BNEZ_TA (INSN_BNEZ | (REG_TA << 20))
823 #define INSN_MOVI_TA (INSN_MOVI | (REG_TA << 20))
824 #define INSN_BEQ_TA (INSN_BEQ | (REG_TA << 15))
825 #define INSN_BNE_TA (INSN_BNE | (REG_TA << 15))
827 /* Instructions use $r5 register as operand. */
828 #define INSN_BNE_R5 (INSN_BNE | (REG_R5 << 15))
829 #define INSN_BEQ_R5 (INSN_BEQ | (REG_R5 << 15))
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