include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   3    2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version 3,
  11    or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING3.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #ifndef PPC_H
  24 #define PPC_H
  25
  26 #include "bfd_stdint.h"
  27
  28 typedef uint64_t ppc_cpu_t;
  29
  30 /* The opcode table is an array of struct powerpc_opcode.  */
  31
  32 struct powerpc_opcode
  33 {
  34   /* The opcode name.  */
  35   const char *name;
  36
  37   /* The opcode itself.  Those bits which will be filled in with
  38      operands are zeroes.  */
  39   unsigned long opcode;
  40
  41   /* The opcode mask.  This is used by the disassembler.  This is a
  42      mask containing ones indicating those bits which must match the
  43      opcode field, and zeroes indicating those bits which need not
  44      match (and are presumably filled in by operands).  */
  45   unsigned long mask;
  46
  47   /* One bit flags for the opcode.  These are used to indicate which
  48      specific processors support the instructions.  The defined values
  49      are listed below.  */
  50   ppc_cpu_t flags;
  51
  52   /* One bit flags for the opcode.  These are used to indicate which
  53      specific processors no longer support the instructions.  The defined
  54      values are listed below.  */
  55   ppc_cpu_t deprecated;
  56
  57   /* An array of operand codes.  Each code is an index into the
  58      operand table.  They appear in the order which the operands must
  59      appear in assembly code, and are terminated by a zero.  */
  60   unsigned char operands[8];
  61 };
  62
  63 /* The table itself is sorted by major opcode number, and is otherwise
  64    in the order in which the disassembler should consider
  65    instructions.  */
  66 extern const struct powerpc_opcode powerpc_opcodes[];
  67 extern const int powerpc_num_opcodes;
  68
  69 /* Values defined for the flags field of a struct powerpc_opcode.  */
  70
  71 /* Opcode is defined for the PowerPC architecture.  */
  72 #define PPC_OPCODE_PPC                   1
  73
  74 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  75 #define PPC_OPCODE_POWER                 2
  76
  77 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  78 #define PPC_OPCODE_POWER2                4
  79
  80 /* Opcode is only defined on 32 bit architectures.  */
  81 #define PPC_OPCODE_32                    8
  82
  83 /* Opcode is only defined on 64 bit architectures.  */
  84 #define PPC_OPCODE_64                 0x10
  85
  86 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  87    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  88    but it also supports many additional POWER instructions.  */
  89 #define PPC_OPCODE_601                0x20
  90
  91 /* Opcode is supported in both the Power and PowerPC architectures
  92    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  93 #define PPC_OPCODE_COMMON             0x40
  94
  95 /* Opcode is supported for any Power or PowerPC platform (this is
  96    for the assembler's -many option, and it eliminates duplicates).  */
  97 #define PPC_OPCODE_ANY                0x80
  98
  99 /* Opcode is supported as part of the 64-bit bridge.  */
 100 #define PPC_OPCODE_64_BRIDGE         0x100
 101
 102 /* Opcode is supported by Altivec Vector Unit */
 103 #define PPC_OPCODE_ALTIVEC           0x200
 104
 105 /* Opcode is supported by PowerPC 403 processor.  */
 106 #define PPC_OPCODE_403               0x400
 107
 108 /* Opcode is supported by PowerPC BookE processor.  */
 109 #define PPC_OPCODE_BOOKE             0x800
 110
 111 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 112 #define PPC_OPCODE_BOOKE64          0x1000
 113
 114 /* Opcode is supported by PowerPC 440 processor.  */
 115 #define PPC_OPCODE_440              0x2000
 116
 117 /* Opcode is only supported by Power4 architecture.  */
 118 #define PPC_OPCODE_POWER4           0x4000
 119
 120 /* Opcode is only supported by Power7 architecture.  */
 121 #define PPC_OPCODE_POWER7           0x8000
 122
 123 /* Opcode is only supported by POWERPC Classic architecture.  */
 124 #define PPC_OPCODE_CLASSIC         0x10000
 125
 126 /* Opcode is only supported by e500x2 Core.  */
 127 #define PPC_OPCODE_SPE             0x20000
 128
 129 /* Opcode is supported by e500x2 Integer select APU.  */
 130 #define PPC_OPCODE_ISEL            0x40000
 131
 132 /* Opcode is an e500 SPE floating point instruction.  */
 133 #define PPC_OPCODE_EFS             0x80000
 134
 135 /* Opcode is supported by branch locking APU.  */
 136 #define PPC_OPCODE_BRLOCK         0x100000
 137
 138 /* Opcode is supported by performance monitor APU.  */
 139 #define PPC_OPCODE_PMR            0x200000
 140
 141 /* Opcode is supported by cache locking APU.  */
 142 #define PPC_OPCODE_CACHELCK       0x400000
 143
 144 /* Opcode is supported by machine check APU.  */
 145 #define PPC_OPCODE_RFMCI          0x800000
 146
 147 /* Opcode is only supported by Power5 architecture.  */
 148 #define PPC_OPCODE_POWER5        0x1000000
 149
 150 /* Opcode is supported by PowerPC e300 family.  */
 151 #define PPC_OPCODE_E300          0x2000000
 152
 153 /* Opcode is only supported by Power6 architecture.  */
 154 #define PPC_OPCODE_POWER6        0x4000000
 155
 156 /* Opcode is only supported by PowerPC Cell family.  */
 157 #define PPC_OPCODE_CELL          0x8000000
 158
 159 /* Opcode is supported by CPUs with paired singles support.  */
 160 #define PPC_OPCODE_PPCPS         0x10000000
 161
 162 /* Opcode is supported by Power E500MC */
 163 #define PPC_OPCODE_E500MC        0x20000000
 164
 165 /* Opcode is supported by PowerPC 405 processor.  */
 166 #define PPC_OPCODE_405           0x40000000
 167
 168 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 169 #define PPC_OPCODE_VSX           0x80000000
 170
 171 /* Opcode is supported by A2.  */
 172 #define PPC_OPCODE_A2            0x100000000ULL
 173
 174 /* Opcode is supported by PowerPC 476 processor.  */
 175 #define PPC_OPCODE_476           0x200000000ULL
 176
 177 /* Opcode is supported by AppliedMicro Titan core */
 178 #define PPC_OPCODE_TITAN         0x400000000ULL
 179
 180 /* Opcode which is supported by the e500 family */
 181 #define PPC_OPCODE_E500         0x800000000ULL
 182
 183 /* A macro to extract the major opcode from an instruction.  */
 184 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 185 \f
 186 /* The operands table is an array of struct powerpc_operand.  */
 187
 188 struct powerpc_operand
 189 {
 190   /* A bitmask of bits in the operand.  */
 191   unsigned int bitm;
 192
 193   /* How far the operand is left shifted in the instruction.
 194      -1 to indicate that BITM and SHIFT cannot be used to determine
 195      where the operand goes in the insn.  */
 196   int shift;
 197
 198   /* Insertion function.  This is used by the assembler.  To insert an
 199      operand value into an instruction, check this field.
 200
 201      If it is NULL, execute
 202          i |= (op & o->bitm) << o->shift;
 203      (i is the instruction which we are filling in, o is a pointer to
 204      this structure, and op is the operand value).
 205
 206      If this field is not NULL, then simply call it with the
 207      instruction and the operand value.  It will return the new value
 208      of the instruction.  If the ERRMSG argument is not NULL, then if
 209      the operand value is illegal, *ERRMSG will be set to a warning
 210      string (the operand will be inserted in any case).  If the
 211      operand value is legal, *ERRMSG will be unchanged (most operands
 212      can accept any value).  */
 213   unsigned long (*insert)
 214     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 215
 216   /* Extraction function.  This is used by the disassembler.  To
 217      extract this operand type from an instruction, check this field.
 218
 219      If it is NULL, compute
 220          op = (i >> o->shift) & o->bitm;
 221          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 222            sign_extend (op);
 223      (i is the instruction, o is a pointer to this structure, and op
 224      is the result).
 225
 226      If this field is not NULL, then simply call it with the
 227      instruction value.  It will return the value of the operand.  If
 228      the INVALID argument is not NULL, *INVALID will be set to
 229      non-zero if this operand type can not actually be extracted from
 230      this operand (i.e., the instruction does not match).  If the
 231      operand is valid, *INVALID will not be changed.  */
 232   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 233
 234   /* One bit syntax flags.  */
 235   unsigned long flags;
 236 };
 237
 238 /* Elements in the table are retrieved by indexing with values from
 239    the operands field of the powerpc_opcodes table.  */
 240
 241 extern const struct powerpc_operand powerpc_operands[];
 242 extern const unsigned int num_powerpc_operands;
 243
 244 /* Values defined for the flags field of a struct powerpc_operand.  */
 245
 246 /* This operand takes signed values.  */
 247 #define PPC_OPERAND_SIGNED (0x1)
 248
 249 /* This operand takes signed values, but also accepts a full positive
 250    range of values when running in 32 bit mode.  That is, if bits is
 251    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 252    this flag is ignored.  */
 253 #define PPC_OPERAND_SIGNOPT (0x2)
 254
 255 /* This operand does not actually exist in the assembler input.  This
 256    is used to support extended mnemonics such as mr, for which two
 257    operands fields are identical.  The assembler should call the
 258    insert function with any op value.  The disassembler should call
 259    the extract function, ignore the return value, and check the value
 260    placed in the valid argument.  */
 261 #define PPC_OPERAND_FAKE (0x4)
 262
 263 /* The next operand should be wrapped in parentheses rather than
 264    separated from this one by a comma.  This is used for the load and
 265    store instructions which want their operands to look like
 266        reg,displacement(reg)
 267    */
 268 #define PPC_OPERAND_PARENS (0x8)
 269
 270 /* This operand may use the symbolic names for the CR fields, which
 271    are
 272        lt  0    gt  1   eq  2   so  3   un  3
 273        cr0 0    cr1 1   cr2 2   cr3 3
 274        cr4 4    cr5 5   cr6 6   cr7 7
 275    These may be combined arithmetically, as in cr2*4+gt.  These are
 276    only supported on the PowerPC, not the POWER.  */
 277 #define PPC_OPERAND_CR (0x10)
 278
 279 /* This operand names a register.  The disassembler uses this to print
 280    register names with a leading 'r'.  */
 281 #define PPC_OPERAND_GPR (0x20)
 282
 283 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 284 #define PPC_OPERAND_GPR_0 (0x40)
 285
 286 /* This operand names a floating point register.  The disassembler
 287    prints these with a leading 'f'.  */
 288 #define PPC_OPERAND_FPR (0x80)
 289
 290 /* This operand is a relative branch displacement.  The disassembler
 291    prints these symbolically if possible.  */
 292 #define PPC_OPERAND_RELATIVE (0x100)
 293
 294 /* This operand is an absolute branch address.  The disassembler
 295    prints these symbolically if possible.  */
 296 #define PPC_OPERAND_ABSOLUTE (0x200)
 297
 298 /* This operand is optional, and is zero if omitted.  This is used for
 299    example, in the optional BF field in the comparison instructions.  The
 300    assembler must count the number of operands remaining on the line,
 301    and the number of operands remaining for the opcode, and decide
 302    whether this operand is present or not.  The disassembler should
 303    print this operand out only if it is not zero.  */
 304 #define PPC_OPERAND_OPTIONAL (0x400)
 305
 306 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 307    is omitted, then for the next operand use this operand value plus
 308    1, ignoring the next operand field for the opcode.  This wretched
 309    hack is needed because the Power rotate instructions can take
 310    either 4 or 5 operands.  The disassembler should print this operand
 311    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 312 #define PPC_OPERAND_NEXT (0x800)
 313
 314 /* This operand should be regarded as a negative number for the
 315    purposes of overflow checking (i.e., the normal most negative
 316    number is disallowed and one more than the normal most positive
 317    number is allowed).  This flag will only be set for a signed
 318    operand.  */
 319 #define PPC_OPERAND_NEGATIVE (0x1000)
 320
 321 /* This operand names a vector unit register.  The disassembler
 322    prints these with a leading 'v'.  */
 323 #define PPC_OPERAND_VR (0x2000)
 324
 325 /* This operand is for the DS field in a DS form instruction.  */
 326 #define PPC_OPERAND_DS (0x4000)
 327
 328 /* This operand is for the DQ field in a DQ form instruction.  */
 329 #define PPC_OPERAND_DQ (0x8000)
 330
 331 /* Valid range of operand is 0..n rather than 0..n-1.  */
 332 #define PPC_OPERAND_PLUS1 (0x10000)
 333
 334 /* Xilinx APU and FSL related operands */
 335 #define PPC_OPERAND_FSL (0x20000)
 336 #define PPC_OPERAND_FCR (0x40000)
 337 #define PPC_OPERAND_UDI (0x80000)
 338
 339 /* This operand names a vector-scalar unit register.  The disassembler
 340    prints these with a leading 'vs'.  */
 341 #define PPC_OPERAND_VSR (0x100000)
 342 \f
 343 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 344    with the operands table for simplicity.  The macro table is an
 345    array of struct powerpc_macro.  */
 346
 347 struct powerpc_macro
 348 {
 349   /* The macro name.  */
 350   const char *name;
 351
 352   /* The number of operands the macro takes.  */
 353   unsigned int operands;
 354
 355   /* One bit flags for the opcode.  These are used to indicate which
 356      specific processors support the instructions.  The values are the
 357      same as those for the struct powerpc_opcode flags field.  */
 358   ppc_cpu_t flags;
 359
 360   /* A format string to turn the macro into a normal instruction.
 361      Each %N in the string is replaced with operand number N (zero
 362      based).  */
 363   const char *format;
 364 };
 365
 366 extern const struct powerpc_macro powerpc_macros[];
 367 extern const int powerpc_num_macros;
 368
 369 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
 370
 371 #endif /* PPC_H */