* config.sub, config.guess: Update from upstream sources.
[deliverable/binutils-gdb.git] / include / opcode / ppc.h
1 /* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22 #ifndef PPC_H
23 #define PPC_H
24
25 /* The opcode table is an array of struct powerpc_opcode. */
26
27 struct powerpc_opcode
28 {
29 /* The opcode name. */
30 const char *name;
31
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
34 unsigned long opcode;
35
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
40 unsigned long mask;
41
42 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values
44 are listed below. */
45 unsigned long flags;
46
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[8];
51 };
52
53 /* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
55 instructions. */
56 extern const struct powerpc_opcode powerpc_opcodes[];
57 extern const int powerpc_num_opcodes;
58
59 /* Values defined for the flags field of a struct powerpc_opcode. */
60
61 /* Opcode is defined for the PowerPC architecture. */
62 #define PPC_OPCODE_PPC 1
63
64 /* Opcode is defined for the POWER (RS/6000) architecture. */
65 #define PPC_OPCODE_POWER 2
66
67 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
68 #define PPC_OPCODE_POWER2 4
69
70 /* Opcode is only defined on 32 bit architectures. */
71 #define PPC_OPCODE_32 8
72
73 /* Opcode is only defined on 64 bit architectures. */
74 #define PPC_OPCODE_64 0x10
75
76 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */
79 #define PPC_OPCODE_601 0x20
80
81 /* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */
83 #define PPC_OPCODE_COMMON 0x40
84
85 /* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */
87 #define PPC_OPCODE_ANY 0x80
88
89 /* Opcode is supported as part of the 64-bit bridge. */
90 #define PPC_OPCODE_64_BRIDGE 0x100
91
92 /* Opcode is supported by Altivec Vector Unit */
93 #define PPC_OPCODE_ALTIVEC 0x200
94
95 /* Opcode is supported by PowerPC 403 processor. */
96 #define PPC_OPCODE_403 0x400
97
98 /* Opcode is supported by PowerPC BookE processor. */
99 #define PPC_OPCODE_BOOKE 0x800
100
101 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
102 #define PPC_OPCODE_BOOKE64 0x1000
103
104 /* Opcode is supported by PowerPC 440 processor. */
105 #define PPC_OPCODE_440 0x2000
106
107 /* Opcode is only supported by Power4 architecture. */
108 #define PPC_OPCODE_POWER4 0x4000
109
110 /* Opcode isn't supported by Power4 architecture. */
111 #define PPC_OPCODE_NOPOWER4 0x8000
112
113 /* Opcode is only supported by POWERPC Classic architecture. */
114 #define PPC_OPCODE_CLASSIC 0x10000
115
116 /* Opcode is only supported by e500x2 Core. */
117 #define PPC_OPCODE_SPE 0x20000
118
119 /* Opcode is supported by e500x2 Integer select APU. */
120 #define PPC_OPCODE_ISEL 0x40000
121
122 /* Opcode is an e500 SPE floating point instruction. */
123 #define PPC_OPCODE_EFS 0x80000
124
125 /* Opcode is supported by branch locking APU. */
126 #define PPC_OPCODE_BRLOCK 0x100000
127
128 /* Opcode is supported by performance monitor APU. */
129 #define PPC_OPCODE_PMR 0x200000
130
131 /* Opcode is supported by cache locking APU. */
132 #define PPC_OPCODE_CACHELCK 0x400000
133
134 /* Opcode is supported by machine check APU. */
135 #define PPC_OPCODE_RFMCI 0x800000
136
137 /* Opcode is only supported by Power5 architecture. */
138 #define PPC_OPCODE_POWER5 0x1000000
139
140 /* Opcode is supported by PowerPC e300 family. */
141 #define PPC_OPCODE_E300 0x2000000
142
143 /* Opcode is only supported by Power6 architecture. */
144 #define PPC_OPCODE_POWER6 0x4000000
145
146 /* Opcode is only supported by PowerPC Cell family. */
147 #define PPC_OPCODE_CELL 0x8000000
148
149 /* Opcode is supported by CPUs with paired singles support. */
150 #define PPC_OPCODE_PPCPS 0x10000000
151
152 /* A macro to extract the major opcode from an instruction. */
153 #define PPC_OP(i) (((i) >> 26) & 0x3f)
154 \f
155 /* The operands table is an array of struct powerpc_operand. */
156
157 struct powerpc_operand
158 {
159 /* A bitmask of bits in the operand. */
160 unsigned int bitm;
161
162 /* How far the operand is left shifted in the instruction.
163 -1 to indicate that BITM and SHIFT cannot be used to determine
164 where the operand goes in the insn. */
165 int shift;
166
167 /* Insertion function. This is used by the assembler. To insert an
168 operand value into an instruction, check this field.
169
170 If it is NULL, execute
171 i |= (op & o->bitm) << o->shift;
172 (i is the instruction which we are filling in, o is a pointer to
173 this structure, and op is the operand value).
174
175 If this field is not NULL, then simply call it with the
176 instruction and the operand value. It will return the new value
177 of the instruction. If the ERRMSG argument is not NULL, then if
178 the operand value is illegal, *ERRMSG will be set to a warning
179 string (the operand will be inserted in any case). If the
180 operand value is legal, *ERRMSG will be unchanged (most operands
181 can accept any value). */
182 unsigned long (*insert)
183 (unsigned long instruction, long op, int dialect, const char **errmsg);
184
185 /* Extraction function. This is used by the disassembler. To
186 extract this operand type from an instruction, check this field.
187
188 If it is NULL, compute
189 op = (i >> o->shift) & o->bitm;
190 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
191 sign_extend (op);
192 (i is the instruction, o is a pointer to this structure, and op
193 is the result).
194
195 If this field is not NULL, then simply call it with the
196 instruction value. It will return the value of the operand. If
197 the INVALID argument is not NULL, *INVALID will be set to
198 non-zero if this operand type can not actually be extracted from
199 this operand (i.e., the instruction does not match). If the
200 operand is valid, *INVALID will not be changed. */
201 long (*extract) (unsigned long instruction, int dialect, int *invalid);
202
203 /* One bit syntax flags. */
204 unsigned long flags;
205 };
206
207 /* Elements in the table are retrieved by indexing with values from
208 the operands field of the powerpc_opcodes table. */
209
210 extern const struct powerpc_operand powerpc_operands[];
211 extern const unsigned int num_powerpc_operands;
212
213 /* Values defined for the flags field of a struct powerpc_operand. */
214
215 /* This operand takes signed values. */
216 #define PPC_OPERAND_SIGNED (0x1)
217
218 /* This operand takes signed values, but also accepts a full positive
219 range of values when running in 32 bit mode. That is, if bits is
220 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
221 this flag is ignored. */
222 #define PPC_OPERAND_SIGNOPT (0x2)
223
224 /* This operand does not actually exist in the assembler input. This
225 is used to support extended mnemonics such as mr, for which two
226 operands fields are identical. The assembler should call the
227 insert function with any op value. The disassembler should call
228 the extract function, ignore the return value, and check the value
229 placed in the valid argument. */
230 #define PPC_OPERAND_FAKE (0x4)
231
232 /* The next operand should be wrapped in parentheses rather than
233 separated from this one by a comma. This is used for the load and
234 store instructions which want their operands to look like
235 reg,displacement(reg)
236 */
237 #define PPC_OPERAND_PARENS (0x8)
238
239 /* This operand may use the symbolic names for the CR fields, which
240 are
241 lt 0 gt 1 eq 2 so 3 un 3
242 cr0 0 cr1 1 cr2 2 cr3 3
243 cr4 4 cr5 5 cr6 6 cr7 7
244 These may be combined arithmetically, as in cr2*4+gt. These are
245 only supported on the PowerPC, not the POWER. */
246 #define PPC_OPERAND_CR (0x10)
247
248 /* This operand names a register. The disassembler uses this to print
249 register names with a leading 'r'. */
250 #define PPC_OPERAND_GPR (0x20)
251
252 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
253 #define PPC_OPERAND_GPR_0 (0x40)
254
255 /* This operand names a floating point register. The disassembler
256 prints these with a leading 'f'. */
257 #define PPC_OPERAND_FPR (0x80)
258
259 /* This operand is a relative branch displacement. The disassembler
260 prints these symbolically if possible. */
261 #define PPC_OPERAND_RELATIVE (0x100)
262
263 /* This operand is an absolute branch address. The disassembler
264 prints these symbolically if possible. */
265 #define PPC_OPERAND_ABSOLUTE (0x200)
266
267 /* This operand is optional, and is zero if omitted. This is used for
268 example, in the optional BF field in the comparison instructions. The
269 assembler must count the number of operands remaining on the line,
270 and the number of operands remaining for the opcode, and decide
271 whether this operand is present or not. The disassembler should
272 print this operand out only if it is not zero. */
273 #define PPC_OPERAND_OPTIONAL (0x400)
274
275 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
276 is omitted, then for the next operand use this operand value plus
277 1, ignoring the next operand field for the opcode. This wretched
278 hack is needed because the Power rotate instructions can take
279 either 4 or 5 operands. The disassembler should print this operand
280 out regardless of the PPC_OPERAND_OPTIONAL field. */
281 #define PPC_OPERAND_NEXT (0x800)
282
283 /* This operand should be regarded as a negative number for the
284 purposes of overflow checking (i.e., the normal most negative
285 number is disallowed and one more than the normal most positive
286 number is allowed). This flag will only be set for a signed
287 operand. */
288 #define PPC_OPERAND_NEGATIVE (0x1000)
289
290 /* This operand names a vector unit register. The disassembler
291 prints these with a leading 'v'. */
292 #define PPC_OPERAND_VR (0x2000)
293
294 /* This operand is for the DS field in a DS form instruction. */
295 #define PPC_OPERAND_DS (0x4000)
296
297 /* This operand is for the DQ field in a DQ form instruction. */
298 #define PPC_OPERAND_DQ (0x8000)
299
300 /* Valid range of operand is 0..n rather than 0..n-1. */
301 #define PPC_OPERAND_PLUS1 (0x10000)
302 \f
303 /* The POWER and PowerPC assemblers use a few macros. We keep them
304 with the operands table for simplicity. The macro table is an
305 array of struct powerpc_macro. */
306
307 struct powerpc_macro
308 {
309 /* The macro name. */
310 const char *name;
311
312 /* The number of operands the macro takes. */
313 unsigned int operands;
314
315 /* One bit flags for the opcode. These are used to indicate which
316 specific processors support the instructions. The values are the
317 same as those for the struct powerpc_opcode flags field. */
318 unsigned long flags;
319
320 /* A format string to turn the macro into a normal instruction.
321 Each %N in the string is replaced with operand number N (zero
322 based). */
323 const char *format;
324 };
325
326 extern const struct powerpc_macro powerpc_macros[];
327 extern const int powerpc_num_macros;
328
329 #endif /* PPC_H */
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