include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright (C) 1994-2015 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 typedef uint64_t ppc_cpu_t;
  28
  29 /* The opcode table is an array of struct powerpc_opcode.  */
  30
  31 struct powerpc_opcode
  32 {
  33   /* The opcode name.  */
  34   const char *name;
  35
  36   /* The opcode itself.  Those bits which will be filled in with
  37      operands are zeroes.  */
  38   unsigned long opcode;
  39
  40   /* The opcode mask.  This is used by the disassembler.  This is a
  41      mask containing ones indicating those bits which must match the
  42      opcode field, and zeroes indicating those bits which need not
  43      match (and are presumably filled in by operands).  */
  44   unsigned long mask;
  45
  46   /* One bit flags for the opcode.  These are used to indicate which
  47      specific processors support the instructions.  The defined values
  48      are listed below.  */
  49   ppc_cpu_t flags;
  50
  51   /* One bit flags for the opcode.  These are used to indicate which
  52      specific processors no longer support the instructions.  The defined
  53      values are listed below.  */
  54   ppc_cpu_t deprecated;
  55
  56   /* An array of operand codes.  Each code is an index into the
  57      operand table.  They appear in the order which the operands must
  58      appear in assembly code, and are terminated by a zero.  */
  59   unsigned char operands[8];
  60 };
  61
  62 /* The table itself is sorted by major opcode number, and is otherwise
  63    in the order in which the disassembler should consider
  64    instructions.  */
  65 extern const struct powerpc_opcode powerpc_opcodes[];
  66 extern const int powerpc_num_opcodes;
  67 extern const struct powerpc_opcode vle_opcodes[];
  68 extern const int vle_num_opcodes;
  69
  70 /* Values defined for the flags field of a struct powerpc_opcode.  */
  71
  72 /* Opcode is defined for the PowerPC architecture.  */
  73 #define PPC_OPCODE_PPC                   1
  74
  75 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  76 #define PPC_OPCODE_POWER                 2
  77
  78 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  79 #define PPC_OPCODE_POWER2                4
  80
  81 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  82    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  83    but it also supports many additional POWER instructions.  */
  84 #define PPC_OPCODE_601                   8
  85
  86 /* Opcode is supported in both the Power and PowerPC architectures
  87    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
  88    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
  89    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
  90    between POWER and POWERPC.  */
  91 #define PPC_OPCODE_COMMON             0x10
  92
  93 /* Opcode is supported for any Power or PowerPC platform (this is
  94    for the assembler's -many option, and it eliminates duplicates).  */
  95 #define PPC_OPCODE_ANY                0x20
  96
  97 /* Opcode is only defined on 64 bit architectures.  */
  98 #define PPC_OPCODE_64                 0x40
  99
 100 /* Opcode is supported as part of the 64-bit bridge.  */
 101 #define PPC_OPCODE_64_BRIDGE          0x80
 102
 103 /* Opcode is supported by Altivec Vector Unit */
 104 #define PPC_OPCODE_ALTIVEC           0x100
 105
 106 /* Opcode is supported by PowerPC 403 processor.  */
 107 #define PPC_OPCODE_403               0x200
 108
 109 /* Opcode is supported by PowerPC BookE processor.  */
 110 #define PPC_OPCODE_BOOKE             0x400
 111
 112 /* Opcode is supported by PowerPC 440 processor.  */
 113 #define PPC_OPCODE_440               0x800
 114
 115 /* Opcode is only supported by Power4 architecture.  */
 116 #define PPC_OPCODE_POWER4           0x1000
 117
 118 /* Opcode is only supported by Power7 architecture.  */
 119 #define PPC_OPCODE_POWER7           0x2000
 120
 121 /* Opcode is only supported by e500x2 Core.  */
 122 #define PPC_OPCODE_SPE              0x4000
 123
 124 /* Opcode is supported by e500x2 Integer select APU.  */
 125 #define PPC_OPCODE_ISEL             0x8000
 126
 127 /* Opcode is an e500 SPE floating point instruction.  */
 128 #define PPC_OPCODE_EFS             0x10000
 129
 130 /* Opcode is supported by branch locking APU.  */
 131 #define PPC_OPCODE_BRLOCK          0x20000
 132
 133 /* Opcode is supported by performance monitor APU.  */
 134 #define PPC_OPCODE_PMR             0x40000
 135
 136 /* Opcode is supported by cache locking APU.  */
 137 #define PPC_OPCODE_CACHELCK        0x80000
 138
 139 /* Opcode is supported by machine check APU.  */
 140 #define PPC_OPCODE_RFMCI          0x100000
 141
 142 /* Opcode is only supported by Power5 architecture.  */
 143 #define PPC_OPCODE_POWER5         0x200000
 144
 145 /* Opcode is supported by PowerPC e300 family.  */
 146 #define PPC_OPCODE_E300           0x400000
 147
 148 /* Opcode is only supported by Power6 architecture.  */
 149 #define PPC_OPCODE_POWER6         0x800000
 150
 151 /* Opcode is only supported by PowerPC Cell family.  */
 152 #define PPC_OPCODE_CELL          0x1000000
 153
 154 /* Opcode is supported by CPUs with paired singles support.  */
 155 #define PPC_OPCODE_PPCPS         0x2000000
 156
 157 /* Opcode is supported by Power E500MC */
 158 #define PPC_OPCODE_E500MC        0x4000000
 159
 160 /* Opcode is supported by PowerPC 405 processor.  */
 161 #define PPC_OPCODE_405           0x8000000
 162
 163 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 164 #define PPC_OPCODE_VSX          0x10000000
 165
 166 /* Opcode is supported by A2.  */
 167 #define PPC_OPCODE_A2           0x20000000
 168
 169 /* Opcode is supported by PowerPC 476 processor.  */
 170 #define PPC_OPCODE_476          0x40000000
 171
 172 /* Opcode is supported by AppliedMicro Titan core */
 173 #define PPC_OPCODE_TITAN        0x80000000
 174
 175 /* Opcode which is supported by the e500 family */
 176 #define PPC_OPCODE_E500        0x100000000ull
 177
 178 /* Opcode is supported by Extended Altivec Vector Unit */
 179 #define PPC_OPCODE_ALTIVEC2    0x200000000ull
 180
 181 /* Opcode is supported by Power E6500 */
 182 #define PPC_OPCODE_E6500       0x400000000ull
 183
 184 /* Opcode is supported by Thread management APU */
 185 #define PPC_OPCODE_TMR         0x800000000ull
 186
 187 /* Opcode which is supported by the VLE extension.  */
 188 #define PPC_OPCODE_VLE        0x1000000000ull
 189
 190 /* Opcode is only supported by Power8 architecture.  */
 191 #define PPC_OPCODE_POWER8     0x2000000000ull
 192
 193 /* Opcode which is supported by the Hardware Transactional Memory extension.  */
 194 /* Currently, this is the same as the POWER8 mask.  If another cpu comes out
 195    that isn't a superset of POWER8, we can define this to its own mask.  */
 196 #define PPC_OPCODE_HTM        PPC_OPCODE_POWER8
 197
 198 /* Opcode is supported by ppc750cl.  */
 199 #define PPC_OPCODE_750        0x4000000000ull
 200
 201 /* Opcode is supported by ppc7450.  */
 202 #define PPC_OPCODE_7450       0x8000000000ull
 203
 204 /* Opcode is supported by ppc821/850/860.  */
 205 #define PPC_OPCODE_860        0x10000000000ull
 206
 207 /* A macro to extract the major opcode from an instruction.  */
 208 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 209
 210 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
 211 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
 212
 213 /* A macro to extract the major opcode from a VLE instruction.  */
 214 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
 215
 216 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
 217 #define VLE_OP_TO_SEG(i) ((i) >> 1)
 218 \f
 219 /* The operands table is an array of struct powerpc_operand.  */
 220
 221 struct powerpc_operand
 222 {
 223   /* A bitmask of bits in the operand.  */
 224   unsigned int bitm;
 225
 226   /* The shift operation to be applied to the operand.  No shift
 227      is made if this is zero.  For positive values, the operand
 228      is shifted left by SHIFT.  For negative values, the operand
 229      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
 230      that BITM and SHIFT cannot be used to determine where the
 231      operand goes in the insn.  */
 232   int shift;
 233
 234   /* Insertion function.  This is used by the assembler.  To insert an
 235      operand value into an instruction, check this field.
 236
 237      If it is NULL, execute
 238          if (o->shift >= 0)
 239            i |= (op & o->bitm) << o->shift;
 240          else
 241            i |= (op & o->bitm) >> -o->shift;
 242      (i is the instruction which we are filling in, o is a pointer to
 243      this structure, and op is the operand value).
 244
 245      If this field is not NULL, then simply call it with the
 246      instruction and the operand value.  It will return the new value
 247      of the instruction.  If the ERRMSG argument is not NULL, then if
 248      the operand value is illegal, *ERRMSG will be set to a warning
 249      string (the operand will be inserted in any case).  If the
 250      operand value is legal, *ERRMSG will be unchanged (most operands
 251      can accept any value).  */
 252   unsigned long (*insert)
 253     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 254
 255   /* Extraction function.  This is used by the disassembler.  To
 256      extract this operand type from an instruction, check this field.
 257
 258      If it is NULL, compute
 259          if (o->shift >= 0)
 260            op = (i >> o->shift) & o->bitm;
 261          else
 262            op = (i << -o->shift) & o->bitm;
 263          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 264            sign_extend (op);
 265      (i is the instruction, o is a pointer to this structure, and op
 266      is the result).
 267
 268      If this field is not NULL, then simply call it with the
 269      instruction value.  It will return the value of the operand.  If
 270      the INVALID argument is not NULL, *INVALID will be set to
 271      non-zero if this operand type can not actually be extracted from
 272      this operand (i.e., the instruction does not match).  If the
 273      operand is valid, *INVALID will not be changed.  */
 274   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 275
 276   /* One bit syntax flags.  */
 277   unsigned long flags;
 278 };
 279
 280 /* Elements in the table are retrieved by indexing with values from
 281    the operands field of the powerpc_opcodes table.  */
 282
 283 extern const struct powerpc_operand powerpc_operands[];
 284 extern const unsigned int num_powerpc_operands;
 285
 286 /* Use with the shift field of a struct powerpc_operand to indicate
 287      that BITM and SHIFT cannot be used to determine where the operand
 288      goes in the insn.  */
 289 #define PPC_OPSHIFT_INV (-1 << 31)
 290
 291 /* Values defined for the flags field of a struct powerpc_operand.  */
 292
 293 /* This operand takes signed values.  */
 294 #define PPC_OPERAND_SIGNED (0x1)
 295
 296 /* This operand takes signed values, but also accepts a full positive
 297    range of values when running in 32 bit mode.  That is, if bits is
 298    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 299    this flag is ignored.  */
 300 #define PPC_OPERAND_SIGNOPT (0x2)
 301
 302 /* This operand does not actually exist in the assembler input.  This
 303    is used to support extended mnemonics such as mr, for which two
 304    operands fields are identical.  The assembler should call the
 305    insert function with any op value.  The disassembler should call
 306    the extract function, ignore the return value, and check the value
 307    placed in the valid argument.  */
 308 #define PPC_OPERAND_FAKE (0x4)
 309
 310 /* The next operand should be wrapped in parentheses rather than
 311    separated from this one by a comma.  This is used for the load and
 312    store instructions which want their operands to look like
 313        reg,displacement(reg)
 314    */
 315 #define PPC_OPERAND_PARENS (0x8)
 316
 317 /* This operand may use the symbolic names for the CR fields, which
 318    are
 319        lt  0    gt  1   eq  2   so  3   un  3
 320        cr0 0    cr1 1   cr2 2   cr3 3
 321        cr4 4    cr5 5   cr6 6   cr7 7
 322    These may be combined arithmetically, as in cr2*4+gt.  These are
 323    only supported on the PowerPC, not the POWER.  */
 324 #define PPC_OPERAND_CR_BIT (0x10)
 325
 326 /* This operand names a register.  The disassembler uses this to print
 327    register names with a leading 'r'.  */
 328 #define PPC_OPERAND_GPR (0x20)
 329
 330 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 331 #define PPC_OPERAND_GPR_0 (0x40)
 332
 333 /* This operand names a floating point register.  The disassembler
 334    prints these with a leading 'f'.  */
 335 #define PPC_OPERAND_FPR (0x80)
 336
 337 /* This operand is a relative branch displacement.  The disassembler
 338    prints these symbolically if possible.  */
 339 #define PPC_OPERAND_RELATIVE (0x100)
 340
 341 /* This operand is an absolute branch address.  The disassembler
 342    prints these symbolically if possible.  */
 343 #define PPC_OPERAND_ABSOLUTE (0x200)
 344
 345 /* This operand is optional, and is zero if omitted.  This is used for
 346    example, in the optional BF field in the comparison instructions.  The
 347    assembler must count the number of operands remaining on the line,
 348    and the number of operands remaining for the opcode, and decide
 349    whether this operand is present or not.  The disassembler should
 350    print this operand out only if it is not zero.  */
 351 #define PPC_OPERAND_OPTIONAL (0x400)
 352
 353 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 354    is omitted, then for the next operand use this operand value plus
 355    1, ignoring the next operand field for the opcode.  This wretched
 356    hack is needed because the Power rotate instructions can take
 357    either 4 or 5 operands.  The disassembler should print this operand
 358    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 359 #define PPC_OPERAND_NEXT (0x800)
 360
 361 /* This operand should be regarded as a negative number for the
 362    purposes of overflow checking (i.e., the normal most negative
 363    number is disallowed and one more than the normal most positive
 364    number is allowed).  This flag will only be set for a signed
 365    operand.  */
 366 #define PPC_OPERAND_NEGATIVE (0x1000)
 367
 368 /* This operand names a vector unit register.  The disassembler
 369    prints these with a leading 'v'.  */
 370 #define PPC_OPERAND_VR (0x2000)
 371
 372 /* This operand is for the DS field in a DS form instruction.  */
 373 #define PPC_OPERAND_DS (0x4000)
 374
 375 /* This operand is for the DQ field in a DQ form instruction.  */
 376 #define PPC_OPERAND_DQ (0x8000)
 377
 378 /* Valid range of operand is 0..n rather than 0..n-1.  */
 379 #define PPC_OPERAND_PLUS1 (0x10000)
 380
 381 /* Xilinx APU and FSL related operands */
 382 #define PPC_OPERAND_FSL (0x20000)
 383 #define PPC_OPERAND_FCR (0x40000)
 384 #define PPC_OPERAND_UDI (0x80000)
 385
 386 /* This operand names a vector-scalar unit register.  The disassembler
 387    prints these with a leading 'vs'.  */
 388 #define PPC_OPERAND_VSR (0x100000)
 389
 390 /* This is a CR FIELD that does not use symbolic names.  */
 391 #define PPC_OPERAND_CR_REG (0x200000)
 392
 393 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 394    is omitted, then the value it should use for the operand is stored
 395    in the SHIFT field of the immediatly following operand field.  */
 396 #define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
 397 \f
 398 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 399    with the operands table for simplicity.  The macro table is an
 400    array of struct powerpc_macro.  */
 401
 402 struct powerpc_macro
 403 {
 404   /* The macro name.  */
 405   const char *name;
 406
 407   /* The number of operands the macro takes.  */
 408   unsigned int operands;
 409
 410   /* One bit flags for the opcode.  These are used to indicate which
 411      specific processors support the instructions.  The values are the
 412      same as those for the struct powerpc_opcode flags field.  */
 413   ppc_cpu_t flags;
 414
 415   /* A format string to turn the macro into a normal instruction.
 416      Each %N in the string is replaced with operand number N (zero
 417      based).  */
 418   const char *format;
 419 };
 420
 421 extern const struct powerpc_macro powerpc_macros[];
 422 extern const int powerpc_num_macros;
 423
 424 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
 425
 426 static inline long
 427 ppc_optional_operand_value (const struct powerpc_operand *operand)
 428 {
 429   if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
 430     return (operand+1)->shift;
 431   return 0;
 432 }
 433
 434 #endif /* PPC_H */