include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   3    2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 typedef uint64_t ppc_cpu_t;
  28
  29 /* The opcode table is an array of struct powerpc_opcode.  */
  30
  31 struct powerpc_opcode
  32 {
  33   /* The opcode name.  */
  34   const char *name;
  35
  36   /* The opcode itself.  Those bits which will be filled in with
  37      operands are zeroes.  */
  38   unsigned long opcode;
  39
  40   /* The opcode mask.  This is used by the disassembler.  This is a
  41      mask containing ones indicating those bits which must match the
  42      opcode field, and zeroes indicating those bits which need not
  43      match (and are presumably filled in by operands).  */
  44   unsigned long mask;
  45
  46   /* One bit flags for the opcode.  These are used to indicate which
  47      specific processors support the instructions.  The defined values
  48      are listed below.  */
  49   ppc_cpu_t flags;
  50
  51   /* One bit flags for the opcode.  These are used to indicate which
  52      specific processors no longer support the instructions.  The defined
  53      values are listed below.  */
  54   ppc_cpu_t deprecated;
  55
  56   /* An array of operand codes.  Each code is an index into the
  57      operand table.  They appear in the order which the operands must
  58      appear in assembly code, and are terminated by a zero.  */
  59   unsigned char operands[8];
  60 };
  61
  62 /* The table itself is sorted by major opcode number, and is otherwise
  63    in the order in which the disassembler should consider
  64    instructions.  */
  65 extern const struct powerpc_opcode powerpc_opcodes[];
  66 extern const int powerpc_num_opcodes;
  67
  68 /* Values defined for the flags field of a struct powerpc_opcode.  */
  69
  70 /* Opcode is defined for the PowerPC architecture.  */
  71 #define PPC_OPCODE_PPC                   1
  72
  73 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  74 #define PPC_OPCODE_POWER                 2
  75
  76 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  77 #define PPC_OPCODE_POWER2                4
  78
  79 /* Opcode is only defined on 32 bit architectures.  */
  80 #define PPC_OPCODE_32                    8
  81
  82 /* Opcode is only defined on 64 bit architectures.  */
  83 #define PPC_OPCODE_64                 0x10
  84
  85 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  86    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  87    but it also supports many additional POWER instructions.  */
  88 #define PPC_OPCODE_601                0x20
  89
  90 /* Opcode is supported in both the Power and PowerPC architectures
  91    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  92 #define PPC_OPCODE_COMMON             0x40
  93
  94 /* Opcode is supported for any Power or PowerPC platform (this is
  95    for the assembler's -many option, and it eliminates duplicates).  */
  96 #define PPC_OPCODE_ANY                0x80
  97
  98 /* Opcode is supported as part of the 64-bit bridge.  */
  99 #define PPC_OPCODE_64_BRIDGE         0x100
 100
 101 /* Opcode is supported by Altivec Vector Unit */
 102 #define PPC_OPCODE_ALTIVEC           0x200
 103
 104 /* Opcode is supported by PowerPC 403 processor.  */
 105 #define PPC_OPCODE_403               0x400
 106
 107 /* Opcode is supported by PowerPC BookE processor.  */
 108 #define PPC_OPCODE_BOOKE             0x800
 109
 110 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 111 #define PPC_OPCODE_BOOKE64          0x1000
 112
 113 /* Opcode is supported by PowerPC 440 processor.  */
 114 #define PPC_OPCODE_440              0x2000
 115
 116 /* Opcode is only supported by Power4 architecture.  */
 117 #define PPC_OPCODE_POWER4           0x4000
 118
 119 /* Opcode is only supported by Power7 architecture.  */
 120 #define PPC_OPCODE_POWER7           0x8000
 121
 122 /* Opcode is only supported by POWERPC Classic architecture.  */
 123 #define PPC_OPCODE_CLASSIC         0x10000
 124
 125 /* Opcode is only supported by e500x2 Core.  */
 126 #define PPC_OPCODE_SPE             0x20000
 127
 128 /* Opcode is supported by e500x2 Integer select APU.  */
 129 #define PPC_OPCODE_ISEL            0x40000
 130
 131 /* Opcode is an e500 SPE floating point instruction.  */
 132 #define PPC_OPCODE_EFS             0x80000
 133
 134 /* Opcode is supported by branch locking APU.  */
 135 #define PPC_OPCODE_BRLOCK         0x100000
 136
 137 /* Opcode is supported by performance monitor APU.  */
 138 #define PPC_OPCODE_PMR            0x200000
 139
 140 /* Opcode is supported by cache locking APU.  */
 141 #define PPC_OPCODE_CACHELCK       0x400000
 142
 143 /* Opcode is supported by machine check APU.  */
 144 #define PPC_OPCODE_RFMCI          0x800000
 145
 146 /* Opcode is only supported by Power5 architecture.  */
 147 #define PPC_OPCODE_POWER5        0x1000000
 148
 149 /* Opcode is supported by PowerPC e300 family.  */
 150 #define PPC_OPCODE_E300          0x2000000
 151
 152 /* Opcode is only supported by Power6 architecture.  */
 153 #define PPC_OPCODE_POWER6        0x4000000
 154
 155 /* Opcode is only supported by PowerPC Cell family.  */
 156 #define PPC_OPCODE_CELL          0x8000000
 157
 158 /* Opcode is supported by CPUs with paired singles support.  */
 159 #define PPC_OPCODE_PPCPS         0x10000000
 160
 161 /* Opcode is supported by Power E500MC */
 162 #define PPC_OPCODE_E500MC        0x20000000
 163
 164 /* Opcode is supported by PowerPC 405 processor.  */
 165 #define PPC_OPCODE_405           0x40000000
 166
 167 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 168 #define PPC_OPCODE_VSX           0x80000000
 169
 170 /* Opcode is supported by A2.  */
 171 #define PPC_OPCODE_A2            0x100000000ULL
 172
 173 /* Opcode is supported by PowerPC 476 processor.  */
 174 #define PPC_OPCODE_476           0x200000000ULL
 175
 176 /* Opcode is supported by AppliedMicro Titan core */
 177 #define PPC_OPCODE_TITAN         0x400000000ULL
 178
 179 /* A macro to extract the major opcode from an instruction.  */
 180 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 181 \f
 182 /* The operands table is an array of struct powerpc_operand.  */
 183
 184 struct powerpc_operand
 185 {
 186   /* A bitmask of bits in the operand.  */
 187   unsigned int bitm;
 188
 189   /* How far the operand is left shifted in the instruction.
 190      -1 to indicate that BITM and SHIFT cannot be used to determine
 191      where the operand goes in the insn.  */
 192   int shift;
 193
 194   /* Insertion function.  This is used by the assembler.  To insert an
 195      operand value into an instruction, check this field.
 196
 197      If it is NULL, execute
 198          i |= (op & o->bitm) << o->shift;
 199      (i is the instruction which we are filling in, o is a pointer to
 200      this structure, and op is the operand value).
 201
 202      If this field is not NULL, then simply call it with the
 203      instruction and the operand value.  It will return the new value
 204      of the instruction.  If the ERRMSG argument is not NULL, then if
 205      the operand value is illegal, *ERRMSG will be set to a warning
 206      string (the operand will be inserted in any case).  If the
 207      operand value is legal, *ERRMSG will be unchanged (most operands
 208      can accept any value).  */
 209   unsigned long (*insert)
 210     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 211
 212   /* Extraction function.  This is used by the disassembler.  To
 213      extract this operand type from an instruction, check this field.
 214
 215      If it is NULL, compute
 216          op = (i >> o->shift) & o->bitm;
 217          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 218            sign_extend (op);
 219      (i is the instruction, o is a pointer to this structure, and op
 220      is the result).
 221
 222      If this field is not NULL, then simply call it with the
 223      instruction value.  It will return the value of the operand.  If
 224      the INVALID argument is not NULL, *INVALID will be set to
 225      non-zero if this operand type can not actually be extracted from
 226      this operand (i.e., the instruction does not match).  If the
 227      operand is valid, *INVALID will not be changed.  */
 228   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 229
 230   /* One bit syntax flags.  */
 231   unsigned long flags;
 232 };
 233
 234 /* Elements in the table are retrieved by indexing with values from
 235    the operands field of the powerpc_opcodes table.  */
 236
 237 extern const struct powerpc_operand powerpc_operands[];
 238 extern const unsigned int num_powerpc_operands;
 239
 240 /* Values defined for the flags field of a struct powerpc_operand.  */
 241
 242 /* This operand takes signed values.  */
 243 #define PPC_OPERAND_SIGNED (0x1)
 244
 245 /* This operand takes signed values, but also accepts a full positive
 246    range of values when running in 32 bit mode.  That is, if bits is
 247    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 248    this flag is ignored.  */
 249 #define PPC_OPERAND_SIGNOPT (0x2)
 250
 251 /* This operand does not actually exist in the assembler input.  This
 252    is used to support extended mnemonics such as mr, for which two
 253    operands fields are identical.  The assembler should call the
 254    insert function with any op value.  The disassembler should call
 255    the extract function, ignore the return value, and check the value
 256    placed in the valid argument.  */
 257 #define PPC_OPERAND_FAKE (0x4)
 258
 259 /* The next operand should be wrapped in parentheses rather than
 260    separated from this one by a comma.  This is used for the load and
 261    store instructions which want their operands to look like
 262        reg,displacement(reg)
 263    */
 264 #define PPC_OPERAND_PARENS (0x8)
 265
 266 /* This operand may use the symbolic names for the CR fields, which
 267    are
 268        lt  0    gt  1   eq  2   so  3   un  3
 269        cr0 0    cr1 1   cr2 2   cr3 3
 270        cr4 4    cr5 5   cr6 6   cr7 7
 271    These may be combined arithmetically, as in cr2*4+gt.  These are
 272    only supported on the PowerPC, not the POWER.  */
 273 #define PPC_OPERAND_CR (0x10)
 274
 275 /* This operand names a register.  The disassembler uses this to print
 276    register names with a leading 'r'.  */
 277 #define PPC_OPERAND_GPR (0x20)
 278
 279 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 280 #define PPC_OPERAND_GPR_0 (0x40)
 281
 282 /* This operand names a floating point register.  The disassembler
 283    prints these with a leading 'f'.  */
 284 #define PPC_OPERAND_FPR (0x80)
 285
 286 /* This operand is a relative branch displacement.  The disassembler
 287    prints these symbolically if possible.  */
 288 #define PPC_OPERAND_RELATIVE (0x100)
 289
 290 /* This operand is an absolute branch address.  The disassembler
 291    prints these symbolically if possible.  */
 292 #define PPC_OPERAND_ABSOLUTE (0x200)
 293
 294 /* This operand is optional, and is zero if omitted.  This is used for
 295    example, in the optional BF field in the comparison instructions.  The
 296    assembler must count the number of operands remaining on the line,
 297    and the number of operands remaining for the opcode, and decide
 298    whether this operand is present or not.  The disassembler should
 299    print this operand out only if it is not zero.  */
 300 #define PPC_OPERAND_OPTIONAL (0x400)
 301
 302 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 303    is omitted, then for the next operand use this operand value plus
 304    1, ignoring the next operand field for the opcode.  This wretched
 305    hack is needed because the Power rotate instructions can take
 306    either 4 or 5 operands.  The disassembler should print this operand
 307    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 308 #define PPC_OPERAND_NEXT (0x800)
 309
 310 /* This operand should be regarded as a negative number for the
 311    purposes of overflow checking (i.e., the normal most negative
 312    number is disallowed and one more than the normal most positive
 313    number is allowed).  This flag will only be set for a signed
 314    operand.  */
 315 #define PPC_OPERAND_NEGATIVE (0x1000)
 316
 317 /* This operand names a vector unit register.  The disassembler
 318    prints these with a leading 'v'.  */
 319 #define PPC_OPERAND_VR (0x2000)
 320
 321 /* This operand is for the DS field in a DS form instruction.  */
 322 #define PPC_OPERAND_DS (0x4000)
 323
 324 /* This operand is for the DQ field in a DQ form instruction.  */
 325 #define PPC_OPERAND_DQ (0x8000)
 326
 327 /* Valid range of operand is 0..n rather than 0..n-1.  */
 328 #define PPC_OPERAND_PLUS1 (0x10000)
 329
 330 /* Xilinx APU and FSL related operands */
 331 #define PPC_OPERAND_FSL (0x20000)
 332 #define PPC_OPERAND_FCR (0x40000)
 333 #define PPC_OPERAND_UDI (0x80000)
 334
 335 /* This operand names a vector-scalar unit register.  The disassembler
 336    prints these with a leading 'vs'.  */
 337 #define PPC_OPERAND_VSR (0x100000)
 338 \f
 339 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 340    with the operands table for simplicity.  The macro table is an
 341    array of struct powerpc_macro.  */
 342
 343 struct powerpc_macro
 344 {
 345   /* The macro name.  */
 346   const char *name;
 347
 348   /* The number of operands the macro takes.  */
 349   unsigned int operands;
 350
 351   /* One bit flags for the opcode.  These are used to indicate which
 352      specific processors support the instructions.  The values are the
 353      same as those for the struct powerpc_opcode flags field.  */
 354   ppc_cpu_t flags;
 355
 356   /* A format string to turn the macro into a normal instruction.
 357      Each %N in the string is replaced with operand number N (zero
 358      based).  */
 359   const char *format;
 360 };
 361
 362 extern const struct powerpc_macro powerpc_macros[];
 363 extern const int powerpc_num_macros;
 364
 365 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
 366
 367 #endif /* PPC_H */