include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995, 1999, 2000, 2001, 2002
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 /* The opcode table is an array of struct powerpc_opcode.  */
  26
  27 struct powerpc_opcode
  28 {
  29   /* The opcode name.  */
  30   const char *name;
  31
  32   /* The opcode itself.  Those bits which will be filled in with
  33      operands are zeroes.  */
  34   unsigned long opcode;
  35
  36   /* The opcode mask.  This is used by the disassembler.  This is a
  37      mask containing ones indicating those bits which must match the
  38      opcode field, and zeroes indicating those bits which need not
  39      match (and are presumably filled in by operands).  */
  40   unsigned long mask;
  41
  42   /* One bit flags for the opcode.  These are used to indicate which
  43      specific processors support the instructions.  The defined values
  44      are listed below.  */
  45   unsigned long flags;
  46
  47   /* An array of operand codes.  Each code is an index into the
  48      operand table.  They appear in the order which the operands must
  49      appear in assembly code, and are terminated by a zero.  */
  50   unsigned char operands[8];
  51 };
  52
  53 /* The table itself is sorted by major opcode number, and is otherwise
  54    in the order in which the disassembler should consider
  55    instructions.  */
  56 extern const struct powerpc_opcode powerpc_opcodes[];
  57 extern const int powerpc_num_opcodes;
  58
  59 /* Values defined for the flags field of a struct powerpc_opcode.  */
  60
  61 /* Opcode is defined for the PowerPC architecture.  */
  62 #define PPC_OPCODE_PPC (01)
  63
  64 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  65 #define PPC_OPCODE_POWER (02)
  66
  67 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  68 #define PPC_OPCODE_POWER2 (04)
  69
  70 /* Opcode is only defined on 32 bit architectures.  */
  71 #define PPC_OPCODE_32 (010)
  72
  73 /* Opcode is only defined on 64 bit architectures.  */
  74 #define PPC_OPCODE_64 (020)
  75
  76 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  77    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  78    but it also supports many additional POWER instructions.  */
  79 #define PPC_OPCODE_601 (040)
  80
  81 /* Opcode is supported in both the Power and PowerPC architectures
  82    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  83 #define PPC_OPCODE_COMMON (0100)
  84
  85 /* Opcode is supported for any Power or PowerPC platform (this is
  86    for the assembler's -many option, and it eliminates duplicates).  */
  87 #define PPC_OPCODE_ANY (0200)
  88
  89 /* Opcode is supported as part of the 64-bit bridge.  */
  90 #define PPC_OPCODE_64_BRIDGE (0400)
  91
  92 /* Opcode is supported by Altivec Vector Unit */
  93 #define PPC_OPCODE_ALTIVEC (01000)
  94
  95 /* Opcode is supported by PowerPC 403 processor.  */
  96 #define PPC_OPCODE_403 (02000)
  97
  98 /* Opcode is supported by PowerPC BookE processor.  */
  99 #define PPC_OPCODE_BOOKE (04000)
 100
 101 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 102 #define PPC_OPCODE_BOOKE64 (010000)
 103
 104 /* Opcode is only supported by Power4 architecture.  */
 105 #define PPC_OPCODE_POWER4 (020000)
 106
 107 /* Opcode isn't supported by Power4 architecture.  */
 108 #define PPC_OPCODE_NOPOWER4 (040000)
 109
 110 /* A macro to extract the major opcode from an instruction.  */
 111 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 112 \f
 113 /* The operands table is an array of struct powerpc_operand.  */
 114
 115 struct powerpc_operand
 116 {
 117   /* The number of bits in the operand.  */
 118   int bits;
 119
 120   /* How far the operand is left shifted in the instruction.  */
 121   int shift;
 122
 123   /* Insertion function.  This is used by the assembler.  To insert an
 124      operand value into an instruction, check this field.
 125
 126      If it is NULL, execute
 127          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 128      (i is the instruction which we are filling in, o is a pointer to
 129      this structure, and op is the opcode value; this assumes twos
 130      complement arithmetic).
 131
 132      If this field is not NULL, then simply call it with the
 133      instruction and the operand value.  It will return the new value
 134      of the instruction.  If the ERRMSG argument is not NULL, then if
 135      the operand value is illegal, *ERRMSG will be set to a warning
 136      string (the operand will be inserted in any case).  If the
 137      operand value is legal, *ERRMSG will be unchanged (most operands
 138      can accept any value).  */
 139   unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
 140                                    int dialect,
 141                                    const char **errmsg));
 142
 143   /* Extraction function.  This is used by the disassembler.  To
 144      extract this operand type from an instruction, check this field.
 145
 146      If it is NULL, compute
 147          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 148          if ((o->flags & PPC_OPERAND_SIGNED) != 0
 149              && (op & (1 << (o->bits - 1))) != 0)
 150            op -= 1 << o->bits;
 151      (i is the instruction, o is a pointer to this structure, and op
 152      is the result; this assumes twos complement arithmetic).
 153
 154      If this field is not NULL, then simply call it with the
 155      instruction value.  It will return the value of the operand.  If
 156      the INVALID argument is not NULL, *INVALID will be set to
 157      non-zero if this operand type can not actually be extracted from
 158      this operand (i.e., the instruction does not match).  If the
 159      operand is valid, *INVALID will not be changed.  */
 160   long (*extract) PARAMS ((unsigned long instruction, int dialect,
 161                            int *invalid));
 162
 163   /* One bit syntax flags.  */
 164   unsigned long flags;
 165 };
 166
 167 /* Elements in the table are retrieved by indexing with values from
 168    the operands field of the powerpc_opcodes table.  */
 169
 170 extern const struct powerpc_operand powerpc_operands[];
 171
 172 /* Values defined for the flags field of a struct powerpc_operand.  */
 173
 174 /* This operand takes signed values.  */
 175 #define PPC_OPERAND_SIGNED (01)
 176
 177 /* This operand takes signed values, but also accepts a full positive
 178    range of values when running in 32 bit mode.  That is, if bits is
 179    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 180    this flag is ignored.  */
 181 #define PPC_OPERAND_SIGNOPT (02)
 182
 183 /* This operand does not actually exist in the assembler input.  This
 184    is used to support extended mnemonics such as mr, for which two
 185    operands fields are identical.  The assembler should call the
 186    insert function with any op value.  The disassembler should call
 187    the extract function, ignore the return value, and check the value
 188    placed in the valid argument.  */
 189 #define PPC_OPERAND_FAKE (04)
 190
 191 /* The next operand should be wrapped in parentheses rather than
 192    separated from this one by a comma.  This is used for the load and
 193    store instructions which want their operands to look like
 194        reg,displacement(reg)
 195    */
 196 #define PPC_OPERAND_PARENS (010)
 197
 198 /* This operand may use the symbolic names for the CR fields, which
 199    are
 200        lt  0    gt  1   eq  2   so  3   un  3
 201        cr0 0    cr1 1   cr2 2   cr3 3
 202        cr4 4    cr5 5   cr6 6   cr7 7
 203    These may be combined arithmetically, as in cr2*4+gt.  These are
 204    only supported on the PowerPC, not the POWER.  */
 205 #define PPC_OPERAND_CR (020)
 206
 207 /* This operand names a register.  The disassembler uses this to print
 208    register names with a leading 'r'.  */
 209 #define PPC_OPERAND_GPR (040)
 210
 211 /* This operand names a floating point register.  The disassembler
 212    prints these with a leading 'f'.  */
 213 #define PPC_OPERAND_FPR (0100)
 214
 215 /* This operand is a relative branch displacement.  The disassembler
 216    prints these symbolically if possible.  */
 217 #define PPC_OPERAND_RELATIVE (0200)
 218
 219 /* This operand is an absolute branch address.  The disassembler
 220    prints these symbolically if possible.  */
 221 #define PPC_OPERAND_ABSOLUTE (0400)
 222
 223 /* This operand is optional, and is zero if omitted.  This is used for
 224    the optional BF and L fields in the comparison instructions.  The
 225    assembler must count the number of operands remaining on the line,
 226    and the number of operands remaining for the opcode, and decide
 227    whether this operand is present or not.  The disassembler should
 228    print this operand out only if it is not zero.  */
 229 #define PPC_OPERAND_OPTIONAL (01000)
 230
 231 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 232    is omitted, then for the next operand use this operand value plus
 233    1, ignoring the next operand field for the opcode.  This wretched
 234    hack is needed because the Power rotate instructions can take
 235    either 4 or 5 operands.  The disassembler should print this operand
 236    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 237 #define PPC_OPERAND_NEXT (02000)
 238
 239 /* This operand should be regarded as a negative number for the
 240    purposes of overflow checking (i.e., the normal most negative
 241    number is disallowed and one more than the normal most positive
 242    number is allowed).  This flag will only be set for a signed
 243    operand.  */
 244 #define PPC_OPERAND_NEGATIVE (04000)
 245
 246 /* This operand names a vector unit register.  The disassembler
 247    prints these with a leading 'v'.  */
 248 #define PPC_OPERAND_VR (010000)
 249
 250 /* This operand is for the DS field in a DS form instruction.  */
 251 #define PPC_OPERAND_DS (020000)
 252 \f
 253 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 254    with the operands table for simplicity.  The macro table is an
 255    array of struct powerpc_macro.  */
 256
 257 struct powerpc_macro
 258 {
 259   /* The macro name.  */
 260   const char *name;
 261
 262   /* The number of operands the macro takes.  */
 263   unsigned int operands;
 264
 265   /* One bit flags for the opcode.  These are used to indicate which
 266      specific processors support the instructions.  The values are the
 267      same as those for the struct powerpc_opcode flags field.  */
 268   unsigned long flags;
 269
 270   /* A format string to turn the macro into a normal instruction.
 271      Each %N in the string is replaced with operand number N (zero
 272      based).  */
 273   const char *format;
 274 };
 275
 276 extern const struct powerpc_macro powerpc_macros[];
 277 extern const int powerpc_num_macros;
 278
 279 #endif /* PPC_H */