include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 typedef uint64_t ppc_cpu_t;
  32
  33 /* The opcode table is an array of struct powerpc_opcode.  */
  34
  35 struct powerpc_opcode
  36 {
  37   /* The opcode name.  */
  38   const char *name;
  39
  40   /* The opcode itself.  Those bits which will be filled in with
  41      operands are zeroes.  */
  42   unsigned long opcode;
  43
  44   /* The opcode mask.  This is used by the disassembler.  This is a
  45      mask containing ones indicating those bits which must match the
  46      opcode field, and zeroes indicating those bits which need not
  47      match (and are presumably filled in by operands).  */
  48   unsigned long mask;
  49
  50   /* One bit flags for the opcode.  These are used to indicate which
  51      specific processors support the instructions.  The defined values
  52      are listed below.  */
  53   ppc_cpu_t flags;
  54
  55   /* One bit flags for the opcode.  These are used to indicate which
  56      specific processors no longer support the instructions.  The defined
  57      values are listed below.  */
  58   ppc_cpu_t deprecated;
  59
  60   /* An array of operand codes.  Each code is an index into the
  61      operand table.  They appear in the order which the operands must
  62      appear in assembly code, and are terminated by a zero.  */
  63   unsigned char operands[8];
  64 };
  65
  66 /* The table itself is sorted by major opcode number, and is otherwise
  67    in the order in which the disassembler should consider
  68    instructions.  */
  69 extern const struct powerpc_opcode powerpc_opcodes[];
  70 extern const int powerpc_num_opcodes;
  71 extern const struct powerpc_opcode vle_opcodes[];
  72 extern const int vle_num_opcodes;
  73
  74 /* Values defined for the flags field of a struct powerpc_opcode.  */
  75
  76 /* Opcode is defined for the PowerPC architecture.  */
  77 #define PPC_OPCODE_PPC                 0x1ull
  78
  79 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  80 #define PPC_OPCODE_POWER               0x2ull
  81
  82 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  83 #define PPC_OPCODE_POWER2              0x4ull
  84
  85 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  86    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  87    but it also supports many additional POWER instructions.  */
  88 #define PPC_OPCODE_601                 0x8ull
  89
  90 /* Opcode is supported in both the Power and PowerPC architectures
  91    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
  92    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
  93    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
  94    between POWER and POWERPC.  */
  95 #define PPC_OPCODE_COMMON             0x10ull
  96
  97 /* Opcode is supported for any Power or PowerPC platform (this is
  98    for the assembler's -many option, and it eliminates duplicates).  */
  99 #define PPC_OPCODE_ANY                0x20ull
 100
 101 /* Opcode is only defined on 64 bit architectures.  */
 102 #define PPC_OPCODE_64                 0x40ull
 103
 104 /* Opcode is supported as part of the 64-bit bridge.  */
 105 #define PPC_OPCODE_64_BRIDGE          0x80ull
 106
 107 /* Opcode is supported by Altivec Vector Unit */
 108 #define PPC_OPCODE_ALTIVEC           0x100ull
 109
 110 /* Opcode is supported by PowerPC 403 processor.  */
 111 #define PPC_OPCODE_403               0x200ull
 112
 113 /* Opcode is supported by PowerPC BookE processor.  */
 114 #define PPC_OPCODE_BOOKE             0x400ull
 115
 116 /* Opcode is supported by PowerPC 440 processor.  */
 117 #define PPC_OPCODE_440               0x800ull
 118
 119 /* Opcode is only supported by Power4 architecture.  */
 120 #define PPC_OPCODE_POWER4           0x1000ull
 121
 122 /* Opcode is only supported by Power7 architecture.  */
 123 #define PPC_OPCODE_POWER7           0x2000ull
 124
 125 /* Opcode is only supported by e500x2 Core.  */
 126 #define PPC_OPCODE_SPE              0x4000ull
 127
 128 /* Opcode is supported by e500x2 Integer select APU.  */
 129 #define PPC_OPCODE_ISEL             0x8000ull
 130
 131 /* Opcode is an e500 SPE floating point instruction.  */
 132 #define PPC_OPCODE_EFS             0x10000ull
 133
 134 /* Opcode is supported by branch locking APU.  */
 135 #define PPC_OPCODE_BRLOCK          0x20000ull
 136
 137 /* Opcode is supported by performance monitor APU.  */
 138 #define PPC_OPCODE_PMR             0x40000ull
 139
 140 /* Opcode is supported by cache locking APU.  */
 141 #define PPC_OPCODE_CACHELCK        0x80000ull
 142
 143 /* Opcode is supported by machine check APU.  */
 144 #define PPC_OPCODE_RFMCI          0x100000ull
 145
 146 /* Opcode is only supported by Power5 architecture.  */
 147 #define PPC_OPCODE_POWER5         0x200000ull
 148
 149 /* Opcode is supported by PowerPC e300 family.  */
 150 #define PPC_OPCODE_E300           0x400000ull
 151
 152 /* Opcode is only supported by Power6 architecture.  */
 153 #define PPC_OPCODE_POWER6         0x800000ull
 154
 155 /* Opcode is only supported by PowerPC Cell family.  */
 156 #define PPC_OPCODE_CELL          0x1000000ull
 157
 158 /* Opcode is supported by CPUs with paired singles support.  */
 159 #define PPC_OPCODE_PPCPS         0x2000000ull
 160
 161 /* Opcode is supported by Power E500MC */
 162 #define PPC_OPCODE_E500MC        0x4000000ull
 163
 164 /* Opcode is supported by PowerPC 405 processor.  */
 165 #define PPC_OPCODE_405           0x8000000ull
 166
 167 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 168 #define PPC_OPCODE_VSX          0x10000000ull
 169
 170 /* Opcode is supported by A2.  */
 171 #define PPC_OPCODE_A2           0x20000000ull
 172
 173 /* Opcode is supported by PowerPC 476 processor.  */
 174 #define PPC_OPCODE_476          0x40000000ull
 175
 176 /* Opcode is supported by AppliedMicro Titan core */
 177 #define PPC_OPCODE_TITAN        0x80000000ull
 178
 179 /* Opcode which is supported by the e500 family */
 180 #define PPC_OPCODE_E500        0x100000000ull
 181
 182 /* Opcode is supported by Power E6500 */
 183 #define PPC_OPCODE_E6500       0x400000000ull
 184
 185 /* Opcode is supported by Thread management APU */
 186 #define PPC_OPCODE_TMR         0x800000000ull
 187
 188 /* Opcode which is supported by the VLE extension.  */
 189 #define PPC_OPCODE_VLE        0x1000000000ull
 190
 191 /* Opcode is only supported by Power8 architecture.  */
 192 #define PPC_OPCODE_POWER8     0x2000000000ull
 193
 194 /* Opcode which is supported by the Hardware Transactional Memory extension.  */
 195 /* Currently, this is the same as the POWER8 mask.  If another cpu comes out
 196    that isn't a superset of POWER8, we can define this to its own mask.  */
 197 #define PPC_OPCODE_HTM        PPC_OPCODE_POWER8
 198
 199 /* Opcode is supported by ppc750cl.  */
 200 #define PPC_OPCODE_750        0x4000000000ull
 201
 202 /* Opcode is supported by ppc7450.  */
 203 #define PPC_OPCODE_7450       0x8000000000ull
 204
 205 /* Opcode is supported by ppc821/850/860.  */
 206 #define PPC_OPCODE_860       0x10000000000ull
 207
 208 /* Opcode is only supported by Power9 architecture.  */
 209 #define PPC_OPCODE_POWER9    0x20000000000ull
 210
 211 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
 212 #define PPC_OPCODE_VSX3      0x40000000000ull
 213
 214 /* Opcode is supported by e200z4.  */
 215 #define PPC_OPCODE_E200Z4    0x80000000000ull
 216
 217 /* Disassemble to instructions matching later in the opcode table
 218    with fewer "mask" bits set rather than the earlist match.  Fewer
 219    "mask" bits set imply a more general form of the opcode, in fact
 220    the underlying machine instruction.  */
 221 #define PPC_OPCODE_RAW      0x100000000000ull
 222
 223 /* A macro to extract the major opcode from an instruction.  */
 224 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 225
 226 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
 227 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
 228
 229 /* A macro to extract the major opcode from a VLE instruction.  */
 230 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
 231
 232 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
 233 #define VLE_OP_TO_SEG(i) ((i) >> 1)
 234 \f
 235 /* The operands table is an array of struct powerpc_operand.  */
 236
 237 struct powerpc_operand
 238 {
 239   /* A bitmask of bits in the operand.  */
 240   unsigned int bitm;
 241
 242   /* The shift operation to be applied to the operand.  No shift
 243      is made if this is zero.  For positive values, the operand
 244      is shifted left by SHIFT.  For negative values, the operand
 245      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
 246      that BITM and SHIFT cannot be used to determine where the
 247      operand goes in the insn.  */
 248   int shift;
 249
 250   /* Insertion function.  This is used by the assembler.  To insert an
 251      operand value into an instruction, check this field.
 252
 253      If it is NULL, execute
 254          if (o->shift >= 0)
 255            i |= (op & o->bitm) << o->shift;
 256          else
 257            i |= (op & o->bitm) >> -o->shift;
 258      (i is the instruction which we are filling in, o is a pointer to
 259      this structure, and op is the operand value).
 260
 261      If this field is not NULL, then simply call it with the
 262      instruction and the operand value.  It will return the new value
 263      of the instruction.  If the ERRMSG argument is not NULL, then if
 264      the operand value is illegal, *ERRMSG will be set to a warning
 265      string (the operand will be inserted in any case).  If the
 266      operand value is legal, *ERRMSG will be unchanged (most operands
 267      can accept any value).  */
 268   unsigned long (*insert)
 269     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 270
 271   /* Extraction function.  This is used by the disassembler.  To
 272      extract this operand type from an instruction, check this field.
 273
 274      If it is NULL, compute
 275          if (o->shift >= 0)
 276            op = (i >> o->shift) & o->bitm;
 277          else
 278            op = (i << -o->shift) & o->bitm;
 279          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 280            sign_extend (op);
 281      (i is the instruction, o is a pointer to this structure, and op
 282      is the result).
 283
 284      If this field is not NULL, then simply call it with the
 285      instruction value.  It will return the value of the operand.  If
 286      the INVALID argument is not NULL, *INVALID will be set to
 287      non-zero if this operand type can not actually be extracted from
 288      this operand (i.e., the instruction does not match).  If the
 289      operand is valid, *INVALID will not be changed.  */
 290   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 291
 292   /* One bit syntax flags.  */
 293   unsigned long flags;
 294 };
 295
 296 /* Elements in the table are retrieved by indexing with values from
 297    the operands field of the powerpc_opcodes table.  */
 298
 299 extern const struct powerpc_operand powerpc_operands[];
 300 extern const unsigned int num_powerpc_operands;
 301
 302 /* Use with the shift field of a struct powerpc_operand to indicate
 303      that BITM and SHIFT cannot be used to determine where the operand
 304      goes in the insn.  */
 305 #define PPC_OPSHIFT_INV (-1U << 31)
 306
 307 /* Values defined for the flags field of a struct powerpc_operand.
 308    Keep the register bits low:  They need to fit in an unsigned short.  */
 309
 310 /* This operand names a register.  The disassembler uses this to print
 311    register names with a leading 'r'.  */
 312 #define PPC_OPERAND_GPR (0x1)
 313
 314 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 315 #define PPC_OPERAND_GPR_0 (0x2)
 316
 317 /* This operand names a floating point register.  The disassembler
 318    prints these with a leading 'f'.  */
 319 #define PPC_OPERAND_FPR (0x4)
 320
 321 /* This operand names a vector unit register.  The disassembler
 322    prints these with a leading 'v'.  */
 323 #define PPC_OPERAND_VR (0x8)
 324
 325 /* This operand names a vector-scalar unit register.  The disassembler
 326    prints these with a leading 'vs'.  */
 327 #define PPC_OPERAND_VSR (0x10)
 328
 329 /* This operand may use the symbolic names for the CR fields (even
 330    without -mregnames), which are
 331        lt  0    gt  1   eq  2   so  3   un  3
 332        cr0 0    cr1 1   cr2 2   cr3 3
 333        cr4 4    cr5 5   cr6 6   cr7 7
 334    These may be combined arithmetically, as in cr2*4+gt.  These are
 335    only supported on the PowerPC, not the POWER.  */
 336 #define PPC_OPERAND_CR_BIT (0x20)
 337
 338 /* This is a CR FIELD that does not use symbolic names (unless
 339    -mregnames is in effect).  */
 340 #define PPC_OPERAND_CR_REG (0x40)
 341
 342 /* This operand names a special purpose register.  */
 343 #define PPC_OPERAND_SPR (0x80)
 344
 345 /* This operand names a paired-single graphics quantization register.  */
 346 #define PPC_OPERAND_GQR (0x100)
 347
 348 /* This operand is a relative branch displacement.  The disassembler
 349    prints these symbolically if possible.  */
 350 #define PPC_OPERAND_RELATIVE (0x200)
 351
 352 /* This operand is an absolute branch address.  The disassembler
 353    prints these symbolically if possible.  */
 354 #define PPC_OPERAND_ABSOLUTE (0x400)
 355
 356 /* This operand takes signed values.  */
 357 #define PPC_OPERAND_SIGNED (0x800)
 358
 359 /* This operand takes signed values, but also accepts a full positive
 360    range of values when running in 32 bit mode.  That is, if bits is
 361    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 362    this flag is ignored.  */
 363 #define PPC_OPERAND_SIGNOPT (0x1000)
 364
 365 /* The next operand should be wrapped in parentheses rather than
 366    separated from this one by a comma.  This is used for the load and
 367    store instructions which want their operands to look like
 368        reg,displacement(reg)
 369    */
 370 #define PPC_OPERAND_PARENS (0x2000)
 371
 372 /* This operand is for the DS field in a DS form instruction.  */
 373 #define PPC_OPERAND_DS (0x4000)
 374
 375 /* This operand is for the DQ field in a DQ form instruction.  */
 376 #define PPC_OPERAND_DQ (0x8000)
 377
 378 /* This operand should be regarded as a negative number for the
 379    purposes of overflow checking (i.e., the normal most negative
 380    number is disallowed and one more than the normal most positive
 381    number is allowed).  This flag will only be set for a signed
 382    operand.  */
 383 #define PPC_OPERAND_NEGATIVE (0x10000)
 384
 385 /* Valid range of operand is 0..n rather than 0..n-1.  */
 386 #define PPC_OPERAND_PLUS1 (0x20000)
 387
 388 /* This operand does not actually exist in the assembler input.  This
 389    is used to support extended mnemonics such as mr, for which two
 390    operands fields are identical.  The assembler should call the
 391    insert function with any op value.  The disassembler should call
 392    the extract function, ignore the return value, and check the value
 393    placed in the valid argument.  */
 394 #define PPC_OPERAND_FAKE (0x40000)
 395
 396 /* This operand is optional, and is zero if omitted.  This is used for
 397    example, in the optional BF field in the comparison instructions.  The
 398    assembler must count the number of operands remaining on the line,
 399    and the number of operands remaining for the opcode, and decide
 400    whether this operand is present or not.  The disassembler should
 401    print this operand out only if it is not zero.  */
 402 #define PPC_OPERAND_OPTIONAL (0x80000)
 403
 404 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 405    is omitted, then for the next operand use this operand value plus
 406    1, ignoring the next operand field for the opcode.  This wretched
 407    hack is needed because the Power rotate instructions can take
 408    either 4 or 5 operands.  The disassembler should print this operand
 409    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 410 #define PPC_OPERAND_NEXT (0x100000)
 411
 412 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 413    is omitted, then the value it should use for the operand is stored
 414    in the SHIFT field of the immediatly following operand field.  */
 415 #define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
 416
 417 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
 418    only optional when generating 32-bit code.  */
 419 #define PPC_OPERAND_OPTIONAL32 (0x400000)
 420
 421 /* Xilinx APU and FSL related operands */
 422 #define PPC_OPERAND_FSL (0x800000)
 423 #define PPC_OPERAND_FCR (0x1000000)
 424 #define PPC_OPERAND_UDI (0x2000000)
 425 \f
 426 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 427    with the operands table for simplicity.  The macro table is an
 428    array of struct powerpc_macro.  */
 429
 430 struct powerpc_macro
 431 {
 432   /* The macro name.  */
 433   const char *name;
 434
 435   /* The number of operands the macro takes.  */
 436   unsigned int operands;
 437
 438   /* One bit flags for the opcode.  These are used to indicate which
 439      specific processors support the instructions.  The values are the
 440      same as those for the struct powerpc_opcode flags field.  */
 441   ppc_cpu_t flags;
 442
 443   /* A format string to turn the macro into a normal instruction.
 444      Each %N in the string is replaced with operand number N (zero
 445      based).  */
 446   const char *format;
 447 };
 448
 449 extern const struct powerpc_macro powerpc_macros[];
 450 extern const int powerpc_num_macros;
 451
 452 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
 453
 454 static inline long
 455 ppc_optional_operand_value (const struct powerpc_operand *operand)
 456 {
 457   if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
 458     return (operand+1)->shift;
 459   return 0;
 460 }
 461
 462 /* PowerPC VLE insns.  */
 463 /* Form I16L, uses 16A relocs.  */
 464 #define E_OR2I_INSN             0x7000C000
 465 #define E_AND2I_DOT_INSN        0x7000C800
 466 #define E_OR2IS_INSN            0x7000D000
 467 #define E_LIS_INSN              0x7000E000
 468 #define E_AND2IS_DOT_INSN       0x7000E800
 469
 470 /* Form I16A, uses 16D relocs.  */
 471 #define E_ADD2I_DOT_INSN        0x70008800
 472 #define E_ADD2IS_INSN           0x70009000
 473 #define E_CMP16I_INSN           0x70009800
 474 #define E_MULL2I_INSN           0x7000A000
 475 #define E_CMPL16I_INSN          0x7000A800
 476 #define E_CMPH16I_INSN          0x7000B000
 477 #define E_CMPHL16I_INSN         0x7000B800
 478
 479 #ifdef __cplusplus
 480 }
 481 #endif
 482
 483 #endif /* PPC_H */