1 /* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version 3,
11 or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING3. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "bfd_stdint.h"
28 typedef uint64_t ppc_cpu_t
;
30 /* The opcode table is an array of struct powerpc_opcode. */
34 /* The opcode name. */
37 /* The opcode itself. Those bits which will be filled in with
38 operands are zeroes. */
41 /* The opcode mask. This is used by the disassembler. This is a
42 mask containing ones indicating those bits which must match the
43 opcode field, and zeroes indicating those bits which need not
44 match (and are presumably filled in by operands). */
47 /* One bit flags for the opcode. These are used to indicate which
48 specific processors support the instructions. The defined values
52 /* One bit flags for the opcode. These are used to indicate which
53 specific processors no longer support the instructions. The defined
54 values are listed below. */
57 /* An array of operand codes. Each code is an index into the
58 operand table. They appear in the order which the operands must
59 appear in assembly code, and are terminated by a zero. */
60 unsigned char operands
[8];
63 /* The table itself is sorted by major opcode number, and is otherwise
64 in the order in which the disassembler should consider
66 extern const struct powerpc_opcode powerpc_opcodes
[];
67 extern const int powerpc_num_opcodes
;
69 /* Values defined for the flags field of a struct powerpc_opcode. */
71 /* Opcode is defined for the PowerPC architecture. */
72 #define PPC_OPCODE_PPC 1
74 /* Opcode is defined for the POWER (RS/6000) architecture. */
75 #define PPC_OPCODE_POWER 2
77 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
78 #define PPC_OPCODE_POWER2 4
80 /* Opcode is only defined on 32 bit architectures. */
81 #define PPC_OPCODE_32 8
83 /* Opcode is only defined on 64 bit architectures. */
84 #define PPC_OPCODE_64 0x10
86 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
87 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
88 but it also supports many additional POWER instructions. */
89 #define PPC_OPCODE_601 0x20
91 /* Opcode is supported in both the Power and PowerPC architectures
92 (ie, compiler's -mcpu=common or assembler's -mcom). More than just
93 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
94 and PPC_OPCODE_POWER2 because many instructions changed mnemonics
95 between POWER and POWERPC. */
96 #define PPC_OPCODE_COMMON 0x40
98 /* Opcode is supported for any Power or PowerPC platform (this is
99 for the assembler's -many option, and it eliminates duplicates). */
100 #define PPC_OPCODE_ANY 0x80
102 /* Opcode is supported as part of the 64-bit bridge. */
103 #define PPC_OPCODE_64_BRIDGE 0x100
105 /* Opcode is supported by Altivec Vector Unit */
106 #define PPC_OPCODE_ALTIVEC 0x200
108 /* Opcode is supported by PowerPC 403 processor. */
109 #define PPC_OPCODE_403 0x400
111 /* Opcode is supported by PowerPC BookE processor. */
112 #define PPC_OPCODE_BOOKE 0x800
114 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
115 #define PPC_OPCODE_BOOKE64 0x1000
117 /* Opcode is supported by PowerPC 440 processor. */
118 #define PPC_OPCODE_440 0x2000
120 /* Opcode is only supported by Power4 architecture. */
121 #define PPC_OPCODE_POWER4 0x4000
123 /* Opcode is only supported by Power7 architecture. */
124 #define PPC_OPCODE_POWER7 0x8000
126 /* Opcode is only supported by POWERPC Classic architecture. */
127 #define PPC_OPCODE_CLASSIC 0x10000
129 /* Opcode is only supported by e500x2 Core. */
130 #define PPC_OPCODE_SPE 0x20000
132 /* Opcode is supported by e500x2 Integer select APU. */
133 #define PPC_OPCODE_ISEL 0x40000
135 /* Opcode is an e500 SPE floating point instruction. */
136 #define PPC_OPCODE_EFS 0x80000
138 /* Opcode is supported by branch locking APU. */
139 #define PPC_OPCODE_BRLOCK 0x100000
141 /* Opcode is supported by performance monitor APU. */
142 #define PPC_OPCODE_PMR 0x200000
144 /* Opcode is supported by cache locking APU. */
145 #define PPC_OPCODE_CACHELCK 0x400000
147 /* Opcode is supported by machine check APU. */
148 #define PPC_OPCODE_RFMCI 0x800000
150 /* Opcode is only supported by Power5 architecture. */
151 #define PPC_OPCODE_POWER5 0x1000000
153 /* Opcode is supported by PowerPC e300 family. */
154 #define PPC_OPCODE_E300 0x2000000
156 /* Opcode is only supported by Power6 architecture. */
157 #define PPC_OPCODE_POWER6 0x4000000
159 /* Opcode is only supported by PowerPC Cell family. */
160 #define PPC_OPCODE_CELL 0x8000000
162 /* Opcode is supported by CPUs with paired singles support. */
163 #define PPC_OPCODE_PPCPS 0x10000000
165 /* Opcode is supported by Power E500MC */
166 #define PPC_OPCODE_E500MC 0x20000000
168 /* Opcode is supported by PowerPC 405 processor. */
169 #define PPC_OPCODE_405 0x40000000
171 /* Opcode is supported by Vector-Scalar (VSX) Unit */
172 #define PPC_OPCODE_VSX 0x80000000
174 /* Opcode is supported by A2. */
175 #define PPC_OPCODE_A2 0x100000000ULL
177 /* Opcode is supported by PowerPC 476 processor. */
178 #define PPC_OPCODE_476 0x200000000ULL
180 /* Opcode is supported by AppliedMicro Titan core */
181 #define PPC_OPCODE_TITAN 0x400000000ULL
183 /* Opcode which is supported by the e500 family */
184 #define PPC_OPCODE_E500 0x800000000ULL
186 /* A macro to extract the major opcode from an instruction. */
187 #define PPC_OP(i) (((i) >> 26) & 0x3f)
189 /* The operands table is an array of struct powerpc_operand. */
191 struct powerpc_operand
193 /* A bitmask of bits in the operand. */
196 /* How far the operand is left shifted in the instruction.
197 -1 to indicate that BITM and SHIFT cannot be used to determine
198 where the operand goes in the insn. */
201 /* Insertion function. This is used by the assembler. To insert an
202 operand value into an instruction, check this field.
204 If it is NULL, execute
205 i |= (op & o->bitm) << o->shift;
206 (i is the instruction which we are filling in, o is a pointer to
207 this structure, and op is the operand value).
209 If this field is not NULL, then simply call it with the
210 instruction and the operand value. It will return the new value
211 of the instruction. If the ERRMSG argument is not NULL, then if
212 the operand value is illegal, *ERRMSG will be set to a warning
213 string (the operand will be inserted in any case). If the
214 operand value is legal, *ERRMSG will be unchanged (most operands
215 can accept any value). */
216 unsigned long (*insert
)
217 (unsigned long instruction
, long op
, ppc_cpu_t dialect
, const char **errmsg
);
219 /* Extraction function. This is used by the disassembler. To
220 extract this operand type from an instruction, check this field.
222 If it is NULL, compute
223 op = (i >> o->shift) & o->bitm;
224 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
226 (i is the instruction, o is a pointer to this structure, and op
229 If this field is not NULL, then simply call it with the
230 instruction value. It will return the value of the operand. If
231 the INVALID argument is not NULL, *INVALID will be set to
232 non-zero if this operand type can not actually be extracted from
233 this operand (i.e., the instruction does not match). If the
234 operand is valid, *INVALID will not be changed. */
235 long (*extract
) (unsigned long instruction
, ppc_cpu_t dialect
, int *invalid
);
237 /* One bit syntax flags. */
241 /* Elements in the table are retrieved by indexing with values from
242 the operands field of the powerpc_opcodes table. */
244 extern const struct powerpc_operand powerpc_operands
[];
245 extern const unsigned int num_powerpc_operands
;
247 /* Values defined for the flags field of a struct powerpc_operand. */
249 /* This operand takes signed values. */
250 #define PPC_OPERAND_SIGNED (0x1)
252 /* This operand takes signed values, but also accepts a full positive
253 range of values when running in 32 bit mode. That is, if bits is
254 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
255 this flag is ignored. */
256 #define PPC_OPERAND_SIGNOPT (0x2)
258 /* This operand does not actually exist in the assembler input. This
259 is used to support extended mnemonics such as mr, for which two
260 operands fields are identical. The assembler should call the
261 insert function with any op value. The disassembler should call
262 the extract function, ignore the return value, and check the value
263 placed in the valid argument. */
264 #define PPC_OPERAND_FAKE (0x4)
266 /* The next operand should be wrapped in parentheses rather than
267 separated from this one by a comma. This is used for the load and
268 store instructions which want their operands to look like
269 reg,displacement(reg)
271 #define PPC_OPERAND_PARENS (0x8)
273 /* This operand may use the symbolic names for the CR fields, which
275 lt 0 gt 1 eq 2 so 3 un 3
276 cr0 0 cr1 1 cr2 2 cr3 3
277 cr4 4 cr5 5 cr6 6 cr7 7
278 These may be combined arithmetically, as in cr2*4+gt. These are
279 only supported on the PowerPC, not the POWER. */
280 #define PPC_OPERAND_CR (0x10)
282 /* This operand names a register. The disassembler uses this to print
283 register names with a leading 'r'. */
284 #define PPC_OPERAND_GPR (0x20)
286 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
287 #define PPC_OPERAND_GPR_0 (0x40)
289 /* This operand names a floating point register. The disassembler
290 prints these with a leading 'f'. */
291 #define PPC_OPERAND_FPR (0x80)
293 /* This operand is a relative branch displacement. The disassembler
294 prints these symbolically if possible. */
295 #define PPC_OPERAND_RELATIVE (0x100)
297 /* This operand is an absolute branch address. The disassembler
298 prints these symbolically if possible. */
299 #define PPC_OPERAND_ABSOLUTE (0x200)
301 /* This operand is optional, and is zero if omitted. This is used for
302 example, in the optional BF field in the comparison instructions. The
303 assembler must count the number of operands remaining on the line,
304 and the number of operands remaining for the opcode, and decide
305 whether this operand is present or not. The disassembler should
306 print this operand out only if it is not zero. */
307 #define PPC_OPERAND_OPTIONAL (0x400)
309 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
310 is omitted, then for the next operand use this operand value plus
311 1, ignoring the next operand field for the opcode. This wretched
312 hack is needed because the Power rotate instructions can take
313 either 4 or 5 operands. The disassembler should print this operand
314 out regardless of the PPC_OPERAND_OPTIONAL field. */
315 #define PPC_OPERAND_NEXT (0x800)
317 /* This operand should be regarded as a negative number for the
318 purposes of overflow checking (i.e., the normal most negative
319 number is disallowed and one more than the normal most positive
320 number is allowed). This flag will only be set for a signed
322 #define PPC_OPERAND_NEGATIVE (0x1000)
324 /* This operand names a vector unit register. The disassembler
325 prints these with a leading 'v'. */
326 #define PPC_OPERAND_VR (0x2000)
328 /* This operand is for the DS field in a DS form instruction. */
329 #define PPC_OPERAND_DS (0x4000)
331 /* This operand is for the DQ field in a DQ form instruction. */
332 #define PPC_OPERAND_DQ (0x8000)
334 /* Valid range of operand is 0..n rather than 0..n-1. */
335 #define PPC_OPERAND_PLUS1 (0x10000)
337 /* Xilinx APU and FSL related operands */
338 #define PPC_OPERAND_FSL (0x20000)
339 #define PPC_OPERAND_FCR (0x40000)
340 #define PPC_OPERAND_UDI (0x80000)
342 /* This operand names a vector-scalar unit register. The disassembler
343 prints these with a leading 'vs'. */
344 #define PPC_OPERAND_VSR (0x100000)
346 /* The POWER and PowerPC assemblers use a few macros. We keep them
347 with the operands table for simplicity. The macro table is an
348 array of struct powerpc_macro. */
352 /* The macro name. */
355 /* The number of operands the macro takes. */
356 unsigned int operands
;
358 /* One bit flags for the opcode. These are used to indicate which
359 specific processors support the instructions. The values are the
360 same as those for the struct powerpc_opcode flags field. */
363 /* A format string to turn the macro into a normal instruction.
364 Each %N in the string is replaced with operand number N (zero
369 extern const struct powerpc_macro powerpc_macros
[];
370 extern const int powerpc_num_macros
;
372 extern ppc_cpu_t
ppc_parse_cpu (ppc_cpu_t
, const char *);