1 /* Opcode decoder for the Renesas RL78
2 Copyright (C) 2011-2017 Free Software Foundation, Inc.
3 Written by DJ Delorie <dj@redhat.com>
5 This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
22 /* The RL78 decoder in libopcodes is used by the simulator, gdb's
23 analyzer, and the disassembler. Given an opcode data source, it
24 decodes the next opcode into the following structures. */
26 #ifndef RL78_OPCODES_H_INCLUDED
27 #define RL78_OPCODES_H_INCLUDED
40 /* For the purposes of these structures, the RL78 registers are as
41 follows, despite most of these being memory-mapped and
45 /* The order of these matches the encodings. */
54 /* The order of these matches the encodings. */
86 RL78_Operand_None
= 0,
87 RL78_Operand_Immediate
, /* #addend */
88 RL78_Operand_Register
, /* reg */
89 RL78_Operand_Indirect
, /* [reg + reg2 + addend] */
90 RL78_Operand_Bit
, /* reg.bit */
91 RL78_Operand_BitIndirect
, /* [reg+reg2+addend].bit */
92 RL78_Operand_PreDec
, /* [--reg] = push */
93 RL78_Operand_PostInc
/* [reg++] = pop */
100 RLO_addc
, /* d += s + CY */
101 RLO_and
, /* d &= s (byte, word, bit) */
102 RLO_branch
, /* pc = d */
103 RLO_branch_cond
, /* pc = d if cond(src) */
104 RLO_branch_cond_clear
, /* pc = d if cond(src), and clear(src) */
107 RLO_cmp
, /* cmp d, s */
108 RLO_divhu
, /* DIVHU */
109 RLO_divwu
, /* DIVWU */
113 RLO_machu
, /* MACHU */
116 RLO_mulhu
, /* MULHU */
121 RLO_rol
, /* d <<= s, MSB to LSB and CY */
122 RLO_rolc
, /* d <<= s, MSB to CY, CY, to LSB */
123 RLO_ror
, /* d >>= s, LSB to MSB and CY */
124 RLO_rorc
, /* d >>= s, LSB to CY, CY, to MSB */
125 RLO_sar
, /* d >>= s, signed */
126 RLO_sel
, /* rb = s */
127 RLO_shr
, /* d >>= s, unsigned */
128 RLO_shl
, /* d <<= s */
129 RLO_skip
, /* skip next insn is cond(s) */
131 RLO_sub
, /* d -= s */
132 RLO_subc
, /* d -= s - CY */
133 RLO_xch
, /* swap d, s */
134 RLO_xor
, /* d ^= s */
138 RL78_Operand_Type type
;
140 RL78_Register reg
: 8;
141 RL78_Register reg2
: 8;
142 unsigned char bit_number
: 4;
143 unsigned char condition
: 3;
144 unsigned char use_es
: 1;
145 } RL78_Opcode_Operand
;
148 #define RL78_PSW_IE 0x80
149 #define RL78_PSW_Z 0x40
150 #define RL78_PSW_RBS1 0x20
151 #define RL78_PSW_AC 0x10
152 #define RL78_PSW_RBS0 0x08
153 #define RL78_PSW_ISP1 0x04
154 #define RL78_PSW_ISP0 0x02
155 #define RL78_PSW_CY 0x01
157 #define RL78_SFR_SP 0xffff8
158 #define RL78_SFR_PSW 0xffffa
159 #define RL78_SFR_CS 0xffffc
160 #define RL78_SFR_ES 0xffffd
161 #define RL78_SFR_PMC 0xffffe
162 #define RL78_SFR_MEM 0xfffff
167 RL78_Opcode_ID id
:24;
168 unsigned flags
:8; /* PSW mask, for side effects only */
172 /* By convention, these are destination, source. */
173 RL78_Opcode_Operand op
[2];
174 } RL78_Opcode_Decoded
;
176 int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded
*, int (*)(void *), void *, RL78_Dis_Isa
);
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