1 /* Opcode decoder for the Renesas RX
2 Copyright (C) 2008-2019 Free Software Foundation, Inc.
3 Written by DJ Delorie <dj@redhat.com>
5 This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
22 /* The RX decoder in libopcodes is used by the simulator, gdb's
23 analyzer, and the disassembler. Given an opcode data source,
24 it decodes the next opcode into the following structures. */
33 RX_Byte
, /* undefined extension */
36 RX_Word
, /* undefined extension */
49 RX_Operand_Immediate
, /* #addend */
50 RX_Operand_Register
, /* Rn */
51 RX_Operand_Indirect
, /* [Rn + addend] */
52 RX_Operand_Zero_Indirect
,/* [Rn] */
53 RX_Operand_Postinc
, /* [Rn+] */
54 RX_Operand_Predec
, /* [-Rn] */
55 RX_Operand_Condition
, /* eq, gtu, etc */
56 RX_Operand_Flag
, /* [UIOSZC] */
57 RX_Operand_TwoReg
, /* [Rn + scale*R2] */
58 RX_Operand_DoubleReg
, /* DRn */
59 RX_Operand_DoubleRegH
,/* DRHn */
60 RX_Operand_DoubleRegL
,/* DRLn */
61 RX_Operand_DoubleCReg
,/* DCRxx */
62 RX_Operand_DoubleCond
,/* UN/EQ/LE/LT */
68 RXO_mov
, /* d = s (signed) */
69 RXO_movbi
, /* d = [s,s2] (signed) */
70 RXO_movbir
, /* [s,s2] = d (signed) */
71 RXO_pushm
, /* s..s2 */
73 RXO_xchg
, /* s <-> d */
74 RXO_stcc
, /* d = s if cond(s2) */
75 RXO_rtsd
, /* rtsd, 1=imm, 2-0 = reg if reg type */
77 /* These are all either d OP= s or, if s2 is set, d = s OP s2. Note
78 that d may be "None". */
91 RXO_adc
, /* d = d + s + carry */
92 RXO_sbb
, /* d = d - s - ~carry */
93 RXO_abs
, /* d = |s| */
94 RXO_max
, /* d = max(d,s) */
95 RXO_min
, /* d = min(d,s) */
96 RXO_emul
, /* d:64 = d:32 * s */
97 RXO_emulu
, /* d:64 = d:32 * s (unsigned) */
99 RXO_rolc
, /* d <<= 1 through carry */
100 RXO_rorc
, /* d >>= 1 through carry*/
101 RXO_rotl
, /* d <<= #s without carry */
102 RXO_rotr
, /* d >>= #s without carry*/
103 RXO_revw
, /* d = revw(s) */
104 RXO_revl
, /* d = revl(s) */
105 RXO_branch
, /* pc = d if cond(s) */
106 RXO_branchrel
,/* pc += d if cond(s) */
107 RXO_jsr
, /* pc = d */
108 RXO_jsrrel
, /* pc += d */
138 RXO_sat
, /* sat(d) */
141 RXO_fadd
, /* d op= s */
150 RXO_bset
, /* d |= (1<<s) */
151 RXO_bclr
, /* d &= ~(1<<s) */
152 RXO_btst
, /* s & (1<<s2) */
153 RXO_bnot
, /* d ^= (1<<s) */
154 RXO_bmcc
, /* d<s> = cond(s2) */
156 RXO_clrpsw
, /* flag index in d */
157 RXO_setpsw
, /* flag index in d */
158 RXO_mvtipl
, /* new IPL in s */
162 RXO_rtd
, /* undocumented */
164 RXO_dbt
, /* undocumented */
165 RXO_int
, /* vector id in s */
169 RXO_sccnd
, /* d = cond(s) ? 1 : 0 */
217 /* Condition bitpatterns, as registers. */
234 #define RXC_always 14
239 RX_Operand_Type type
;
252 /* By convention, these are destination, source1, source2. */
253 RX_Opcode_Operand op
[3];
255 /* The logic here is:
256 newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s)
257 Only the O, S, Z, and C flags are affected. */
258 char flags_0
; /* This also clears out flags-to-be-set. */
263 /* Within the syntax, %c-style format specifiers are as follows:
266 %0 = operand[0] (destination)
267 %1 = operand[1] (source)
268 %2 = operand[2] (2nd source)
269 %s = operation size (b/w/l)
270 %SN = operand size [N] (N=0,1,2)
271 %aN = op[N] as an address (N=0,1,2)
273 Register numbers 0..15 are general registers. 16..31 are control
274 registers. 32..47 are condition codes. */
276 int rx_decode_opcode (unsigned long, RX_Opcode_Decoded
*, int (*)(void *), void *);
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