include/opcode/tic4x.h

   1 /* Table of opcodes for the Texas Instruments TMS320C[34]X family.
   2
   3    Copyright (c) 2002 Free Software Foundation.
   4
   5    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* FIXME:  Only allow floating point registers for floating point
  23    instructions.  Use another field in the instruction table?
  24    This field could also flag which instructions are valid for
  25    which architectures...
  26    e.g., OP_FP | OP_C40  or OP_C40_FP  */
  27
  28 #define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32)
  29 #define IS_CPU_C4X(v) ((v) ==  0 || (v) == 40 || (v) == 44)
  30
  31 /* Define some bitfield extraction/insertion macros.  */
  32 #define EXTR(inst, m, l)          ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
  33 #define EXTRU(inst, m, l)         EXTR ((unsigned long)(inst), (m), (l))
  34 #define EXTRS(inst, m, l)         EXTR ((long)(inst), (m), (l))
  35 #define INSERTU(inst, val, m, l)  (inst |= ((val) << (l)))
  36 #define INSERTS(inst, val, m, l)  INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l)
  37
  38 /* Define register numbers.  */
  39 typedef enum
  40   {
  41     REG_R0, REG_R1, REG_R2, REG_R3,
  42     REG_R4, REG_R5, REG_R6, REG_R7,
  43     REG_AR0, REG_AR1, REG_AR2, REG_AR3,
  44     REG_AR4, REG_AR5, REG_AR6, REG_AR7,
  45     REG_DP, REG_IR0, REG_IR1, REG_BK,
  46     REG_SP, REG_ST, REG_DIE, REG_IIE,
  47     REG_IIF, REG_RS, REG_RE, REG_RC,
  48     REG_R8, REG_R9, REG_R10, REG_R11,
  49     REG_IVTP, REG_TVTP
  50   }
  51 c4x_reg_t;
  52
  53 /* Note that the actual register numbers for IVTP is 0 and TVTP is 1.  */
  54
  55 #define REG_IE REG_DIE          /* C3x only */
  56 #define REG_IF REG_IIE          /* C3x only */
  57 #define REG_IOF REG_IIF         /* C3x only */
  58
  59 #define C3X_REG_MAX REG_RC
  60 #define C4X_REG_MAX REG_TVTP
  61
  62 /* Register table size including C4x expansion regs.  */
  63 #define REG_TABLE_SIZE (C4X_REG_MAX + 1)
  64
  65 struct c4x_register
  66 {
  67   char *        name;
  68   unsigned long regno;
  69 };
  70
  71 typedef struct c4x_register c4x_register_t;
  72
  73 /* We could store register synonyms here.  */
  74 static const c4x_register_t c3x_registers[] =
  75 {
  76   {"f0",  REG_R0},
  77   {"r0",  REG_R0},
  78   {"f1",  REG_R1},
  79   {"r1",  REG_R1},
  80   {"f2",  REG_R2},
  81   {"r2",  REG_R2},
  82   {"f3",  REG_R3},
  83   {"r3",  REG_R3},
  84   {"f4",  REG_R4},
  85   {"r4",  REG_R4},
  86   {"f5",  REG_R5},
  87   {"r5",  REG_R5},
  88   {"f6",  REG_R6},
  89   {"r6",  REG_R6},
  90   {"f7",  REG_R7},
  91   {"r7",  REG_R7},
  92   {"ar0", REG_AR0},
  93   {"ar1", REG_AR1},
  94   {"ar2", REG_AR2},
  95   {"ar3", REG_AR3},
  96   {"ar4", REG_AR4},
  97   {"ar5", REG_AR5},
  98   {"ar6", REG_AR6},
  99   {"ar7", REG_AR7},
 100   {"dp",  REG_DP},
 101   {"ir0", REG_IR0},
 102   {"ir1", REG_IR1},
 103   {"bk",  REG_BK},
 104   {"sp",  REG_SP},
 105   {"st",  REG_ST},
 106   {"ie",  REG_IE},
 107   {"if",  REG_IF},
 108   {"iof", REG_IOF},
 109   {"rs",  REG_RS},
 110   {"re",  REG_RE},
 111   {"rc",  REG_RC},
 112   {"", 0}
 113 };
 114
 115 const unsigned int c3x_num_registers = (((sizeof c3x_registers) / (sizeof c3x_registers[0])) - 1);
 116
 117 /* Define C4x registers in addition to C3x registers.  */
 118 static const c4x_register_t c4x_registers[] =
 119 {
 120   {"die", REG_DIE},             /* Clobbers C3x REG_IE */
 121   {"iie", REG_IIE},             /* Clobbers C3x REG_IF */
 122   {"iif", REG_IIF},             /* Clobbers C3x REG_IOF */
 123   {"f8",  REG_R8},
 124   {"r8",  REG_R8},
 125   {"f9",  REG_R9},
 126   {"r9",  REG_R9},
 127   {"f10", REG_R10},
 128   {"r10", REG_R10},
 129   {"f11", REG_R11},
 130   {"r11", REG_R11},
 131   {"ivtp", REG_IVTP},
 132   {"tvtp", REG_TVTP},
 133   {"", 0}
 134 };
 135
 136 const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);
 137
 138 /* Instruction template.  */
 139 struct c4x_inst
 140 {
 141   char *        name;
 142   unsigned long opcode;
 143   unsigned long opmask;
 144   char *        args;
 145 };
 146
 147 typedef struct c4x_inst c4x_inst_t;
 148
 149 /* B  condition             16--20
 150    C  condition             23--27
 151    ,  required arg follows
 152    ;  optional arg follows
 153    General addressing modes
 154    *  indirect               0--15
 155    #  direct (for ldp only)  0--15
 156    @  direct                 0--15
 157    F  short float immediate  0--15
 158    Q  register               0--15
 159    R  register              16--20
 160    S  short int immediate    0--15
 161    D  src and dst same reg
 162    Three operand addressing modes
 163    E  register               0--7
 164    G  register               8--15
 165    I  indirect(short)        0--7
 166    J  indirect(short)        8--15
 167    R  register              16--20
 168    W  short int (C4x)        0--7
 169    C  indirect(short) (C4x)  0--7
 170    O  indirect(short) (C4x)  8--15
 171    Parallel instruction addressing modes
 172    E  register               0--7
 173    G  register               8--15
 174    I  indirect(short)        0--7
 175    J  indirect(short)        8--15
 176    K  register              19--21
 177    L  register              22--24
 178    M  register (R2,R3)      22--22
 179    N  register (R0,R1)      23--23
 180    Misc. addressing modes
 181    A  address register      22--24
 182    B  unsigned integer       0--23  (absolute on C3x, relative on C4x)
 183    P  displacement (PC Rel)  0--15
 184    U  unsigned integer       0--15
 185    V  vector                 0--4   (C4x 0--8)
 186    T  integer (C4x stik)    16--20
 187    Y  address reg (C4x)     16--20
 188    X  expansion reg (C4x)    0--4
 189    Z  expansion reg (C4x)   16--20.  */
 190
 191 #define C4X_OPERANDS_MAX 7      /* Max number of operands for an inst.  */
 192 #define C4X_NAME_MAX 16         /* Max number of chars in parallel name.  */
 193
 194 /* General (two) operand group.  */
 195 #define G_F_r "F,R"
 196 #define G_I_r "S,R"
 197 #define G_L_r "U,R"
 198 #define G_Q_r "*,R"
 199 #define G_T_r "@,R"
 200 #define G_r_r "Q;R"
 201
 202 /* Three operand group (Type 1 with missing third operand).  */
 203 #define T_rr_ "E,G"
 204 #define T_rS_ "E,J"
 205 #define T_Sr_ "I,G"
 206 #define T_SS_ "I,J"
 207
 208 /* Three operand group (Type 2 with missing third operand).  */
 209 #define T_Jr_ "W,G"             /* C4x only */
 210 #define T_rJ_ "G,W"             /* C4x only (commutative insns only) */
 211 #define T_Rr_ "C,G"             /* C4x only */
 212 #define T_rR_ "G,C"             /* C4x only (commutative insns only) */
 213 #define T_JR_ "W,O"             /* C4x only */
 214 #define T_RJ_ "O,W"             /* C4x only (commutative insns only) */
 215 #define T_RR_ "C,O"             /* C4x only */
 216
 217 /* Three operand group (Type 1).  */
 218 #define T_rrr "E,G;R"
 219 #define T_Srr "E,J,R"
 220 #define T_rSr "I,G;R"
 221 #define T_SSr "I,J,R"
 222
 223 /* Three operand group (Type 2).  */
 224 #define T_Jrr "W,G;R"           /* C4x only */
 225 #define T_rJr "G,W,R"           /* C4x only (commutative insns only) */
 226 #define T_Rrr "C,G;R"           /* C4x only */
 227 #define T_rRr "G,C,R"           /* C4x only (commutative insns only) */
 228 #define T_JRr "W,O,R"           /* C4x only */
 229 #define T_RJr "O,W,R"           /* C4x only (commutative insns only) */
 230 #define T_RRr "C,O,R"           /* C4x only */
 231
 232 /* Parallel group (store || op).  */
 233 #define Q_rS_rSr "H,J|K,I,L"
 234 #define Q_rS_Sr  "H,J|I,L"
 235 #define Q_rS_Srr "H,J|I,K;L"
 236
 237 /* Parallel group (op || store).  */
 238 #define P_rSr_rS "K,I,L|H,J"
 239 #define P_Srr_rS "I,K;L|H,J"
 240 #define P_rS_rS  "L,I|H,J"
 241
 242 /* Parallel group (load || load).  */
 243 #define P_Sr_Sr "I,L|J,K"
 244 #define Q_Sr_Sr "J,K|I,L"
 245
 246 /* Parallel group (store || store).  */
 247 #define P_Sr_rS "I,L|H,J"
 248 #define Q_rS_rS "H,J|L,I"
 249
 250 /* Parallel group (multiply || add/sub).  */
 251 #define P_SSr_rrr "I,J,N|H,K;M" /* 00 (User manual transposes I,J) */
 252 #define P_Srr_rSr "J,K;N|H,I,M" /* 01 */
 253 #define P_rSr_rSr "K,J,N|H,I,M" /* 01 */
 254 #define P_rrr_SSr "H,K;N|I,J,M" /* 10 (User manual transposes H,K) */
 255 #define P_Srr_Srr "J,K;N|I,H;M" /* 11 */
 256 #define P_rSr_Srr "K,J,N|I,H;M" /* 11 */
 257
 258 #define Q_rrr_SSr "H,K;M|I,J,N" /* 00 (User manual transposes I,J) */
 259 #define Q_rSr_Srr "H,I,M|J,K;N" /* 01 */
 260 #define Q_rSr_rSr "H,I,M|K,J,N" /* 01 */
 261 #define Q_SSr_rrr "I,J,M|H,K;N" /* 10 (User manual transposes H,K) */
 262 #define Q_Srr_Srr "I,H;M|J,K;N" /* 11 */
 263 #define Q_Srr_rSr "I,H;M|K,J,N" /* 11 */
 264
 265 /* Define c3x opcodes for assembler and disassembler.  */
 266 static const c4x_inst_t c3x_insts[] =
 267 {
 268   /* Put synonyms after the desired forms in table so that they get
 269      overwritten in the lookup table.  The disassembler will thus
 270      print the `proper' mnemonics.  Note that the disassembler
 271      only decodes the 11 MSBs, so instructions like ldp @0x500 will
 272      be printed as ldiu 5, dp.  Note that with parallel instructions,
 273      the second part is executed before the first part, unless
 274      the sti1||sti2 form is used.  We also allow sti2||sti1
 275      which is equivalent to the default sti||sti form.
 276
 277      Put most common forms first to speed up assembler.
 278
 279      FIXME:  Add all the other parallel/load forms, like absf1_stf2
 280      Perhaps I should have used a few macros...especially with
 281      all the bloat after adding the C4x opcodes...too late now!  */
 282
 283     /* Parallel instructions.  */
 284   { "absf_stf",     0xc8000000, 0xfe000000, P_Sr_rS },
 285   { "absi_sti",     0xca000000, 0xfe000000, P_Sr_rS },
 286   { "addf_mpyf",    0x80000000, 0xff000000, Q_rrr_SSr },
 287   { "addf_mpyf",    0x81000000, 0xff000000, Q_rSr_Srr },
 288   { "addf_mpyf",    0x81000000, 0xff000000, Q_rSr_rSr },
 289   { "addf_mpyf",    0x82000000, 0xff000000, Q_SSr_rrr },
 290   { "addf_mpyf",    0x83000000, 0xff000000, Q_Srr_Srr },
 291   { "addf_mpyf",    0x83000000, 0xff000000, Q_Srr_rSr },
 292   { "addf3_mpyf3",  0x80000000, 0xff000000, Q_rrr_SSr },
 293   { "addf3_mpyf3",  0x81000000, 0xff000000, Q_rSr_Srr },
 294   { "addf3_mpyf3",  0x81000000, 0xff000000, Q_rSr_rSr },
 295   { "addf3_mpyf3",  0x82000000, 0xff000000, Q_SSr_rrr },
 296   { "addf3_mpyf3",  0x83000000, 0xff000000, Q_Srr_Srr },
 297   { "addf3_mpyf3",  0x83000000, 0xff000000, Q_Srr_rSr },
 298   { "addf_stf",     0xcc000000, 0xfe000000, P_Srr_rS },
 299   { "addf_stf",     0xcc000000, 0xfe000000, P_rSr_rS },
 300   { "addf3_stf",    0xcc000000, 0xfe000000, P_Srr_rS },
 301   { "addf3_stf",    0xcc000000, 0xfe000000, P_rSr_rS },
 302   { "addi_mpyi",    0x88000000, 0xff000000, Q_rrr_SSr },
 303   { "addi_mpyi",    0x89000000, 0xff000000, Q_rSr_Srr },
 304   { "addi_mpyi",    0x89000000, 0xff000000, Q_rSr_rSr },
 305   { "addi_mpyi",    0x8a000000, 0xff000000, Q_SSr_rrr },
 306   { "addi_mpyi",    0x8b000000, 0xff000000, Q_Srr_Srr },
 307   { "addi_mpyi",    0x8b000000, 0xff000000, Q_Srr_rSr },
 308   { "addi3_mpyi3",  0x88000000, 0xff000000, Q_rrr_SSr },
 309   { "addi3_mpyi3",  0x89000000, 0xff000000, Q_rSr_Srr },
 310   { "addi3_mpyi3",  0x89000000, 0xff000000, Q_rSr_rSr },
 311   { "addi3_mpyi3",  0x8a000000, 0xff000000, Q_SSr_rrr },
 312   { "addi3_mpyi3",  0x8b000000, 0xff000000, Q_Srr_Srr },
 313   { "addi3_mpyi3",  0x8b000000, 0xff000000, Q_Srr_rSr },
 314   { "addi_sti",     0xce000000, 0xfe000000, P_Srr_rS },
 315   { "addi_sti",     0xce000000, 0xfe000000, P_rSr_rS },
 316   { "addi3_sti",    0xce000000, 0xfe000000, P_Srr_rS },
 317   { "addi3_sti",    0xce000000, 0xfe000000, P_rSr_rS },
 318   { "and_sti",      0xd0000000, 0xfe000000, P_Srr_rS },
 319   { "and_sti",      0xd0000000, 0xfe000000, P_rSr_rS },
 320   { "and3_sti",     0xd0000000, 0xfe000000, P_Srr_rS },
 321   { "and3_sti",     0xd0000000, 0xfe000000, P_rSr_rS },
 322   { "ash_sti",      0xd2000000, 0xfe000000, P_rSr_rS },
 323   { "ash3_sti",     0xd2000000, 0xfe000000, P_rSr_rS },
 324   { "fix_sti",      0xd4000000, 0xfe000000, P_Sr_rS },
 325   { "float_stf",    0xd6000000, 0xfe000000, P_Sr_rS },
 326   { "ldf_ldf",      0xc4000000, 0xfe000000, P_Sr_Sr },
 327   { "ldf1_ldf2",    0xc4000000, 0xfe000000, Q_Sr_Sr }, /* synonym */
 328   { "ldf2_ldf1",    0xc4000000, 0xfe000000, P_Sr_Sr }, /* synonym */
 329   { "ldf_stf",      0xd8000000, 0xfe000000, P_Sr_rS },
 330   { "ldi_ldi",      0xc6000000, 0xfe000000, P_Sr_Sr },
 331   { "ldi1_ldi2",    0xc6000000, 0xfe000000, Q_Sr_Sr }, /* synonym  */
 332   { "ldi2_ldi1",    0xc6000000, 0xfe000000, P_Sr_Sr }, /* synonym  */
 333   { "ldi_sti",      0xda000000, 0xfe000000, P_Sr_rS },
 334   { "lsh_sti",      0xdc000000, 0xfe000000, P_rSr_rS },
 335   { "lsh3_sti",     0xdc000000, 0xfe000000, P_rSr_rS },
 336   { "mpyf_addf",    0x80000000, 0xff000000, P_SSr_rrr },
 337   { "mpyf_addf",    0x81000000, 0xff000000, P_Srr_rSr },
 338   { "mpyf_addf",    0x81000000, 0xff000000, P_rSr_rSr },
 339   { "mpyf_addf",    0x82000000, 0xff000000, P_rrr_SSr },
 340   { "mpyf_addf",    0x83000000, 0xff000000, P_Srr_Srr },
 341   { "mpyf_addf",    0x83000000, 0xff000000, P_rSr_Srr },
 342   { "mpyf3_addf3",  0x80000000, 0xff000000, P_SSr_rrr },
 343   { "mpyf3_addf3",  0x81000000, 0xff000000, P_Srr_rSr },
 344   { "mpyf3_addf3",  0x81000000, 0xff000000, P_rSr_rSr },
 345   { "mpyf3_addf3",  0x82000000, 0xff000000, P_rrr_SSr },
 346   { "mpyf3_addf3",  0x83000000, 0xff000000, P_Srr_Srr },
 347   { "mpyf3_addf3",  0x83000000, 0xff000000, P_rSr_Srr },
 348   { "mpyf_stf",     0xde000000, 0xfe000000, P_Srr_rS },
 349   { "mpyf_stf",     0xde000000, 0xfe000000, P_rSr_rS },
 350   { "mpyf3_stf",    0xde000000, 0xfe000000, P_Srr_rS },
 351   { "mpyf3_stf",    0xde000000, 0xfe000000, P_rSr_rS },
 352   { "mpyf_subf",    0x84000000, 0xff000000, P_SSr_rrr },
 353   { "mpyf_subf",    0x85000000, 0xff000000, P_Srr_rSr },
 354   { "mpyf_subf",    0x85000000, 0xff000000, P_rSr_rSr },
 355   { "mpyf_subf",    0x86000000, 0xff000000, P_rrr_SSr },
 356   { "mpyf_subf",    0x87000000, 0xff000000, P_Srr_Srr },
 357   { "mpyf_subf",    0x87000000, 0xff000000, P_rSr_Srr },
 358   { "mpyf3_subf3",  0x84000000, 0xff000000, P_SSr_rrr },
 359   { "mpyf3_subf3",  0x85000000, 0xff000000, P_Srr_rSr },
 360   { "mpyf3_subf3",  0x85000000, 0xff000000, P_rSr_rSr },
 361   { "mpyf3_subf3",  0x86000000, 0xff000000, P_rrr_SSr },
 362   { "mpyf3_subf3",  0x87000000, 0xff000000, P_Srr_Srr },
 363   { "mpyf3_subf3",  0x87000000, 0xff000000, P_rSr_Srr },
 364   { "mpyi_addi",    0x88000000, 0xff000000, P_SSr_rrr },
 365   { "mpyi_addi",    0x89000000, 0xff000000, P_Srr_rSr },
 366   { "mpyi_addi",    0x89000000, 0xff000000, P_rSr_rSr },
 367   { "mpyi_addi",    0x8a000000, 0xff000000, P_rrr_SSr },
 368   { "mpyi_addi",    0x8b000000, 0xff000000, P_Srr_Srr },
 369   { "mpyi_addi",    0x8b000000, 0xff000000, P_rSr_Srr },
 370   { "mpyi3_addi3",  0x88000000, 0xff000000, P_SSr_rrr },
 371   { "mpyi3_addi3",  0x89000000, 0xff000000, P_Srr_rSr },
 372   { "mpyi3_addi3",  0x89000000, 0xff000000, P_rSr_rSr },
 373   { "mpyi3_addi3",  0x8a000000, 0xff000000, P_rrr_SSr },
 374   { "mpyi3_addi3",  0x8b000000, 0xff000000, P_Srr_Srr },
 375   { "mpyi3_addi3",  0x8b000000, 0xff000000, P_rSr_Srr },
 376   { "mpyi_sti",     0xe0000000, 0xfe000000, P_Srr_rS },
 377   { "mpyi_sti",     0xe0000000, 0xfe000000, P_rSr_rS },
 378   { "mpyi3_sti",    0xe0000000, 0xfe000000, P_Srr_rS },
 379   { "mpyi3_sti",    0xe0000000, 0xfe000000, P_rSr_rS },
 380   { "mpyi_subi",    0x8c000000, 0xff000000, P_SSr_rrr },
 381   { "mpyi_subi",    0x8d000000, 0xff000000, P_Srr_rSr },
 382   { "mpyi_subi",    0x8d000000, 0xff000000, P_rSr_rSr },
 383   { "mpyi_subi",    0x8e000000, 0xff000000, P_rrr_SSr },
 384   { "mpyi_subi",    0x8f000000, 0xff000000, P_Srr_Srr },
 385   { "mpyi_subi",    0x8f000000, 0xff000000, P_rSr_Srr },
 386   { "mpyi3_subi3",  0x8c000000, 0xff000000, P_SSr_rrr },
 387   { "mpyi3_subi3",  0x8d000000, 0xff000000, P_Srr_rSr },
 388   { "mpyi3_subi3",  0x8d000000, 0xff000000, P_rSr_rSr },
 389   { "mpyi3_subi3",  0x8e000000, 0xff000000, P_rrr_SSr },
 390   { "mpyi3_subi3",  0x8f000000, 0xff000000, P_Srr_Srr },
 391   { "mpyi3_subi3",  0x8f000000, 0xff000000, P_rSr_Srr },
 392   { "negf_stf",     0xe2000000, 0xfe000000, P_Sr_rS },
 393   { "negi_sti",     0xe4000000, 0xfe000000, P_Sr_rS },
 394   { "not_sti",      0xe6000000, 0xfe000000, P_Sr_rS },
 395   { "or_sti",       0xe8000000, 0xfe000000, P_Srr_rS },
 396   { "or_sti",       0xe8000000, 0xfe000000, P_rSr_rS },
 397   { "or3_sti",      0xe8000000, 0xfe000000, P_Srr_rS },
 398   { "or3_sti",      0xe8000000, 0xfe000000, P_rSr_rS },
 399   { "stf_absf",     0xc8000000, 0xfe000000, Q_rS_Sr },
 400   { "stf_addf",     0xcc000000, 0xfe000000, Q_rS_Srr },
 401   { "stf_addf",     0xcc000000, 0xfe000000, Q_rS_rSr },
 402   { "stf_addf3",    0xcc000000, 0xfe000000, Q_rS_Srr },
 403   { "stf_addf3",    0xcc000000, 0xfe000000, Q_rS_rSr },
 404   { "stf_float",    0xd6000000, 0xfe000000, Q_rS_Sr },
 405   { "stf_mpyf",     0xde000000, 0xfe000000, Q_rS_Srr },
 406   { "stf_mpyf",     0xde000000, 0xfe000000, Q_rS_rSr },
 407   { "stf_mpyf3",    0xde000000, 0xfe000000, Q_rS_Srr },
 408   { "stf_mpyf3",    0xde000000, 0xfe000000, Q_rS_rSr },
 409   { "stf_ldf",      0xd8000000, 0xfe000000, Q_rS_Sr  },
 410   { "stf_negf",     0xe2000000, 0xfe000000, Q_rS_Sr },
 411   { "stf_stf",      0xc0000000, 0xfe000000, P_rS_rS },
 412   { "stf1_stf2",    0xc0000000, 0xfe000000, Q_rS_rS }, /* synonym */
 413   { "stf2_stf1",    0xc0000000, 0xfe000000, P_rS_rS }, /* synonym */
 414   { "stf_subf",     0xea000000, 0xfe000000, Q_rS_rSr },
 415   { "stf_subf3",    0xea000000, 0xfe000000, Q_rS_rSr },
 416   { "sti_absi",     0xca000000, 0xfe000000, Q_rS_Sr },
 417   { "sti_addi",     0xce000000, 0xfe000000, Q_rS_Srr },
 418   { "sti_addi",     0xce000000, 0xfe000000, Q_rS_rSr },
 419   { "sti_addi3",    0xce000000, 0xfe000000, Q_rS_Srr },
 420   { "sti_addi3",    0xce000000, 0xfe000000, Q_rS_rSr },
 421   { "sti_and",      0xd0000000, 0xfe000000, Q_rS_Srr },
 422   { "sti_and",      0xd0000000, 0xfe000000, Q_rS_rSr },
 423   { "sti_and3",     0xd0000000, 0xfe000000, Q_rS_Srr },
 424   { "sti_and3",     0xd0000000, 0xfe000000, Q_rS_rSr },
 425   { "sti_ash",      0xd2000000, 0xfe000000, Q_rS_rSr },
 426   { "sti_ash3",     0xd2000000, 0xfe000000, Q_rS_rSr },
 427   { "sti_fix",      0xd4000000, 0xfe000000, Q_rS_Sr },
 428   { "sti_ldi",      0xda000000, 0xfe000000, Q_rS_Sr },
 429   { "sti_lsh",      0xdc000000, 0xfe000000, Q_rS_rSr },
 430   { "sti_lsh3",     0xdc000000, 0xfe000000, Q_rS_rSr },
 431   { "sti_mpyi",     0xe0000000, 0xfe000000, Q_rS_Srr },
 432   { "sti_mpyi",     0xe0000000, 0xfe000000, Q_rS_rSr },
 433   { "sti_mpyi3",    0xe0000000, 0xfe000000, Q_rS_Srr },
 434   { "sti_mpyi3",    0xe0000000, 0xfe000000, Q_rS_rSr },
 435   { "sti_negi",     0xe4000000, 0xfe000000, Q_rS_Sr },
 436   { "sti_not",      0xe6000000, 0xfe000000, Q_rS_Sr },
 437   { "sti_or",       0xe8000000, 0xfe000000, Q_rS_Srr },
 438   { "sti_or",       0xe8000000, 0xfe000000, Q_rS_rSr },
 439   { "sti_or3",      0xe8000000, 0xfe000000, Q_rS_Srr },
 440   { "sti_or3",      0xe8000000, 0xfe000000, Q_rS_rSr },
 441   { "sti_sti",      0xc2000000, 0xfe000000, P_rS_rS },
 442   { "sti1_sti2",    0xc2000000, 0xfe000000, Q_rS_rS }, /* synonym */
 443   { "sti2_sti1",    0xc2000000, 0xfe000000, P_rS_rS }, /* synonym */
 444   { "sti_subi",     0xec000000, 0xfe000000, Q_rS_rSr },
 445   { "sti_subi3",    0xec000000, 0xfe000000, Q_rS_rSr },
 446   { "sti_xor",      0xee000000, 0xfe000000, Q_rS_Srr },
 447   { "sti_xor",      0xee000000, 0xfe000000, Q_rS_rSr },
 448   { "sti_xor3",     0xee000000, 0xfe000000, Q_rS_Srr },
 449   { "sti_xor3",     0xee000000, 0xfe000000, Q_rS_rSr },
 450   { "subf_mpyf",    0x84000000, 0xff000000, Q_rrr_SSr },
 451   { "subf_mpyf",    0x85000000, 0xff000000, Q_rSr_Srr },
 452   { "subf_mpyf",    0x85000000, 0xff000000, Q_rSr_rSr },
 453   { "subf_mpyf",    0x86000000, 0xff000000, Q_SSr_rrr },
 454   { "subf_mpyf",    0x87000000, 0xff000000, Q_Srr_Srr },
 455   { "subf_mpyf",    0x87000000, 0xff000000, Q_Srr_rSr },
 456   { "subf3_mpyf3",  0x84000000, 0xff000000, Q_rrr_SSr },
 457   { "subf3_mpyf3",  0x85000000, 0xff000000, Q_rSr_Srr },
 458   { "subf3_mpyf3",  0x85000000, 0xff000000, Q_rSr_rSr },
 459   { "subf3_mpyf3",  0x86000000, 0xff000000, Q_SSr_rrr },
 460   { "subf3_mpyf3",  0x87000000, 0xff000000, Q_Srr_Srr },
 461   { "subf3_mpyf3",  0x87000000, 0xff000000, Q_Srr_rSr },
 462   { "subf_stf",     0xea000000, 0xfe000000, P_rSr_rS },
 463   { "subf3_stf",    0xea000000, 0xfe000000, P_rSr_rS },
 464   { "subi_mpyi",    0x8c000000, 0xff000000, Q_rrr_SSr },
 465   { "subi_mpyi",    0x8d000000, 0xff000000, Q_rSr_Srr },
 466   { "subi_mpyi",    0x8d000000, 0xff000000, Q_rSr_rSr },
 467   { "subi_mpyi",    0x8e000000, 0xff000000, Q_SSr_rrr },
 468   { "subi_mpyi",    0x8f000000, 0xff000000, Q_Srr_Srr },
 469   { "subi_mpyi",    0x8f000000, 0xff000000, Q_Srr_rSr },
 470   { "subi3_mpyi3",  0x8c000000, 0xff000000, Q_rrr_SSr },
 471   { "subi3_mpyi3",  0x8d000000, 0xff000000, Q_rSr_Srr },
 472   { "subi3_mpyi3",  0x8d000000, 0xff000000, Q_rSr_rSr },
 473   { "subi3_mpyi3",  0x8e000000, 0xff000000, Q_SSr_rrr },
 474   { "subi3_mpyi3",  0x8f000000, 0xff000000, Q_Srr_Srr },
 475   { "subi3_mpyi3",  0x8f000000, 0xff000000, Q_Srr_rSr },
 476   { "subi_sti",     0xec000000, 0xfe000000, P_rSr_rS },
 477   { "subi3_sti",    0xec000000, 0xfe000000, P_rSr_rS },
 478   { "xor_sti",      0xee000000, 0xfe000000, P_Srr_rS },
 479   { "xor_sti",      0xee000000, 0xfe000000, P_rSr_rS },
 480   { "xor3_sti",     0xee000000, 0xfe000000, P_Srr_rS },
 481   { "xor3_sti",     0xee000000, 0xfe000000, P_rSr_rS },
 482
 483   { "absf",   0x00000000, 0xffe00000, G_r_r },
 484   { "absf",   0x00200000, 0xffe00000, G_T_r },
 485   { "absf",   0x00400000, 0xffe00000, G_Q_r },
 486   { "absf",   0x00600000, 0xffe00000, G_F_r },
 487   { "absi",   0x00800000, 0xffe00000, G_r_r },
 488   { "absi",   0x00a00000, 0xffe00000, G_T_r },
 489   { "absi",   0x00c00000, 0xffe00000, G_Q_r },
 490   { "absi",   0x00e00000, 0xffe00000, G_I_r },
 491   { "addc",   0x01000000, 0xffe00000, G_r_r },
 492   { "addc",   0x01200000, 0xffe00000, G_T_r },
 493   { "addc",   0x01400000, 0xffe00000, G_Q_r },
 494   { "addc",   0x01600000, 0xffe00000, G_I_r },
 495   { "addc",   0x20000000, 0xffe00000, T_rrr },
 496   { "addc",   0x20200000, 0xffe00000, T_Srr },
 497   { "addc",   0x20400000, 0xffe00000, T_rSr },
 498   { "addc",   0x20600000, 0xffe00000, T_SSr },
 499   { "addc",   0x30000000, 0xffe00000, T_Jrr }, /* C4x */
 500   { "addc",   0x30000000, 0xffe00000, T_rJr }, /* C4x */
 501   { "addc",   0x30200000, 0xffe00000, T_rRr }, /* C4x */
 502   { "addc",   0x30200000, 0xffe00000, T_Rrr }, /* C4x */
 503   { "addc",   0x30400000, 0xffe00000, T_JRr }, /* C4x */
 504   { "addc",   0x30400000, 0xffe00000, T_RJr }, /* C4x */
 505   { "addc",   0x30600000, 0xffe00000, T_RRr }, /* C4x */
 506   { "addc3",  0x20000000, 0xffe00000, T_rrr },
 507   { "addc3",  0x20200000, 0xffe00000, T_Srr },
 508   { "addc3",  0x20400000, 0xffe00000, T_rSr },
 509   { "addc3",  0x20600000, 0xffe00000, T_SSr },
 510   { "addc3",  0x30000000, 0xffe00000, T_Jrr }, /* C4x */
 511   { "addc3",  0x30000000, 0xffe00000, T_rJr }, /* C4x */
 512   { "addc3",  0x30200000, 0xffe00000, T_rRr }, /* C4x */
 513   { "addc3",  0x30200000, 0xffe00000, T_Rrr }, /* C4x */
 514   { "addc3",  0x30400000, 0xffe00000, T_JRr }, /* C4x */
 515   { "addc3",  0x30400000, 0xffe00000, T_RJr }, /* C4x */
 516   { "addc3",  0x30600000, 0xffe00000, T_RRr }, /* C4x */
 517   { "addf",   0x01800000, 0xffe00000, G_r_r },
 518   { "addf",   0x01a00000, 0xffe00000, G_T_r },
 519   { "addf",   0x01c00000, 0xffe00000, G_Q_r },
 520   { "addf",   0x01e00000, 0xffe00000, G_F_r },
 521   { "addf",   0x20800000, 0xffe00000, T_rrr },
 522   { "addf",   0x20a00000, 0xffe00000, T_Srr },
 523   { "addf",   0x20c00000, 0xffe00000, T_rSr },
 524   { "addf",   0x20e00000, 0xffe00000, T_SSr },
 525   { "addf",   0x30800000, 0xffe00000, T_Jrr }, /* C4x */
 526   { "addf",   0x30800000, 0xffe00000, T_rJr }, /* C4x */
 527   { "addf",   0x30a00000, 0xffe00000, T_rRr }, /* C4x */
 528   { "addf",   0x30a00000, 0xffe00000, T_Rrr }, /* C4x */
 529   { "addf",   0x30c00000, 0xffe00000, T_JRr }, /* C4x */
 530   { "addf",   0x30c00000, 0xffe00000, T_RJr }, /* C4x */
 531   { "addf",   0x30e00000, 0xffe00000, T_RRr }, /* C4x */
 532   { "addf3",  0x20800000, 0xffe00000, T_rrr },
 533   { "addf3",  0x20a00000, 0xffe00000, T_Srr },
 534   { "addf3",  0x20c00000, 0xffe00000, T_rSr },
 535   { "addf3",  0x20e00000, 0xffe00000, T_SSr },
 536   { "addf3",  0x30800000, 0xffe00000, T_Jrr }, /* C4x */
 537   { "addf3",  0x30800000, 0xffe00000, T_rJr }, /* C4x */
 538   { "addf3",  0x30a00000, 0xffe00000, T_rRr }, /* C4x */
 539   { "addf3",  0x30a00000, 0xffe00000, T_Rrr }, /* C4x */
 540   { "addf3",  0x30c00000, 0xffe00000, T_JRr }, /* C4x */
 541   { "addf3",  0x30c00000, 0xffe00000, T_RJr }, /* C4x */
 542   { "addf3",  0x30e00000, 0xffe00000, T_RRr }, /* C4x */
 543   { "addi",   0x02000000, 0xffe00000, G_r_r },
 544   { "addi",   0x02200000, 0xffe00000, G_T_r },
 545   { "addi",   0x02400000, 0xffe00000, G_Q_r },
 546   { "addi",   0x02600000, 0xffe00000, G_I_r },
 547   { "addi",   0x21000000, 0xffe00000, T_rrr },
 548   { "addi",   0x21200000, 0xffe00000, T_Srr },
 549   { "addi",   0x21400000, 0xffe00000, T_rSr },
 550   { "addi",   0x21600000, 0xffe00000, T_SSr },
 551   { "addi",   0x31000000, 0xffe00000, T_Jrr }, /* C4x */
 552   { "addi",   0x31000000, 0xffe00000, T_rJr }, /* C4x */
 553   { "addi",   0x31200000, 0xffe00000, T_rRr }, /* C4x */
 554   { "addi",   0x31200000, 0xffe00000, T_Rrr }, /* C4x */
 555   { "addi",   0x31400000, 0xffe00000, T_JRr }, /* C4x */
 556   { "addi",   0x31400000, 0xffe00000, T_RJr }, /* C4x */
 557   { "addi",   0x31600000, 0xffe00000, T_RRr }, /* C4x */
 558   { "addi3",  0x21000000, 0xffe00000, T_rrr },
 559   { "addi3",  0x21200000, 0xffe00000, T_Srr },
 560   { "addi3",  0x21400000, 0xffe00000, T_rSr },
 561   { "addi3",  0x21600000, 0xffe00000, T_SSr },
 562   { "addi3",  0x31000000, 0xffe00000, T_Jrr }, /* C4x */
 563   { "addi3",  0x31000000, 0xffe00000, T_rJr }, /* C4x */
 564   { "addi3",  0x31200000, 0xffe00000, T_rRr }, /* C4x */
 565   { "addi3",  0x31200000, 0xffe00000, T_Rrr }, /* C4x */
 566   { "addi3",  0x31400000, 0xffe00000, T_JRr }, /* C4x */
 567   { "addi3",  0x31400000, 0xffe00000, T_RJr }, /* C4x */
 568   { "addi3",  0x31600000, 0xffe00000, T_RRr }, /* C4x */
 569   { "and",    0x02800000, 0xffe00000, G_r_r },
 570   { "and",    0x02a00000, 0xffe00000, G_T_r },
 571   { "and",    0x02c00000, 0xffe00000, G_Q_r },
 572   { "and",    0x02e00000, 0xffe00000, G_L_r },
 573   { "and",    0x21800000, 0xffe00000, T_rrr },
 574   { "and",    0x21a00000, 0xffe00000, T_Srr },
 575   { "and",    0x21c00000, 0xffe00000, T_rSr },
 576   { "and",    0x21e00000, 0xffe00000, T_SSr },
 577   { "and",    0x31800000, 0xffe00000, T_Jrr }, /* C4x */
 578   { "and",    0x31800000, 0xffe00000, T_rJr }, /* C4x */
 579   { "and",    0x31a00000, 0xffe00000, T_rRr }, /* C4x */
 580   { "and",    0x31a00000, 0xffe00000, T_Rrr }, /* C4x */
 581   { "and",    0x31c00000, 0xffe00000, T_JRr }, /* C4x */
 582   { "and",    0x31c00000, 0xffe00000, T_RJr }, /* C4x */
 583   { "and",    0x31e00000, 0xffe00000, T_RRr }, /* C4x */
 584   { "and3",   0x21800000, 0xffe00000, T_rrr },
 585   { "and3",   0x21a00000, 0xffe00000, T_Srr },
 586   { "and3",   0x21c00000, 0xffe00000, T_rSr },
 587   { "and3",   0x21e00000, 0xffe00000, T_SSr },
 588   { "and3",   0x31800000, 0xffe00000, T_Jrr }, /* C4x */
 589   { "and3",   0x31800000, 0xffe00000, T_rJr }, /* C4x */
 590   { "and3",   0x31a00000, 0xffe00000, T_rRr }, /* C4x */
 591   { "and3",   0x31a00000, 0xffe00000, T_Rrr }, /* C4x */
 592   { "and3",   0x31c00000, 0xffe00000, T_JRr }, /* C4x */
 593   { "and3",   0x31c00000, 0xffe00000, T_RJr }, /* C4x */
 594   { "and3",   0x31e00000, 0xffe00000, T_RRr }, /* C4x */
 595   { "andn",   0x03000000, 0xffe00000, G_r_r },
 596   { "andn",   0x03200000, 0xffe00000, G_T_r },
 597   { "andn",   0x03400000, 0xffe00000, G_Q_r },
 598   { "andn",   0x03600000, 0xffe00000, G_L_r },
 599   { "andn",   0x22000000, 0xffe00000, T_rrr },
 600   { "andn",   0x22200000, 0xffe00000, T_Srr },
 601   { "andn",   0x22400000, 0xffe00000, T_rSr },
 602   { "andn",   0x22600000, 0xffe00000, T_SSr },
 603   { "andn",   0x32000000, 0xffe00000, T_Jrr }, /* C4x */
 604   { "andn",   0x32200000, 0xffe00000, T_Rrr }, /* C4x */
 605   { "andn",   0x32400000, 0xffe00000, T_JRr }, /* C4x */
 606   { "andn",   0x32600000, 0xffe00000, T_RRr }, /* C4x */
 607   { "andn3",  0x22000000, 0xffe00000, T_rrr },
 608   { "andn3",  0x22200000, 0xffe00000, T_Srr },
 609   { "andn3",  0x22400000, 0xffe00000, T_rSr },
 610   { "andn3",  0x22600000, 0xffe00000, T_SSr },
 611   { "andn3",  0x32000000, 0xffe00000, T_Jrr }, /* C4x */
 612   { "andn3",  0x32200000, 0xffe00000, T_Rrr }, /* C4x */
 613   { "andn3",  0x32400000, 0xffe00000, T_JRr }, /* C4x */
 614   { "andn3",  0x32600000, 0xffe00000, T_RRr }, /* C4x */
 615   { "ash",    0x03800000, 0xffe00000, G_r_r },
 616   { "ash",    0x03a00000, 0xffe00000, G_T_r },
 617   { "ash",    0x03c00000, 0xffe00000, G_Q_r },
 618   { "ash",    0x03e00000, 0xffe00000, G_I_r },
 619   { "ash",    0x22800000, 0xffe00000, T_rrr },
 620   { "ash",    0x22a00000, 0xffe00000, T_Srr },
 621   { "ash",    0x22c00000, 0xffe00000, T_rSr },
 622   { "ash",    0x22e00000, 0xffe00000, T_SSr },
 623   { "ash",    0x32800000, 0xffe00000, T_Jrr }, /* C4x */
 624   { "ash",    0x32a00000, 0xffe00000, T_Rrr }, /* C4x */
 625   { "ash",    0x32c00000, 0xffe00000, T_JRr }, /* C4x */
 626   { "ash",    0x32e00000, 0xffe00000, T_RRr }, /* C4x */
 627   { "ash3",   0x22800000, 0xffe00000, T_rrr },
 628   { "ash3",   0x22a00000, 0xffe00000, T_Srr },
 629   { "ash3",   0x22c00000, 0xffe00000, T_rSr },
 630   { "ash3",   0x22e00000, 0xffe00000, T_SSr },
 631   { "ash3",   0x32800000, 0xffe00000, T_Jrr }, /* C4x */
 632   { "ash3",   0x32a00000, 0xffe00000, T_Rrr }, /* C4x */
 633   { "ash3",   0x32c00000, 0xffe00000, T_JRr }, /* C4x */
 634   { "ash3",   0x32e00000, 0xffe00000, T_RRr }, /* C4x */
 635   { "bB",     0x68000000, 0xffe00000, "Q" },
 636   { "bB",     0x6a000000, 0xffe00000, "P" },
 637   { "b",      0x68000000, 0xffe00000, "Q" }, /* synonym for bu */
 638   { "b",      0x6a000000, 0xffe00000, "P" }, /* synonym for bu */
 639   { "bBd",    0x68200000, 0xffe00000, "Q" },
 640   { "bBd",    0x6a200000, 0xffe00000, "P" },
 641   { "bd",     0x68200000, 0xffe00000, "Q" }, /* synonym for bud */
 642   { "bd",     0x6a200000, 0xffe00000, "P" }, /* synonym for bud */
 643   { "br",     0x60000000, 0xff000000, "B" },
 644   { "brd",    0x61000000, 0xff000000, "B" },
 645   { "call",   0x62000000, 0xff000000, "B" },
 646   { "callB",  0x70000000, 0xffe00000, "Q" },
 647   { "callB",  0x72000000, 0xffe00000, "P" },
 648   { "cmpf",   0x04000000, 0xffe00000, G_r_r },
 649   { "cmpf",   0x04200000, 0xffe00000, G_T_r },
 650   { "cmpf",   0x04400000, 0xffe00000, G_Q_r },
 651   { "cmpf",   0x04600000, 0xffe00000, G_F_r },
 652   { "cmpf",   0x23000000, 0xffe00000, T_rr_ },
 653   { "cmpf",   0x23200000, 0xffe00000, T_rS_ },
 654   { "cmpf",   0x23400000, 0xffe00000, T_Sr_ },
 655   { "cmpf",   0x23600000, 0xffe00000, T_SS_ },
 656   { "cmpf",   0x33200000, 0xffe00000, T_Rr_ }, /* C4x */
 657   { "cmpf",   0x33600000, 0xffe00000, T_RR_ }, /* C4x */
 658   { "cmpf3",  0x23000000, 0xffe00000, T_rr_ },
 659   { "cmpf3",  0x23200000, 0xffe00000, T_rS_ },
 660   { "cmpf3",  0x23400000, 0xffe00000, T_Sr_ },
 661   { "cmpf3",  0x23600000, 0xffe00000, T_SS_ },
 662   { "cmpf3",  0x33200000, 0xffe00000, T_Rr_ }, /* C4x */
 663   { "cmpf3",  0x33600000, 0xffe00000, T_RR_ }, /* C4x */
 664   { "cmpi",   0x04800000, 0xffe00000, G_r_r },
 665   { "cmpi",   0x04a00000, 0xffe00000, G_T_r },
 666   { "cmpi",   0x04c00000, 0xffe00000, G_Q_r },
 667   { "cmpi",   0x04e00000, 0xffe00000, G_I_r },
 668   { "cmpi",   0x23800000, 0xffe00000, T_rr_ },
 669   { "cmpi",   0x23a00000, 0xffe00000, T_rS_ },
 670   { "cmpi",   0x23c00000, 0xffe00000, T_Sr_ },
 671   { "cmpi",   0x23e00000, 0xffe00000, T_SS_ },
 672   { "cmpi",   0x33800000, 0xffe00000, T_Jr_ }, /* C4x */
 673   { "cmpi",   0x33a00000, 0xffe00000, T_Rr_ }, /* C4x */
 674   { "cmpi",   0x33c00000, 0xffe00000, T_JR_ }, /* C4x */
 675   { "cmpi",   0x33e00000, 0xffe00000, T_RR_ }, /* C4x */
 676   { "cmpi3",  0x23800000, 0xffe00000, T_rr_ },
 677   { "cmpi3",  0x23a00000, 0xffe00000, T_rS_ },
 678   { "cmpi3",  0x23c00000, 0xffe00000, T_Sr_ },
 679   { "cmpi3",  0x23e00000, 0xffe00000, T_SS_ },
 680   { "cmpi3",  0x33800000, 0xffe00000, T_Jr_ }, /* C4x */
 681   { "cmpi3",  0x33a00000, 0xffe00000, T_Rr_ }, /* C4x */
 682   { "cmpi3",  0x33c00000, 0xffe00000, T_JR_ }, /* C4x */
 683   { "cmpi3",  0x33e00000, 0xffe00000, T_RR_ }, /* C4x */
 684   { "dbB",    0x6c000000, 0xfe200000, "A,Q" },
 685   { "dbB",    0x6e000000, 0xfe200000, "A,P" },
 686   { "db",     0x6c000000, 0xfe200000, "A,Q" }, /* synonym for dbu */
 687   { "db",     0x6e000000, 0xfe200000, "A,P" }, /* synonym for dbu */
 688   { "dbBd",   0x6c200000, 0xfe200000, "A,Q" },
 689   { "dbBd",   0x6e200000, 0xfe200000, "A,P" },
 690   { "dbd",    0x6c200000, 0xfe200000, "A,Q" }, /* synonym for dbud */
 691   { "dbd",    0x6e200000, 0xfe200000, "A,P" }, /* synonym for dbud */
 692   { "fix",    0x05000000, 0xffe00000, G_r_r },
 693   { "fix",    0x05200000, 0xffe00000, G_T_r },
 694   { "fix",    0x05400000, 0xffe00000, G_Q_r },
 695   { "fix",    0x05600000, 0xffe00000, G_F_r },
 696   { "float",  0x05800000, 0xffe00000, G_r_r },
 697   { "float",  0x05a00000, 0xffe00000, G_T_r },
 698   { "float",  0x05c00000, 0xffe00000, G_Q_r },
 699   { "float",  0x05e00000, 0xffe00000, G_I_r },
 700   { "iack",   0x1b200000, 0xffe00000, "@" },
 701   { "iack",   0x1b400000, 0xffe00000, "*" },
 702   { "idle",   0x06000000, 0xffffffff, "" },
 703   { "lde",    0x06800000, 0xffe00000, G_r_r },
 704   { "lde",    0x06a00000, 0xffe00000, G_T_r },
 705   { "lde",    0x06c00000, 0xffe00000, G_Q_r },
 706   { "lde",    0x06e00000, 0xffe00000, G_F_r },
 707   { "ldf",    0x07000000, 0xffe00000, G_r_r },
 708   { "ldf",    0x07200000, 0xffe00000, G_T_r },
 709   { "ldf",    0x07400000, 0xffe00000, G_Q_r },
 710   { "ldf",    0x07600000, 0xffe00000, G_F_r },
 711   { "ldfC",   0x40000000, 0xf0600000, G_r_r },
 712   { "ldfC",   0x40200000, 0xf0600000, G_T_r },
 713   { "ldfC",   0x40400000, 0xf0600000, G_Q_r },
 714   { "ldfC",   0x40600000, 0xf0600000, G_F_r },
 715   { "ldfi",   0x07a00000, 0xffe00000, G_T_r },
 716   { "ldfi",   0x07c00000, 0xffe00000, G_Q_r },
 717   { "ldi",    0x08000000, 0xffe00000, G_r_r },
 718   { "ldi",    0x08200000, 0xffe00000, G_T_r },
 719   { "ldi",    0x08400000, 0xffe00000, G_Q_r },
 720   { "ldi",    0x08600000, 0xffe00000, G_I_r },
 721   { "ldiC",   0x50000000, 0xf0600000, G_r_r },
 722   { "ldiC",   0x50200000, 0xf0600000, G_T_r },
 723   { "ldiC",   0x50400000, 0xf0600000, G_Q_r },
 724   { "ldiC",   0x50600000, 0xf0600000, G_I_r },
 725   { "ldii",   0x08a00000, 0xffe00000, G_T_r },
 726   { "ldii",   0x08c00000, 0xffe00000, G_Q_r },
 727   { "ldp",    0x50700000, 0xffff0000, "#" }, /* synonym for ldiu #,dp */
 728   { "ldm",    0x09000000, 0xffe00000, G_r_r },
 729   { "ldm",    0x09200000, 0xffe00000, G_T_r },
 730   { "ldm",    0x09400000, 0xffe00000, G_Q_r },
 731   { "ldm",    0x09600000, 0xffe00000, G_F_r },
 732   { "lsh",    0x09800000, 0xffe00000, G_r_r },
 733   { "lsh",    0x09a00000, 0xffe00000, G_T_r },
 734   { "lsh",    0x09c00000, 0xffe00000, G_Q_r },
 735   { "lsh",    0x09e00000, 0xffe00000, G_I_r },
 736   { "lsh",    0x24000000, 0xffe00000, T_rrr },
 737   { "lsh",    0x24200000, 0xffe00000, T_Srr },
 738   { "lsh",    0x24400000, 0xffe00000, T_rSr },
 739   { "lsh",    0x24600000, 0xffe00000, T_SSr },
 740   { "lsh",    0x34000000, 0xffe00000, T_Jrr }, /* C4x */
 741   { "lsh",    0x34200000, 0xffe00000, T_Rrr }, /* C4x */
 742   { "lsh",    0x34400000, 0xffe00000, T_JRr }, /* C4x */
 743   { "lsh",    0x34600000, 0xffe00000, T_RRr }, /* C4x */
 744   { "lsh3",   0x24000000, 0xffe00000, T_rrr },
 745   { "lsh3",   0x24200000, 0xffe00000, T_Srr },
 746   { "lsh3",   0x24400000, 0xffe00000, T_rSr },
 747   { "lsh3",   0x24600000, 0xffe00000, T_SSr },
 748   { "lsh3",   0x34000000, 0xffe00000, T_Jrr }, /* C4x */
 749   { "lsh3",   0x34200000, 0xffe00000, T_Rrr }, /* C4x */
 750   { "lsh3",   0x34400000, 0xffe00000, T_JRr }, /* C4x */
 751   { "lsh3",   0x34600000, 0xffe00000, T_RRr }, /* C4x */
 752   { "mpyf",   0x0a000000, 0xffe00000, G_r_r },
 753   { "mpyf",   0x0a200000, 0xffe00000, G_T_r },
 754   { "mpyf",   0x0a400000, 0xffe00000, G_Q_r },
 755   { "mpyf",   0x0a600000, 0xffe00000, G_F_r },
 756   { "mpyf",   0x24800000, 0xffe00000, T_rrr },
 757   { "mpyf",   0x24a00000, 0xffe00000, T_Srr },
 758   { "mpyf",   0x24c00000, 0xffe00000, T_rSr },
 759   { "mpyf",   0x24e00000, 0xffe00000, T_SSr },
 760   { "mpyf",   0x34800000, 0xffe00000, T_Jrr }, /* C4x */
 761   { "mpyf",   0x34800000, 0xffe00000, T_rJr }, /* C4x */
 762   { "mpyf",   0x34a00000, 0xffe00000, T_rRr }, /* C4x */
 763   { "mpyf",   0x34a00000, 0xffe00000, T_Rrr }, /* C4x */
 764   { "mpyf",   0x34c00000, 0xffe00000, T_JRr }, /* C4x */
 765   { "mpyf",   0x34c00000, 0xffe00000, T_RJr }, /* C4x */
 766   { "mpyf",   0x34e00000, 0xffe00000, T_RRr }, /* C4x */
 767   { "mpyf3",  0x24800000, 0xffe00000, T_rrr },
 768   { "mpyf3",  0x24a00000, 0xffe00000, T_Srr },
 769   { "mpyf3",  0x24c00000, 0xffe00000, T_rSr },
 770   { "mpyf3",  0x24e00000, 0xffe00000, T_SSr },
 771   { "mpyf3",  0x34800000, 0xffe00000, T_Jrr }, /* C4x */
 772   { "mpyf3",  0x34800000, 0xffe00000, T_rJr }, /* C4x */
 773   { "mpyf3",  0x34a00000, 0xffe00000, T_rRr }, /* C4x */
 774   { "mpyf3",  0x34a00000, 0xffe00000, T_Rrr }, /* C4x */
 775   { "mpyf3",  0x34c00000, 0xffe00000, T_JRr }, /* C4x */
 776   { "mpyf3",  0x34c00000, 0xffe00000, T_RJr }, /* C4x */
 777   { "mpyf3",  0x34e00000, 0xffe00000, T_RRr }, /* C4x */
 778   { "mpyi",   0x0a800000, 0xffe00000, G_r_r },
 779   { "mpyi",   0x0aa00000, 0xffe00000, G_T_r },
 780   { "mpyi",   0x0ac00000, 0xffe00000, G_Q_r },
 781   { "mpyi",   0x0ae00000, 0xffe00000, G_I_r },
 782   { "mpyi",   0x25000000, 0xffe00000, T_rrr },
 783   { "mpyi",   0x25200000, 0xffe00000, T_Srr },
 784   { "mpyi",   0x25400000, 0xffe00000, T_rSr },
 785   { "mpyi",   0x25600000, 0xffe00000, T_SSr },
 786   { "mpyi",   0x35000000, 0xffe00000, T_Jrr }, /* C4x */
 787   { "mpyi",   0x35000000, 0xffe00000, T_rJr }, /* C4x */
 788   { "mpyi",   0x35200000, 0xffe00000, T_rRr }, /* C4x */
 789   { "mpyi",   0x35200000, 0xffe00000, T_Rrr }, /* C4x */
 790   { "mpyi",   0x35400000, 0xffe00000, T_JRr }, /* C4x */
 791   { "mpyi",   0x35400000, 0xffe00000, T_RJr }, /* C4x */
 792   { "mpyi",   0x35600000, 0xffe00000, T_RRr }, /* C4x */
 793   { "mpyi3",  0x25000000, 0xffe00000, T_rrr },
 794   { "mpyi3",  0x25200000, 0xffe00000, T_Srr },
 795   { "mpyi3",  0x25400000, 0xffe00000, T_rSr },
 796   { "mpyi3",  0x25600000, 0xffe00000, T_SSr },
 797   { "mpyi3",  0x35000000, 0xffe00000, T_Jrr }, /* C4x */
 798   { "mpyi3",  0x35000000, 0xffe00000, T_rJr }, /* C4x */
 799   { "mpyi3",  0x35200000, 0xffe00000, T_rRr }, /* C4x */
 800   { "mpyi3",  0x35200000, 0xffe00000, T_Rrr }, /* C4x */
 801   { "mpyi3",  0x35400000, 0xffe00000, T_JRr }, /* C4x */
 802   { "mpyi3",  0x35400000, 0xffe00000, T_RJr }, /* C4x */
 803   { "mpyi3",  0x35600000, 0xffe00000, T_RRr }, /* C4x */
 804   { "negb",   0x0b000000, 0xffe00000, G_r_r },
 805   { "negb",   0x0b200000, 0xffe00000, G_T_r },
 806   { "negb",   0x0b400000, 0xffe00000, G_Q_r },
 807   { "negb",   0x0b600000, 0xffe00000, G_I_r },
 808   { "negf",   0x0b800000, 0xffe00000, G_r_r },
 809   { "negf",   0x0ba00000, 0xffe00000, G_T_r },
 810   { "negf",   0x0bc00000, 0xffe00000, G_Q_r },
 811   { "negf",   0x0be00000, 0xffe00000, G_F_r },
 812   { "negi",   0x0c000000, 0xffe00000, G_r_r },
 813   { "negi",   0x0c200000, 0xffe00000, G_T_r },
 814   { "negi",   0x0c400000, 0xffe00000, G_Q_r },
 815   { "negi",   0x0c600000, 0xffe00000, G_I_r },
 816   { "nop",    0x0c800000, 0xffe00000, "Q" },
 817   { "nop",    0x0cc00000, 0xffe00000, "*" },
 818   { "nop",    0x0c800000, 0xffe00000, "" },
 819   { "norm",   0x0d000000, 0xffe00000, G_r_r },
 820   { "norm",   0x0d200000, 0xffe00000, G_T_r },
 821   { "norm",   0x0d400000, 0xffe00000, G_Q_r },
 822   { "norm",   0x0d600000, 0xffe00000, G_F_r },
 823   { "not",    0x0d800000, 0xffe00000, G_r_r },
 824   { "not",    0x0da00000, 0xffe00000, G_T_r },
 825   { "not",    0x0dc00000, 0xffe00000, G_Q_r },
 826   { "not",    0x0de00000, 0xffe00000, G_L_r },
 827   { "or",     0x10000000, 0xffe00000, G_r_r },
 828   { "or",     0x10200000, 0xffe00000, G_T_r },
 829   { "or",     0x10400000, 0xffe00000, G_Q_r },
 830   { "or",     0x10600000, 0xffe00000, G_L_r },
 831   { "or",     0x25800000, 0xffe00000, T_rrr },
 832   { "or",     0x25a00000, 0xffe00000, T_Srr },
 833   { "or",     0x25c00000, 0xffe00000, T_rSr },
 834   { "or",     0x25e00000, 0xffe00000, T_SSr },
 835   { "or",     0x35800000, 0xffe00000, T_Jrr }, /* C4x */
 836   { "or",     0x35800000, 0xffe00000, T_rJr }, /* C4x */
 837   { "or",     0x35a00000, 0xffe00000, T_rRr }, /* C4x */
 838   { "or",     0x35a00000, 0xffe00000, T_Rrr }, /* C4x */
 839   { "or",     0x35c00000, 0xffe00000, T_JRr }, /* C4x */
 840   { "or",     0x35c00000, 0xffe00000, T_RJr }, /* C4x */
 841   { "or",     0x35e00000, 0xffe00000, T_RRr }, /* C4x */
 842   { "or3",    0x25800000, 0xffe00000, T_rrr },
 843   { "or3",    0x25a00000, 0xffe00000, T_Srr },
 844   { "or3",    0x25c00000, 0xffe00000, T_rSr },
 845   { "or3",    0x25e00000, 0xffe00000, T_SSr },
 846   { "or3",    0x35800000, 0xffe00000, T_Jrr }, /* C4x */
 847   { "or3",    0x35800000, 0xffe00000, T_rJr }, /* C4x */
 848   { "or3",    0x35a00000, 0xffe00000, T_rRr }, /* C4x */
 849   { "or3",    0x35a00000, 0xffe00000, T_Rrr }, /* C4x */
 850   { "or3",    0x35c00000, 0xffe00000, T_JRr }, /* C4x */
 851   { "or3",    0x35c00000, 0xffe00000, T_RJr }, /* C4x */
 852   { "or3",    0x35e00000, 0xffe00000, T_RRr }, /* C4x */
 853   { "pop",    0x0e200000, 0xffe00000, "R" },
 854   { "popf",   0x0ea00000, 0xffe00000, "R" },
 855   { "push",   0x0f200000, 0xffe00000, "R" },
 856   { "pushf",  0x0fa00000, 0xffe00000, "R" },
 857   { "retiB",  0x78000000, 0xffe00000, "" },
 858   { "reti",   0x78000000, 0xffe00000, "" }, /* synonym for reti */
 859   { "retsB",  0x78800000, 0xffe00000, "" },
 860   { "rets",   0x78800000, 0xffe00000, "" }, /* synonym for rets */
 861   { "rnd",    0x11000000, 0xffe00000, G_r_r },
 862   { "rnd",    0x11200000, 0xffe00000, G_T_r },
 863   { "rnd",    0x11400000, 0xffe00000, G_Q_r },
 864   { "rnd",    0x11600000, 0xffe00000, G_F_r },
 865   { "rol",    0x11e00000, 0xffe00000, "R" },
 866   { "rolc",   0x12600000, 0xffe00000, "R" },
 867   { "ror",    0x12e00000, 0xffe00000, "R" },
 868   { "rorc",   0x13600000, 0xffe00000, "R" },
 869   { "rptb",   0x64000000, 0xff000000, "B" },
 870   { "rptb",   0x79000000, 0xff000000, "Q" }, /* C4x */
 871   { "rpts",   0x139b0000, 0xffff0000, "Q" },
 872   { "rpts",   0x13bb0000, 0xffff0000, "@" },
 873   { "rpts",   0x13db0000, 0xffff0000, "*" },
 874   { "rpts",   0x13fb0000, 0xffff0000, "U" },
 875   { "sigi",   0x16000000, 0xffe00000, "" },  /* C3x */
 876   { "sigi",   0x16200000, 0xffe00000, G_T_r }, /* C4x */
 877   { "sigi",   0x16400000, 0xffe00000, G_Q_r }, /* C4x */
 878   { "stf",    0x14200000, 0xffe00000, "R,@" },
 879   { "stf",    0x14400000, 0xffe00000, "R,*" },
 880   { "stfi",   0x14a00000, 0xffe00000, "R,@" },
 881   { "stfi",   0x14c00000, 0xffe00000, "R,*" },
 882   { "sti",    0x15000000, 0xffe00000, "T,@" }, /* C4x only */
 883   { "sti",    0x15200000, 0xffe00000, "R,@" },
 884   { "sti",    0x15400000, 0xffe00000, "R,*" },
 885   { "sti",    0x15600000, 0xffe00000, "T,*" }, /* C4x only */
 886   { "stii",   0x15a00000, 0xffe00000, "R,@" },
 887   { "stii",   0x15c00000, 0xffe00000, "R,*" },
 888   { "subb",   0x16800000, 0xffe00000, G_r_r },
 889   { "subb",   0x16a00000, 0xffe00000, G_T_r },
 890   { "subb",   0x16c00000, 0xffe00000, G_Q_r },
 891   { "subb",   0x16e00000, 0xffe00000, G_I_r },
 892   { "subb",   0x26000000, 0xffe00000, T_rrr },
 893   { "subb",   0x26200000, 0xffe00000, T_Srr },
 894   { "subb",   0x26400000, 0xffe00000, T_rSr },
 895   { "subb",   0x26600000, 0xffe00000, T_SSr },
 896   { "subb",   0x36000000, 0xffe00000, T_Jrr }, /* C4x */
 897   { "subb",   0x36200000, 0xffe00000, T_Rrr }, /* C4x */
 898   { "subb",   0x36400000, 0xffe00000, T_JRr }, /* C4x */
 899   { "subb",   0x36600000, 0xffe00000, T_RRr }, /* C4x */
 900   { "subb3",  0x26000000, 0xffe00000, T_rrr },
 901   { "subb3",  0x26200000, 0xffe00000, T_Srr },
 902   { "subb3",  0x26400000, 0xffe00000, T_rSr },
 903   { "subb3",  0x26600000, 0xffe00000, T_SSr },
 904   { "subb3",  0x36000000, 0xffe00000, T_Jrr }, /* C4x */
 905   { "subb3",  0x36200000, 0xffe00000, T_Rrr }, /* C4x */
 906   { "subb3",  0x36400000, 0xffe00000, T_JRr }, /* C4x */
 907   { "subb3",  0x36600000, 0xffe00000, T_RRr }, /* C4x */
 908   { "subc",   0x17000000, 0xffe00000, G_r_r },
 909   { "subc",   0x17200000, 0xffe00000, G_T_r },
 910   { "subc",   0x17400000, 0xffe00000, G_Q_r },
 911   { "subc",   0x17600000, 0xffe00000, G_I_r },
 912   { "subf",   0x17800000, 0xffe00000, G_r_r },
 913   { "subf",   0x17a00000, 0xffe00000, G_T_r },
 914   { "subf",   0x17c00000, 0xffe00000, G_Q_r },
 915   { "subf",   0x17e00000, 0xffe00000, G_F_r },
 916   { "subf",   0x26800000, 0xffe00000, T_rrr },
 917   { "subf",   0x26a00000, 0xffe00000, T_Srr },
 918   { "subf",   0x26c00000, 0xffe00000, T_rSr },
 919   { "subf",   0x26e00000, 0xffe00000, T_SSr },
 920   { "subf",   0x36800000, 0xffe00000, T_Jrr }, /* C4x */
 921   { "subf",   0x36a00000, 0xffe00000, T_Rrr }, /* C4x */
 922   { "subf",   0x36c00000, 0xffe00000, T_JRr }, /* C4x */
 923   { "subf",   0x36e00000, 0xffe00000, T_RRr }, /* C4x */
 924   { "subf3",  0x26800000, 0xffe00000, T_rrr },
 925   { "subf3",  0x26a00000, 0xffe00000, T_Srr },
 926   { "subf3",  0x26c00000, 0xffe00000, T_rSr },
 927   { "subf3",  0x26e00000, 0xffe00000, T_SSr },
 928   { "subf3",  0x36800000, 0xffe00000, T_Jrr }, /* C4x */
 929   { "subf3",  0x36a00000, 0xffe00000, T_Rrr }, /* C4x */
 930   { "subf3",  0x36c00000, 0xffe00000, T_JRr }, /* C4x */
 931   { "subf3",  0x36e00000, 0xffe00000, T_RRr }, /* C4x */
 932   { "subi",   0x18000000, 0xffe00000, G_r_r },
 933   { "subi",   0x18200000, 0xffe00000, G_T_r },
 934   { "subi",   0x18400000, 0xffe00000, G_Q_r },
 935   { "subi",   0x18600000, 0xffe00000, G_I_r },
 936   { "subi",   0x27000000, 0xffe00000, T_rrr },
 937   { "subi",   0x27200000, 0xffe00000, T_Srr },
 938   { "subi",   0x27400000, 0xffe00000, T_rSr },
 939   { "subi",   0x27600000, 0xffe00000, T_SSr },
 940   { "subi",   0x37000000, 0xffe00000, T_Jrr }, /* C4x */
 941   { "subi",   0x37200000, 0xffe00000, T_Rrr }, /* C4x */
 942   { "subi",   0x37400000, 0xffe00000, T_JRr }, /* C4x */
 943   { "subi",   0x37600000, 0xffe00000, T_RRr }, /* C4x */
 944   { "subi3",  0x27000000, 0xffe00000, T_rrr },
 945   { "subi3",  0x27200000, 0xffe00000, T_Srr },
 946   { "subi3",  0x27400000, 0xffe00000, T_rSr },
 947   { "subi3",  0x27600000, 0xffe00000, T_SSr },
 948   { "subi3",  0x37000000, 0xffe00000, T_Jrr }, /* C4x */
 949   { "subi3",  0x37200000, 0xffe00000, T_Rrr }, /* C4x */
 950   { "subi3",  0x37400000, 0xffe00000, T_JRr }, /* C4x */
 951   { "subi3",  0x37600000, 0xffe00000, T_RRr }, /* C4x */
 952   { "subrb",  0x18800000, 0xffe00000, G_r_r },
 953   { "subrb",  0x18a00000, 0xffe00000, G_T_r },
 954   { "subrb",  0x18c00000, 0xffe00000, G_Q_r },
 955   { "subrb",  0x18e00000, 0xffe00000, G_I_r },
 956   { "subrf",  0x19000000, 0xffe00000, G_r_r },
 957   { "subrf",  0x19200000, 0xffe00000, G_T_r },
 958   { "subrf",  0x19400000, 0xffe00000, G_Q_r },
 959   { "subrf",  0x19600000, 0xffe00000, G_F_r },
 960   { "subri",  0x19800000, 0xffe00000, G_r_r },
 961   { "subri",  0x19a00000, 0xffe00000, G_T_r },
 962   { "subri",  0x19c00000, 0xffe00000, G_Q_r },
 963   { "subri",  0x19e00000, 0xffe00000, G_I_r },
 964   { "swi",    0x66000000, 0xffffffff, "" },
 965   { "trapB",  0x74000000, 0xffe00000, "V" },
 966   { "trap",   0x74000000, 0xffe00000, "V" }, /* synonym for trapu */
 967   { "tstb",   0x1a000000, 0xffe00000, G_r_r },
 968   { "tstb",   0x1a200000, 0xffe00000, G_T_r },
 969   { "tstb",   0x1a400000, 0xffe00000, G_Q_r },
 970   { "tstb",   0x1a600000, 0xffe00000, G_L_r },
 971   { "tstb",   0x27800000, 0xffe00000, T_rr_ },
 972   { "tstb",   0x27a00000, 0xffe00000, T_rS_ },
 973   { "tstb",   0x27c00000, 0xffe00000, T_Sr_ },
 974   { "tstb",   0x27e00000, 0xffe00000, T_SS_ },
 975   { "tstb",   0x37800000, 0xffe00000, T_Jr_ }, /* C4x */
 976   { "tstb",   0x37800000, 0xffe00000, T_rJ_ }, /* C4x */
 977   { "tstb",   0x37a00000, 0xffe00000, T_rR_ }, /* C4x */
 978   { "tstb",   0x37a00000, 0xffe00000, T_Rr_ }, /* C4x */
 979   { "tstb",   0x37c00000, 0xffe00000, T_JR_ }, /* C4x */
 980   { "tstb",   0x37c00000, 0xffe00000, T_RJ_ }, /* C4x */
 981   { "tstb",   0x37e00000, 0xffe00000, T_RR_ }, /* C4x */
 982   { "tstb3",  0x27800000, 0xffe00000, T_rr_ },
 983   { "tstb3",  0x27a00000, 0xffe00000, T_rS_ },
 984   { "tstb3",  0x27c00000, 0xffe00000, T_Sr_ },
 985   { "tstb3",  0x27e00000, 0xffe00000, T_SS_ },
 986   { "tstb3",  0x37800000, 0xffe00000, T_Jr_ }, /* C4x */
 987   { "tstb3",  0x37800000, 0xffe00000, T_rJ_ }, /* C4x */
 988   { "tstb3",  0x37a00000, 0xffe00000, T_rR_ }, /* C4x */
 989   { "tstb3",  0x37a00000, 0xffe00000, T_Rr_ }, /* C4x */
 990   { "tstb3",  0x37c00000, 0xffe00000, T_JR_ }, /* C4x */
 991   { "tstb3",  0x37c00000, 0xffe00000, T_RJ_ }, /* C4x */
 992   { "tstb3",  0x37e00000, 0xffe00000, T_RR_ }, /* C4x */
 993   { "xor",    0x1a800000, 0xffe00000, G_r_r },
 994   { "xor",    0x1aa00000, 0xffe00000, G_T_r },
 995   { "xor",    0x1ac00000, 0xffe00000, G_Q_r },
 996   { "xor",    0x1ae00000, 0xffe00000, G_L_r },
 997   { "xor",    0x28000000, 0xffe00000, T_rrr },
 998   { "xor",    0x28200000, 0xffe00000, T_Srr },
 999   { "xor",    0x28400000, 0xffe00000, T_rSr },
1000   { "xor",    0x28600000, 0xffe00000, T_SSr },
1001   { "xor",    0x38000000, 0xffe00000, T_Jrr }, /* C4x */
1002   { "xor",    0x38000000, 0xffe00000, T_rJr }, /* C4x */
1003   { "xor",    0x38200000, 0xffe00000, T_rRr }, /* C4x */
1004   { "xor",    0x38200000, 0xffe00000, T_Rrr }, /* C4x */
1005   { "xor",    0x3c400000, 0xffe00000, T_JRr }, /* C4x */
1006   { "xor",    0x3c400000, 0xffe00000, T_RJr }, /* C4x */
1007   { "xor",    0x3c600000, 0xffe00000, T_RRr }, /* C4x */
1008   { "xor3",   0x28000000, 0xffe00000, T_rrr },
1009   { "xor3",   0x28200000, 0xffe00000, T_Srr },
1010   { "xor3",   0x28400000, 0xffe00000, T_rSr },
1011   { "xor3",   0x28600000, 0xffe00000, T_SSr },
1012   { "xor3",   0x38000000, 0xffe00000, T_Jrr }, /* C4x */
1013   { "xor3",   0x38000000, 0xffe00000, T_rJr }, /* C4x */
1014   { "xor3",   0x38200000, 0xffe00000, T_rRr }, /* C4x */
1015   { "xor3",   0x38200000, 0xffe00000, T_Rrr }, /* C4x */
1016   { "xor3",   0x38400000, 0xffe00000, T_JRr }, /* C4x */
1017   { "xor3",   0x38400000, 0xffe00000, T_RJr }, /* C4x */
1018   { "xor3",   0x38600000, 0xffe00000, T_RRr }, /* C4x */
1019
1020   /* Dummy entry, not included in c3x_num_insts.  This
1021      lets code examine entry i + 1 without checking
1022      if we've run off the end of the table.  */
1023   { "",      0x0, 0x00, "" }
1024 };
1025
1026 const unsigned int c3x_num_insts = (((sizeof c3x_insts) / (sizeof c3x_insts[0])) - 1);
1027
1028 /* Define c4x additional opcodes for assembler and disassembler.  */
1029 static const c4x_inst_t c4x_insts[] =
1030 {
1031   /* Parallel instructions.  */
1032   { "frieee_stf",    0xf2000000, 0xfe000000, P_Sr_rS },
1033   { "toieee_stf",    0xf0000000, 0xfe000000, P_Sr_rS },
1034   { "stf_frieee",    0xf2000000, 0xfe000000, Q_rS_Sr },
1035   { "stf_toieee",    0xf0000000, 0xfe000000, Q_rS_Sr },
1036
1037   { "bBaf",    0x68a00000, 0xffe00000, "Q" },
1038   { "bBaf",    0x6aa00000, 0xffe00000, "P" },
1039   { "baf",     0x68a00000, 0xffe00000, "Q" }, /* synonym for buaf */
1040   { "baf",     0x6aa00000, 0xffe00000, "P" }, /* synonym for buaf */
1041   { "bBat",    0x68600000, 0xffe00000, "Q" },
1042   { "bBat",    0x6a600000, 0xffe00000, "P" },
1043   { "bat",     0x68600000, 0xffe00000, "Q" }, /* synonym for buat */
1044   { "bat",     0x6a600000, 0xffe00000, "P" }, /* synonym for buat */
1045   { "laj",     0x63000000, 0xff000000, "B" },
1046   { "lajB",    0x70200000, 0xffe00000, "Q" },
1047   { "lajB",    0x72200000, 0xffe00000, "P" },
1048   { "latB",    0x74800000, 0xffe00000, "V" },
1049   { "frieee",  0x1c000000, 0xffe00000, G_r_r },
1050   { "frieee",  0x1c200000, 0xffe00000, G_T_r },
1051   { "frieee",  0x1c400000, 0xffe00000, G_Q_r },
1052   { "frieee",  0x1c600000, 0xffe00000, G_F_r },
1053   { "lb0",     0xb0000000, 0xffe00000, G_r_r },
1054   { "lb0",     0xb0200000, 0xffe00000, G_T_r },
1055   { "lb0",     0xb0400000, 0xffe00000, G_Q_r },
1056   { "lb0",     0xb0600000, 0xffe00000, G_I_r },
1057   { "lbu0",    0xb2000000, 0xffe00000, G_r_r },
1058   { "lbu0",    0xb2200000, 0xffe00000, G_T_r },
1059   { "lbu0",    0xb2400000, 0xffe00000, G_Q_r },
1060   { "lbu0",    0xb2600000, 0xffe00000, G_L_r },
1061   { "lb1",     0xb0800000, 0xffe00000, G_r_r },
1062   { "lb1",     0xb0a00000, 0xffe00000, G_T_r },
1063   { "lb1",     0xb0c00000, 0xffe00000, G_Q_r },
1064   { "lb1",     0xb0e00000, 0xffe00000, G_I_r },
1065   { "lbu1",    0xb2800000, 0xffe00000, G_r_r },
1066   { "lbu1",    0xb2a00000, 0xffe00000, G_T_r },
1067   { "lbu1",    0xb2c00000, 0xffe00000, G_Q_r },
1068   { "lbu1",    0xb2e00000, 0xffe00000, G_L_r },
1069   { "lb2",     0xb1000000, 0xffe00000, G_r_r },
1070   { "lb2",     0xb1200000, 0xffe00000, G_T_r },
1071   { "lb2",     0xb1400000, 0xffe00000, G_Q_r },
1072   { "lb2",     0xb1600000, 0xffe00000, G_I_r },
1073   { "lbu2",    0xb3000000, 0xffe00000, G_r_r },
1074   { "lbu2",    0xb3200000, 0xffe00000, G_T_r },
1075   { "lbu2",    0xb3400000, 0xffe00000, G_Q_r },
1076   { "lbu2",    0xb3600000, 0xffe00000, G_L_r },
1077   { "lb3",     0xb1800000, 0xffe00000, G_r_r },
1078   { "lb3",     0xb1a00000, 0xffe00000, G_T_r },
1079   { "lb3",     0xb1c00000, 0xffe00000, G_Q_r },
1080   { "lb3",     0xb1e00000, 0xffe00000, G_I_r },
1081   { "lbu3",    0xb3800000, 0xffe00000, G_r_r },
1082   { "lbu3",    0xb3a00000, 0xffe00000, G_T_r },
1083   { "lbu3",    0xb3c00000, 0xffe00000, G_Q_r },
1084   { "lbu3",    0xb3e00000, 0xffe00000, G_L_r },
1085   { "lda",     0x1e800000, 0xffe00000, "Q,Y" },
1086   { "lda",     0x1ea00000, 0xffe00000, "@,Y" },
1087   { "lda",     0x1ec00000, 0xffe00000, "*,Y" },
1088   { "lda",     0x1ee00000, 0xffe00000, "S,Y" },
1089   { "ldep",    0x76000000, 0xffe00000, "X,R" },
1090   { "ldhi",    0x1fe00000, 0xffe00000, G_L_r },
1091   { "ldhi",    0x1fe00000, 0xffe00000, "#,R" },
1092   { "ldpe",    0x76800000, 0xffe00000, "Q,Z" },
1093   { "ldpk",    0x1F700000, 0xffff0000, "#" },
1094   { "lh0",     0xba000000, 0xffe00000, G_r_r },
1095   { "lh0",     0xba200000, 0xffe00000, G_T_r },
1096   { "lh0",     0xba400000, 0xffe00000, G_Q_r },
1097   { "lh0",     0xba600000, 0xffe00000, G_I_r },
1098   { "lhu0",    0xbb000000, 0xffe00000, G_r_r },
1099   { "lhu0",    0xbb200000, 0xffe00000, G_T_r },
1100   { "lhu0",    0xbb400000, 0xffe00000, G_Q_r },
1101   { "lhu0",    0xbb600000, 0xffe00000, G_L_r },
1102   { "lh1",     0xba800000, 0xffe00000, G_r_r },
1103   { "lh1",     0xbaa00000, 0xffe00000, G_T_r },
1104   { "lh1",     0xbac00000, 0xffe00000, G_Q_r },
1105   { "lh1",     0xbae00000, 0xffe00000, G_I_r },
1106   { "lhu1",    0xbb800000, 0xffe00000, G_r_r },
1107   { "lhu1",    0xbba00000, 0xffe00000, G_T_r },
1108   { "lhu1",    0xbbc00000, 0xffe00000, G_Q_r },
1109   { "lhu1",    0xbbe00000, 0xffe00000, G_L_r },
1110   { "lwl0",    0xb4000000, 0xffe00000, G_r_r },
1111   { "lwl0",    0xb4200000, 0xffe00000, G_T_r },
1112   { "lwl0",    0xb4400000, 0xffe00000, G_Q_r },
1113   { "lwl0",    0xb4600000, 0xffe00000, G_I_r },
1114   { "lwl1",    0xb4800000, 0xffe00000, G_r_r },
1115   { "lwl1",    0xb4a00000, 0xffe00000, G_T_r },
1116   { "lwl1",    0xb4c00000, 0xffe00000, G_Q_r },
1117   { "lwl1",    0xb4e00000, 0xffe00000, G_I_r },
1118   { "lwl2",    0xb5000000, 0xffe00000, G_r_r },
1119   { "lwl2",    0xb5200000, 0xffe00000, G_T_r },
1120   { "lwl2",    0xb5400000, 0xffe00000, G_Q_r },
1121   { "lwl2",    0xb5600000, 0xffe00000, G_I_r },
1122   { "lwl3",    0xb5800000, 0xffe00000, G_r_r },
1123   { "lwl3",    0xb5a00000, 0xffe00000, G_T_r },
1124   { "lwl3",    0xb5c00000, 0xffe00000, G_Q_r },
1125   { "lwl3",    0xb5e00000, 0xffe00000, G_I_r },
1126   { "lwr0",    0xb6000000, 0xffe00000, G_r_r },
1127   { "lwr0",    0xb6200000, 0xffe00000, G_T_r },
1128   { "lwr0",    0xb6400000, 0xffe00000, G_Q_r },
1129   { "lwr0",    0xb6600000, 0xffe00000, G_I_r },
1130   { "lwr1",    0xb6800000, 0xffe00000, G_r_r },
1131   { "lwr1",    0xb6a00000, 0xffe00000, G_T_r },
1132   { "lwr1",    0xb6c00000, 0xffe00000, G_Q_r },
1133   { "lwr1",    0xb6e00000, 0xffe00000, G_I_r },
1134   { "lwr2",    0xb7000000, 0xffe00000, G_r_r },
1135   { "lwr2",    0xb7200000, 0xffe00000, G_T_r },
1136   { "lwr2",    0xb7400000, 0xffe00000, G_Q_r },
1137   { "lwr2",    0xb7600000, 0xffe00000, G_I_r },
1138   { "lwr3",    0xb7800000, 0xffe00000, G_r_r },
1139   { "lwr3",    0xb7a00000, 0xffe00000, G_T_r },
1140   { "lwr3",    0xb7c00000, 0xffe00000, G_Q_r },
1141   { "lwr3",    0xb7e00000, 0xffe00000, G_I_r },
1142   { "mb0",     0xb8000000, 0xffe00000, G_r_r },
1143   { "mb0",     0xb8200000, 0xffe00000, G_T_r },
1144   { "mb0",     0xb8400000, 0xffe00000, G_Q_r },
1145   { "mb0",     0xb8600000, 0xffe00000, G_I_r },
1146   { "mb1",     0xb8800000, 0xffe00000, G_r_r },
1147   { "mb1",     0xb8a00000, 0xffe00000, G_T_r },
1148   { "mb1",     0xb8c00000, 0xffe00000, G_Q_r },
1149   { "mb1",     0xb8e00000, 0xffe00000, G_I_r },
1150   { "mb2",     0xb9000000, 0xffe00000, G_r_r },
1151   { "mb2",     0xb9200000, 0xffe00000, G_T_r },
1152   { "mb2",     0xb9400000, 0xffe00000, G_Q_r },
1153   { "mb2",     0xb9600000, 0xffe00000, G_I_r },
1154   { "mb3",     0xb9800000, 0xffe00000, G_r_r },
1155   { "mb3",     0xb9a00000, 0xffe00000, G_T_r },
1156   { "mb3",     0xb9c00000, 0xffe00000, G_Q_r },
1157   { "mb3",     0xb9e00000, 0xffe00000, G_I_r },
1158   { "mh0",     0xbc000000, 0xffe00000, G_r_r },
1159   { "mh0",     0xbc200000, 0xffe00000, G_T_r },
1160   { "mh0",     0xbc400000, 0xffe00000, G_Q_r },
1161   { "mh0",     0xbc600000, 0xffe00000, G_I_r },
1162   { "mh1",     0xbc800000, 0xffe00000, G_r_r },
1163   { "mh1",     0xbca00000, 0xffe00000, G_T_r },
1164   { "mh1",     0xbcc00000, 0xffe00000, G_Q_r },
1165   { "mh1",     0xbce00000, 0xffe00000, G_I_r },
1166   { "mh2",     0xbd000000, 0xffe00000, G_r_r },
1167   { "mh2",     0xbd200000, 0xffe00000, G_T_r },
1168   { "mh2",     0xbd400000, 0xffe00000, G_Q_r },
1169   { "mh2",     0xbd600000, 0xffe00000, G_I_r },
1170   { "mh3",     0xbd800000, 0xffe00000, G_r_r },
1171   { "mh3",     0xbda00000, 0xffe00000, G_T_r },
1172   { "mh3",     0xbdc00000, 0xffe00000, G_Q_r },
1173   { "mh3",     0xbde00000, 0xffe00000, G_I_r },
1174   { "mpyshi",  0x1d800000, 0xffe00000, G_r_r },
1175   { "mpyshi",  0x1da00000, 0xffe00000, G_T_r },
1176   { "mpyshi",  0x1dc00000, 0xffe00000, G_Q_r },
1177   { "mpyshi",  0x1de00000, 0xffe00000, G_I_r },
1178   { "mpyshi",  0x28800000, 0xffe00000, T_rrr },
1179   { "mpyshi",  0x28a00000, 0xffe00000, T_Srr },
1180   { "mpyshi",  0x28c00000, 0xffe00000, T_rSr },
1181   { "mpyshi",  0x28e00000, 0xffe00000, T_SSr },
1182   { "mpyshi",  0x38800000, 0xffe00000, T_Jrr }, /* C4x */
1183   { "mpyshi",  0x38800000, 0xffe00000, T_rJr }, /* C4x */
1184   { "mpyshi",  0x38a00000, 0xffe00000, T_rRr }, /* C4x */
1185   { "mpyshi",  0x38a00000, 0xffe00000, T_Rrr }, /* C4x */
1186   { "mpyshi",  0x38c00000, 0xffe00000, T_JRr }, /* C4x */
1187   { "mpyshi",  0x38c00000, 0xffe00000, T_RJr }, /* C4x */
1188   { "mpyshi",  0x38e00000, 0xffe00000, T_RRr }, /* C4x */
1189   { "mpyshi3", 0x28800000, 0xffe00000, T_rrr },
1190   { "mpyshi3", 0x28a00000, 0xffe00000, T_Srr },
1191   { "mpyshi3", 0x28c00000, 0xffe00000, T_rSr },
1192   { "mpyshi3", 0x28e00000, 0xffe00000, T_SSr },
1193   { "mpyshi3", 0x38800000, 0xffe00000, T_Jrr }, /* C4x */
1194   { "mpyshi3", 0x38800000, 0xffe00000, T_rJr }, /* C4x */
1195   { "mpyshi3", 0x38a00000, 0xffe00000, T_rRr }, /* C4x */
1196   { "mpyshi3", 0x38a00000, 0xffe00000, T_Rrr }, /* C4x */
1197   { "mpyshi3", 0x38c00000, 0xffe00000, T_JRr }, /* C4x */
1198   { "mpyshi3", 0x38c00000, 0xffe00000, T_RJr }, /* C4x */
1199   { "mpyshi3", 0x38e00000, 0xffe00000, T_RRr }, /* C4x */
1200   { "mpyuhi",  0x1e000000, 0xffe00000, G_r_r },
1201   { "mpyuhi",  0x1e200000, 0xffe00000, G_T_r },
1202   { "mpyuhi",  0x1e400000, 0xffe00000, G_Q_r },
1203   { "mpyuhi",  0x1e600000, 0xffe00000, G_I_r },
1204   { "mpyuhi",  0x29000000, 0xffe00000, T_rrr },
1205   { "mpyuhi",  0x29200000, 0xffe00000, T_Srr },
1206   { "mpyuhi",  0x29400000, 0xffe00000, T_rSr },
1207   { "mpyuhi",  0x29600000, 0xffe00000, T_SSr },
1208   { "mpyuhi",  0x39000000, 0xffe00000, T_Jrr }, /* C4x */
1209   { "mpyuhi",  0x39000000, 0xffe00000, T_rJr }, /* C4x */
1210   { "mpyuhi",  0x39200000, 0xffe00000, T_rRr }, /* C4x */
1211   { "mpyuhi",  0x39200000, 0xffe00000, T_Rrr }, /* C4x */
1212   { "mpyuhi",  0x39400000, 0xffe00000, T_JRr }, /* C4x */
1213   { "mpyuhi",  0x39400000, 0xffe00000, T_RJr }, /* C4x */
1214   { "mpyuhi",  0x39600000, 0xffe00000, T_RRr }, /* C4x */
1215   { "mpyuhi3", 0x29000000, 0xffe00000, T_rrr },
1216   { "mpyuhi3", 0x29200000, 0xffe00000, T_Srr },
1217   { "mpyuhi3", 0x29400000, 0xffe00000, T_rSr },
1218   { "mpyuhi3", 0x29600000, 0xffe00000, T_SSr },
1219   { "mpyuhi3", 0x39000000, 0xffe00000, T_Jrr }, /* C4x */
1220   { "mpyuhi3", 0x39000000, 0xffe00000, T_rJr }, /* C4x */
1221   { "mpyuhi3", 0x39200000, 0xffe00000, T_rRr }, /* C4x */
1222   { "mpyuhi3", 0x39200000, 0xffe00000, T_Rrr }, /* C4x */
1223   { "mpyuhi3", 0x39400000, 0xffe00000, T_JRr }, /* C4x */
1224   { "mpyuhi3", 0x39400000, 0xffe00000, T_RJr }, /* C4x */
1225   { "mpyuhi3", 0x39600000, 0xffe00000, T_RRr }, /* C4x */
1226   { "rcpf",    0x1d000000, 0xffe00000, G_r_r },
1227   { "rcpf",    0x1d200000, 0xffe00000, G_T_r },
1228   { "rcpf",    0x1d400000, 0xffe00000, G_Q_r },
1229   { "rcpf",    0x1d600000, 0xffe00000, G_F_r },
1230   { "retiBd",  0x78200000, 0xffe00000, "" },
1231   { "retid",   0x78200000, 0xffe00000, "" }, /* synonym for retiud */
1232   { "rptbd",   0x79800000, 0xff000000, "Q" },
1233   { "rptbd",   0x65000000, 0xff000000, "B" },
1234   { "rsqrf",   0x1c800000, 0xffe00000, G_r_r },
1235   { "rsqrf",   0x1ca00000, 0xffe00000, G_T_r },
1236   { "rsqrf",   0x1cc00000, 0xffe00000, G_Q_r },
1237   { "rsqrf",   0x1ce00000, 0xffe00000, G_F_r },
1238   { "stik",    0x15000000, 0xffe00000, "T,@" },
1239   { "stik",    0x15600000, 0xffe00000, "T,*" },
1240   { "toieee",  0x1b800000, 0xffe00000, G_r_r },
1241   { "toieee",  0x1ba00000, 0xffe00000, G_T_r },
1242   { "toieee",  0x1bc00000, 0xffe00000, G_Q_r },
1243   { "toieee",  0x1be00000, 0xffe00000, G_F_r },
1244   { "idle2",   0x06000001, 0xffffffff, "" },
1245
1246   /* Dummy entry, not included in num_insts.  This
1247      lets code examine entry i+1 without checking
1248      if we've run off the end of the table.  */
1249   { "",      0x0, 0x00, "" }
1250 };
1251
1252 const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);
1253
1254
1255 struct c4x_cond
1256 {
1257   char *        name;
1258   unsigned long cond;
1259 };
1260
1261 typedef struct c4x_cond c4x_cond_t;
1262
1263 /* Define conditional branch/load suffixes.  Put desired form for
1264    disassembler last.  */
1265 static const c4x_cond_t c4x_conds[] =
1266 {
1267   { "u",    0x00 },
1268   { "c",    0x01 }, { "lo",  0x01 },
1269   { "ls",   0x02 },
1270   { "hi",   0x03 },
1271   { "nc",   0x04 }, { "hs",  0x04 },
1272   { "z",    0x05 }, { "eq",  0x05 },
1273   { "nz",   0x06 }, { "ne",  0x06 },
1274   { "n",    0x07 }, { "l",   0x07 }, { "lt",  0x07 },
1275   { "le",   0x08 },
1276   { "p",    0x09 }, { "gt",  0x09 },
1277   { "nn",   0x0a }, { "ge",  0x0a },
1278   { "nv",   0x0c },
1279   { "v",    0x0d },
1280   { "nuf",  0x0e },
1281   { "uf",   0x0f },
1282   { "nlv",  0x10 },
1283   { "lv",   0x11 },
1284   { "nluf", 0x12 },
1285   { "luf",  0x13 },
1286   { "zuf",  0x14 },
1287   /* Dummy entry, not included in num_conds.  This
1288      lets code examine entry i+1 without checking
1289      if we've run off the end of the table.  */
1290   { "",      0x0}
1291 };
1292
1293 const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
1294
1295 struct c4x_indirect
1296 {
1297   char *        name;
1298   unsigned long modn;
1299 };
1300
1301 typedef struct c4x_indirect c4x_indirect_t;
1302
1303 /* Define indirect addressing modes where:
1304    d displacement (signed)
1305    y ir0
1306    z ir1  */
1307
1308 static const c4x_indirect_t c4x_indirects[] =
1309 {
1310   { "*+a(d)",   0x00 },
1311   { "*-a(d)",   0x01 },
1312   { "*++a(d)",  0x02 },
1313   { "*--a(d)",  0x03 },
1314   { "*a++(d)",  0x04 },
1315   { "*a--(d)",  0x05 },
1316   { "*a++(d)%", 0x06 },
1317   { "*a--(d)%", 0x07 },
1318   { "*+a(y)",   0x08 },
1319   { "*-a(y)",   0x09 },
1320   { "*++a(y)",  0x0a },
1321   { "*--a(y)",  0x0b },
1322   { "*a++(y)",  0x0c },
1323   { "*a--(y)",  0x0d },
1324   { "*a++(y)%", 0x0e },
1325   { "*a--(y)%", 0x0f },
1326   { "*+a(z)",   0x10 },
1327   { "*-a(z)",   0x11 },
1328   { "*++a(z)",  0x12 },
1329   { "*--a(z)",  0x13 },
1330   { "*a++(z)",  0x14 },
1331   { "*a--(z)",  0x15 },
1332   { "*a++(z)%", 0x16 },
1333   { "*a--(z)%", 0x17 },
1334   { "*a",       0x18 },
1335   { "*a++(y)b", 0x19 },
1336   /* Dummy entry, not included in num_indirects.  This
1337      lets code examine entry i+1 without checking
1338      if we've run off the end of the table.  */
1339   { "",      0x0}
1340 };
1341
1342 #define C3X_MODN_MAX 0x19
1343
1344 const unsigned int num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);