include/rseq/arch/aarch64.h

   1 /* SPDX-License-Identifier: MIT */
   2 /* SPDX-FileCopyrightText: 2016-2024 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
   3 /* SPDX-FileCopyrightText: 2018 Will Deacon <will.deacon@arm.com> */
   4
   5 /*
   6  * rseq/arch/aarch64.h
   7  */
   8
   9 #ifndef _RSEQ_RSEQ_H
  10 #error "Never use <rseq/arch/aarch64.h> directly; include <rseq/rseq.h> instead."
  11 #endif
  12
  13 /*
  14  * RSEQ_ASM_*() macro helpers are internal to the librseq headers. Those
  15  * are not part of the public API.
  16  */
  17
  18 /*
  19  * aarch64 -mbig-endian generates mixed endianness code vs data:
  20  * little-endian code and big-endian data. Ensure the RSEQ_SIG signature
  21  * matches code endianness.
  22  */
  23 #define RSEQ_SIG_CODE   0xd428bc00      /* BRK #0x45E0.  */
  24
  25 #ifdef __AARCH64EB__
  26 #define RSEQ_SIG_DATA   0x00bc28d4      /* BRK #0x45E0.  */
  27 #else
  28 #define RSEQ_SIG_DATA   RSEQ_SIG_CODE
  29 #endif
  30
  31 #define RSEQ_SIG        RSEQ_SIG_DATA
  32
  33 /*
  34  * Refer to the Linux kernel memory model (LKMM) for documentation of
  35  * the memory barriers.
  36  */
  37
  38 /* CPU memory barrier. */
  39 #define rseq_smp_mb()   __asm__ __volatile__ ("dmb ish" ::: "memory")
  40 /* CPU read memory barrier */
  41 #define rseq_smp_rmb()  __asm__ __volatile__ ("dmb ishld" ::: "memory")
  42 /* CPU write memory barrier */
  43 #define rseq_smp_wmb()  __asm__ __volatile__ ("dmb ishst" ::: "memory")
  44
  45 /* Acquire: One-way permeable barrier. */
  46 #define rseq_smp_load_acquire(p)                                                \
  47 __extension__ ({                                                                \
  48         union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u; \
  49         switch (sizeof(*(p))) {                                                 \
  50         case 1:                                                                 \
  51                 __asm__ __volatile__ ("ldarb %w0, %1"                           \
  52                         : "=r" (*(__u8 *)__u.__c)                               \
  53                         : "Q" (*(p)) : "memory");                               \
  54                 break;                                                          \
  55         case 2:                                                                 \
  56                 __asm__ __volatile__ ("ldarh %w0, %1"                           \
  57                         : "=r" (*(__u16 *)__u.__c)                              \
  58                         : "Q" (*(p)) : "memory");                               \
  59                 break;                                                          \
  60         case 4:                                                                 \
  61                 __asm__ __volatile__ ("ldar %w0, %1"                            \
  62                         : "=r" (*(__u32 *)__u.__c)                              \
  63                         : "Q" (*(p)) : "memory");                               \
  64                 break;                                                          \
  65         case 8:                                                                 \
  66                 __asm__ __volatile__ ("ldar %0, %1"                             \
  67                         : "=r" (*(__u64 *)__u.__c)                              \
  68                         : "Q" (*(p)) : "memory");                               \
  69                 break;                                                          \
  70         }                                                                       \
  71         (rseq_unqual_scalar_typeof(*(p)))__u.__val;                             \
  72 })
  73
  74 /* Acquire barrier after control dependency. */
  75 #define rseq_smp_acquire__after_ctrl_dep()      rseq_smp_rmb()
  76
  77 /* Release: One-way permeable barrier. */
  78 #define rseq_smp_store_release(p, v)                                            \
  79 do {                                                                            \
  80         union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u = \
  81                 { .__val = (rseq_unqual_scalar_typeof(*(p))) (v) };             \
  82         switch (sizeof(*(p))) {                                                 \
  83         case 1:                                                                 \
  84                 __asm__ __volatile__ ("stlrb %w1, %0"                           \
  85                                 : "=Q" (*(p))                                   \
  86                                 : "r" (*(__u8 *)__u.__c)                        \
  87                                 : "memory");                                    \
  88                 break;                                                          \
  89         case 2:                                                                 \
  90                 __asm__ __volatile__ ("stlrh %w1, %0"                           \
  91                                 : "=Q" (*(p))                                   \
  92                                 : "r" (*(__u16 *)__u.__c)                       \
  93                                 : "memory");                                    \
  94                 break;                                                          \
  95         case 4:                                                                 \
  96                 __asm__ __volatile__ ("stlr %w1, %0"                            \
  97                                 : "=Q" (*(p))                                   \
  98                                 : "r" (*(__u32 *)__u.__c)                       \
  99                                 : "memory");                                    \
 100                 break;                                                          \
 101         case 8:                                                                 \
 102                 __asm__ __volatile__ ("stlr %1, %0"                             \
 103                                 : "=Q" (*(p))                                   \
 104                                 : "r" (*(__u64 *)__u.__c)                       \
 105                                 : "memory");                                    \
 106                 break;                                                          \
 107         }                                                                       \
 108 } while (0)
 109
 110 /* Temporary scratch registers. */
 111 #define RSEQ_ASM_TMP_REG32      "w15"
 112 #define RSEQ_ASM_TMP_REG        "x15"
 113 #define RSEQ_ASM_TMP_REG_2      "x14"
 114
 115 /* Only used in RSEQ_ASM_DEFINE_TABLE. */
 116 #define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip,                \
 117                                 post_commit_offset, abort_ip)                   \
 118         "       .pushsection    __rseq_cs, \"aw\"\n"                            \
 119         "       .balign 32\n"                                                   \
 120         __rseq_str(label) ":\n"                                                 \
 121         "       .long   " __rseq_str(version) ", " __rseq_str(flags) "\n"       \
 122         "       .quad   " __rseq_str(start_ip) ", "                             \
 123                           __rseq_str(post_commit_offset) ", "                   \
 124                           __rseq_str(abort_ip) "\n"                             \
 125         "       .popsection\n\t"                                                \
 126         "       .pushsection __rseq_cs_ptr_array, \"aw\"\n"                     \
 127         "       .quad " __rseq_str(label) "b\n"                                 \
 128         "       .popsection\n"
 129
 130 /*
 131  * Define an rseq critical section structure of version 0 with no flags.
 132  *
 133  *  @label:
 134  *    Local label for the beginning of the critical section descriptor
 135  *    structure.
 136  *  @start_ip:
 137  *    Pointer to the first instruction of the sequence of consecutive assembly
 138  *    instructions.
 139  *  @post_commit_ip:
 140  *    Pointer to the instruction after the last instruction of the sequence of
 141  *    consecutive assembly instructions.
 142  *  @abort_ip:
 143  *    Pointer to the instruction where to move the execution flow in case of
 144  *    abort of the sequence of consecutive assembly instructions.
 145  */
 146 #define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip)        \
 147         __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip,                      \
 148                                 (post_commit_ip) - (start_ip), abort_ip)
 149
 150 /*
 151  * Define the @exit_ip pointer as an exit point for the sequence of consecutive
 152  * assembly instructions at @start_ip.
 153  *
 154  *  @start_ip:
 155  *    Pointer to the first instruction of the sequence of consecutive assembly
 156  *    instructions.
 157  *  @exit_ip:
 158  *    Pointer to an exit point instruction.
 159  *
 160  * Exit points of a rseq critical section consist of all instructions outside
 161  * of the critical section where a critical section can either branch to or
 162  * reach through the normal course of its execution. The abort IP and the
 163  * post-commit IP are already part of the __rseq_cs section and should not be
 164  * explicitly defined as additional exit points. Knowing all exit points is
 165  * useful to assist debuggers stepping over the critical section.
 166  */
 167 #define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip)                           \
 168         "       .pushsection __rseq_exit_point_array, \"aw\"\n"                 \
 169         "       .quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n"      \
 170         "       .popsection\n"
 171
 172 /*
 173  * Define a critical section abort handler.
 174  *
 175  *  @label:
 176  *    Local label to the abort handler.
 177  *  @teardown:
 178  *    Sequence of instructions to run on abort.
 179  *  @abort_label:
 180  *    C label to jump to at the end of the sequence.
 181  */
 182 #define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label)                     \
 183         "       b       222f\n"                                                 \
 184         "       .inst   "       __rseq_str(RSEQ_SIG_CODE) "\n"                  \
 185         __rseq_str(label) ":\n"                                                 \
 186         teardown                                                                \
 187         "       b       %l[" __rseq_str(abort_label) "]\n"                      \
 188         "222:\n"
 189
 190 /* Jump to local label @label when @cpu_id != @current_cpu_id. */
 191 #define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs)                        \
 192         RSEQ_INJECT_ASM(1)                                                      \
 193         "       adrp    " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n"       \
 194         "       add     " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG                \
 195                         ", :lo12:" __rseq_str(cs_label) "\n"                    \
 196         "       str     " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n"     \
 197         __rseq_str(label) ":\n"
 198
 199 /* Store @value to address @var. */
 200 #define RSEQ_ASM_OP_STORE(value, var)                                           \
 201         "       str     %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
 202
 203 /* Store-release @value to address @var. */
 204 #define RSEQ_ASM_OP_STORE_RELEASE(value, var)                                   \
 205         "       stlr    %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
 206
 207 /*
 208  * End-of-sequence store of @value to address @var. Emit
 209  * @post_commit_label label after the store instruction.
 210  */
 211 #define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label)                  \
 212         RSEQ_ASM_OP_STORE(value, var)                                           \
 213         __rseq_str(post_commit_label) ":\n"
 214
 215 /*
 216  * End-of-sequence store-release of @value to address @var. Emit
 217  * @post_commit_label label after the store instruction.
 218  */
 219 #define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label)          \
 220         RSEQ_ASM_OP_STORE_RELEASE(value, var)                                   \
 221         __rseq_str(post_commit_label) ":\n"
 222
 223 /* Jump to local label @label when @var != @expect. */
 224 #define RSEQ_ASM_OP_CBNE(var, expect, label)                                    \
 225         "       ldr     " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"         \
 226         "       sub     " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG                \
 227                         ", %[" __rseq_str(expect) "]\n"                         \
 228         "       cbnz    " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
 229
 230 /*
 231  * Jump to local label @label when @var != @expect (32-bit register
 232  * comparison).
 233  */
 234 #define RSEQ_ASM_OP_CBNE32(var, expect, label)                                  \
 235         "       ldr     " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n"       \
 236         "       sub     " RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32            \
 237                         ", %w[" __rseq_str(expect) "]\n"                        \
 238         "       cbnz    " RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n"
 239
 240 /* Jump to local label @label when @var == @expect. */
 241 #define RSEQ_ASM_OP_CBEQ(var, expect, label)                                    \
 242         "       ldr     " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"         \
 243         "       sub     " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG                \
 244                         ", %[" __rseq_str(expect) "]\n"                         \
 245         "       cbz     " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
 246
 247 /* Jump to local label @label when @cpu_id != @current_cpu_id. */
 248 #define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label)                     \
 249         RSEQ_INJECT_ASM(2)                                                      \
 250         RSEQ_ASM_OP_CBNE32(current_cpu_id, cpu_id, label)
 251
 252 /* Load @var into temporary register. */
 253 #define RSEQ_ASM_OP_R_LOAD(var)                                                 \
 254         "       ldr     " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
 255
 256 /* Store from temporary register into @var. */
 257 #define RSEQ_ASM_OP_R_STORE(var)                                                \
 258         "       str     " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
 259
 260 /* Load from address in temporary register+@offset into temporary register. */
 261 #define RSEQ_ASM_OP_R_LOAD_OFF(offset)                                          \
 262         "       ldr     " RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG               \
 263                         ", %[" __rseq_str(offset) "]]\n"
 264
 265 /* Add @count to temporary register. */
 266 #define RSEQ_ASM_OP_R_ADD(count)                                                \
 267         "       add     " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG                \
 268                         ", %[" __rseq_str(count) "]\n"
 269
 270 /*
 271  * End-of-sequence store of temporary register to address @var. Emit
 272  * @post_commit_label label after the store instruction.
 273  */
 274 #define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label)                       \
 275         "       str     " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"         \
 276         __rseq_str(post_commit_label) ":\n"
 277
 278 /*
 279  * Copy @len bytes from @src to @dst. This is an inefficient bytewise
 280  * copy and could be improved in the future.
 281  */
 282 #define RSEQ_ASM_OP_R_BYTEWISE_MEMCPY(dst, src, len)                            \
 283         "       cbz     %[" __rseq_str(len) "], 333f\n"                         \
 284         "       mov     " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n"       \
 285         "222:   sub     " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n"   \
 286         "       ldrb    " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]"        \
 287                         ", " RSEQ_ASM_TMP_REG_2 "]\n"                           \
 288         "       strb    " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]"        \
 289                         ", " RSEQ_ASM_TMP_REG_2 "]\n"                           \
 290         "       cbnz    " RSEQ_ASM_TMP_REG_2 ", 222b\n"                         \
 291         "333:\n"
 292
 293 /* Per-cpu-id indexing. */
 294
 295 #define RSEQ_TEMPLATE_INDEX_CPU_ID
 296 #define RSEQ_TEMPLATE_MO_RELAXED
 297 #include "rseq/arch/aarch64/bits.h"
 298 #undef RSEQ_TEMPLATE_MO_RELAXED
 299
 300 #define RSEQ_TEMPLATE_MO_RELEASE
 301 #include "rseq/arch/aarch64/bits.h"
 302 #undef RSEQ_TEMPLATE_MO_RELEASE
 303 #undef RSEQ_TEMPLATE_INDEX_CPU_ID
 304
 305 /* Per-mm-cid indexing. */
 306
 307 #define RSEQ_TEMPLATE_INDEX_MM_CID
 308 #define RSEQ_TEMPLATE_MO_RELAXED
 309 #include "rseq/arch/aarch64/bits.h"
 310 #undef RSEQ_TEMPLATE_MO_RELAXED
 311
 312 #define RSEQ_TEMPLATE_MO_RELEASE
 313 #include "rseq/arch/aarch64/bits.h"
 314 #undef RSEQ_TEMPLATE_MO_RELEASE
 315 #undef RSEQ_TEMPLATE_INDEX_MM_CID
 316
 317 /* APIs which are not indexed. */
 318
 319 #define RSEQ_TEMPLATE_INDEX_NONE
 320 #define RSEQ_TEMPLATE_MO_RELAXED
 321 #include "rseq/arch/aarch64/bits.h"
 322 #undef RSEQ_TEMPLATE_MO_RELAXED
 323 #undef RSEQ_TEMPLATE_INDEX_NONE