e2ae825878af7c932f96706b5487a8740e7d5873
[librseq.git] / include / rseq / arch / aarch64.h
1 /* SPDX-License-Identifier: MIT */
2 /* SPDX-FileCopyrightText: 2016-2024 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
3 /* SPDX-FileCopyrightText: 2018 Will Deacon <will.deacon@arm.com> */
4
5 /*
6 * rseq/arch/aarch64.h
7 */
8
9 #ifndef _RSEQ_RSEQ_H
10 #error "Never use <rseq/arch/aarch64.h> directly; include <rseq/rseq.h> instead."
11 #endif
12
13 /*
14 * RSEQ_ASM_*() macro helpers are internal to the librseq headers. Those
15 * are not part of the public API.
16 */
17
18 /*
19 * aarch64 -mbig-endian generates mixed endianness code vs data:
20 * little-endian code and big-endian data. Ensure the RSEQ_SIG signature
21 * matches code endianness.
22 */
23 #define RSEQ_SIG_CODE 0xd428bc00 /* BRK #0x45E0. */
24
25 #ifdef __AARCH64EB__ /* Big endian */
26 # define RSEQ_SIG_DATA 0x00bc28d4 /* BRK #0x45E0. */
27 #else /* Little endian */
28 # define RSEQ_SIG_DATA RSEQ_SIG_CODE
29 #endif
30
31 #define RSEQ_SIG RSEQ_SIG_DATA
32
33 /*
34 * Refer to the Linux kernel memory model (LKMM) for documentation of
35 * the memory barriers.
36 */
37
38 /* CPU memory barrier. */
39 #define rseq_smp_mb() __asm__ __volatile__ ("dmb ish" ::: "memory")
40 /* CPU read memory barrier */
41 #define rseq_smp_rmb() __asm__ __volatile__ ("dmb ishld" ::: "memory")
42 /* CPU write memory barrier */
43 #define rseq_smp_wmb() __asm__ __volatile__ ("dmb ishst" ::: "memory")
44
45 /* Acquire: One-way permeable barrier. */
46 #define rseq_smp_load_acquire(p) \
47 __extension__ ({ \
48 union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u; \
49 switch (sizeof(*(p))) { \
50 case 1: \
51 __asm__ __volatile__ ("ldarb %w0, %1" \
52 : "=r" (*(__u8 *)__u.__c) \
53 : "Q" (*(p)) : "memory"); \
54 break; \
55 case 2: \
56 __asm__ __volatile__ ("ldarh %w0, %1" \
57 : "=r" (*(__u16 *)__u.__c) \
58 : "Q" (*(p)) : "memory"); \
59 break; \
60 case 4: \
61 __asm__ __volatile__ ("ldar %w0, %1" \
62 : "=r" (*(__u32 *)__u.__c) \
63 : "Q" (*(p)) : "memory"); \
64 break; \
65 case 8: \
66 __asm__ __volatile__ ("ldar %0, %1" \
67 : "=r" (*(__u64 *)__u.__c) \
68 : "Q" (*(p)) : "memory"); \
69 break; \
70 } \
71 (rseq_unqual_scalar_typeof(*(p)))__u.__val; \
72 })
73
74 /* Acquire barrier after control dependency. */
75 #define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
76
77 /* Release: One-way permeable barrier. */
78 #define rseq_smp_store_release(p, v) \
79 do { \
80 union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u = \
81 { .__val = (rseq_unqual_scalar_typeof(*(p))) (v) }; \
82 switch (sizeof(*(p))) { \
83 case 1: \
84 __asm__ __volatile__ ("stlrb %w1, %0" \
85 : "=Q" (*(p)) \
86 : "r" (*(__u8 *)__u.__c) \
87 : "memory"); \
88 break; \
89 case 2: \
90 __asm__ __volatile__ ("stlrh %w1, %0" \
91 : "=Q" (*(p)) \
92 : "r" (*(__u16 *)__u.__c) \
93 : "memory"); \
94 break; \
95 case 4: \
96 __asm__ __volatile__ ("stlr %w1, %0" \
97 : "=Q" (*(p)) \
98 : "r" (*(__u32 *)__u.__c) \
99 : "memory"); \
100 break; \
101 case 8: \
102 __asm__ __volatile__ ("stlr %1, %0" \
103 : "=Q" (*(p)) \
104 : "r" (*(__u64 *)__u.__c) \
105 : "memory"); \
106 break; \
107 } \
108 } while (0)
109
110 #define RSEQ_ASM_U64_PTR(x) ".quad " x
111 #define RSEQ_ASM_U32(x) ".long " x
112
113 /* Temporary scratch registers. */
114 #define RSEQ_ASM_TMP_REG32 "w15"
115 #define RSEQ_ASM_TMP_REG "x15"
116 #define RSEQ_ASM_TMP_REG_2 "x14"
117
118 /* Only used in RSEQ_ASM_DEFINE_TABLE. */
119 #define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \
120 post_commit_offset, abort_ip) \
121 " .pushsection __rseq_cs, \"aw\"\n" \
122 " .balign 32\n" \
123 __rseq_str(label) ":\n" \
124 " " RSEQ_ASM_U32(__rseq_str(version)) "\n" \
125 " " RSEQ_ASM_U32(__rseq_str(flags)) "\n" \
126 " " RSEQ_ASM_U64_PTR(__rseq_str(start_ip)) "\n" \
127 " " RSEQ_ASM_U64_PTR(__rseq_str(post_commit_offset)) "\n" \
128 " " RSEQ_ASM_U64_PTR(__rseq_str(abort_ip)) "\n" \
129 " .popsection\n\t" \
130 " .pushsection __rseq_cs_ptr_array, \"aw\"\n" \
131 " " RSEQ_ASM_U64_PTR(__rseq_str(label) "b") "\n" \
132 " .popsection\n"
133
134 /*
135 * Define an rseq critical section structure of version 0 with no flags.
136 *
137 * @label:
138 * Local label for the beginning of the critical section descriptor
139 * structure.
140 * @start_ip:
141 * Pointer to the first instruction of the sequence of consecutive assembly
142 * instructions.
143 * @post_commit_ip:
144 * Pointer to the instruction after the last instruction of the sequence of
145 * consecutive assembly instructions.
146 * @abort_ip:
147 * Pointer to the instruction where to move the execution flow in case of
148 * abort of the sequence of consecutive assembly instructions.
149 */
150 #define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
151 __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
152 (post_commit_ip) - (start_ip), abort_ip)
153
154 /*
155 * Define the @exit_ip pointer as an exit point for the sequence of consecutive
156 * assembly instructions at @start_ip.
157 *
158 * @start_ip:
159 * Pointer to the first instruction of the sequence of consecutive assembly
160 * instructions.
161 * @exit_ip:
162 * Pointer to an exit point instruction.
163 *
164 * Exit points of a rseq critical section consist of all instructions outside
165 * of the critical section where a critical section can either branch to or
166 * reach through the normal course of its execution. The abort IP and the
167 * post-commit IP are already part of the __rseq_cs section and should not be
168 * explicitly defined as additional exit points. Knowing all exit points is
169 * useful to assist debuggers stepping over the critical section.
170 */
171 #define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
172 " .pushsection __rseq_exit_point_array, \"aw\"\n" \
173 " " RSEQ_ASM_U64_PTR(__rseq_str(start_ip)) "\n" \
174 " " RSEQ_ASM_U64_PTR(__rseq_str(exit_ip)) "\n" \
175 " .popsection\n"
176
177 /*
178 * Define a critical section abort handler.
179 *
180 * @label:
181 * Local label to the abort handler.
182 * @teardown:
183 * Sequence of instructions to run on abort.
184 * @abort_label:
185 * C label to jump to at the end of the sequence.
186 */
187 #define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \
188 " b 222f\n" \
189 " .inst " __rseq_str(RSEQ_SIG_CODE) "\n" \
190 __rseq_str(label) ":\n" \
191 teardown \
192 " b %l[" __rseq_str(abort_label) "]\n" \
193 "222:\n"
194
195 /* Jump to local label @label when @cpu_id != @current_cpu_id. */
196 #define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
197 RSEQ_INJECT_ASM(1) \
198 " adrp " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n" \
199 " add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
200 ", :lo12:" __rseq_str(cs_label) "\n" \
201 " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n" \
202 __rseq_str(label) ":\n"
203
204 /* Store @value to address @var. */
205 #define RSEQ_ASM_OP_STORE(value, var) \
206 " str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
207
208 /* Store-release @value to address @var. */
209 #define RSEQ_ASM_OP_STORE_RELEASE(value, var) \
210 " stlr %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
211
212 /*
213 * End-of-sequence store of @value to address @var. Emit
214 * @post_commit_label label after the store instruction.
215 */
216 #define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \
217 RSEQ_ASM_OP_STORE(value, var) \
218 __rseq_str(post_commit_label) ":\n"
219
220 /*
221 * End-of-sequence store-release of @value to address @var. Emit
222 * @post_commit_label label after the store instruction.
223 */
224 #define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \
225 RSEQ_ASM_OP_STORE_RELEASE(value, var) \
226 __rseq_str(post_commit_label) ":\n"
227
228 /* Jump to local label @label when @var != @expect. */
229 #define RSEQ_ASM_OP_CBNE(var, expect, label) \
230 " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
231 " sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
232 ", %[" __rseq_str(expect) "]\n" \
233 " cbnz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
234
235 /*
236 * Jump to local label @label when @var != @expect (32-bit register
237 * comparison).
238 */
239 #define RSEQ_ASM_OP_CBNE32(var, expect, label) \
240 " ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \
241 " sub " RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32 \
242 ", %w[" __rseq_str(expect) "]\n" \
243 " cbnz " RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n"
244
245 /* Jump to local label @label when @var == @expect. */
246 #define RSEQ_ASM_OP_CBEQ(var, expect, label) \
247 " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
248 " sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
249 ", %[" __rseq_str(expect) "]\n" \
250 " cbz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
251
252 /* Jump to local label @label when @cpu_id != @current_cpu_id. */
253 #define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label) \
254 RSEQ_INJECT_ASM(2) \
255 RSEQ_ASM_OP_CBNE32(current_cpu_id, cpu_id, label)
256
257 /* Load @var into temporary register. */
258 #define RSEQ_ASM_OP_R_LOAD(var) \
259 " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
260
261 /* Store from temporary register into @var. */
262 #define RSEQ_ASM_OP_R_STORE(var) \
263 " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
264
265 /* Load from address in temporary register+@offset into temporary register. */
266 #define RSEQ_ASM_OP_R_LOAD_OFF(offset) \
267 " ldr " RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG \
268 ", %[" __rseq_str(offset) "]]\n"
269
270 /* Add @count to temporary register. */
271 #define RSEQ_ASM_OP_R_ADD(count) \
272 " add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
273 ", %[" __rseq_str(count) "]\n"
274
275 /*
276 * End-of-sequence store of temporary register to address @var. Emit
277 * @post_commit_label label after the store instruction.
278 */
279 #define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \
280 " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
281 __rseq_str(post_commit_label) ":\n"
282
283 /*
284 * Copy @len bytes from @src to @dst. This is an inefficient bytewise
285 * copy and could be improved in the future.
286 */
287 #define RSEQ_ASM_OP_R_BYTEWISE_MEMCPY(dst, src, len) \
288 " cbz %[" __rseq_str(len) "], 333f\n" \
289 " mov " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n" \
290 "222: sub " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n" \
291 " ldrb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]" \
292 ", " RSEQ_ASM_TMP_REG_2 "]\n" \
293 " strb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]" \
294 ", " RSEQ_ASM_TMP_REG_2 "]\n" \
295 " cbnz " RSEQ_ASM_TMP_REG_2 ", 222b\n" \
296 "333:\n"
297
298 /* Per-cpu-id indexing. */
299
300 #define RSEQ_TEMPLATE_INDEX_CPU_ID
301 #define RSEQ_TEMPLATE_MO_RELAXED
302 #include "rseq/arch/aarch64/bits.h"
303 #undef RSEQ_TEMPLATE_MO_RELAXED
304
305 #define RSEQ_TEMPLATE_MO_RELEASE
306 #include "rseq/arch/aarch64/bits.h"
307 #undef RSEQ_TEMPLATE_MO_RELEASE
308 #undef RSEQ_TEMPLATE_INDEX_CPU_ID
309
310 /* Per-mm-cid indexing. */
311
312 #define RSEQ_TEMPLATE_INDEX_MM_CID
313 #define RSEQ_TEMPLATE_MO_RELAXED
314 #include "rseq/arch/aarch64/bits.h"
315 #undef RSEQ_TEMPLATE_MO_RELAXED
316
317 #define RSEQ_TEMPLATE_MO_RELEASE
318 #include "rseq/arch/aarch64/bits.h"
319 #undef RSEQ_TEMPLATE_MO_RELEASE
320 #undef RSEQ_TEMPLATE_INDEX_MM_CID
321
322 /* APIs which are not indexed. */
323
324 #define RSEQ_TEMPLATE_INDEX_NONE
325 #define RSEQ_TEMPLATE_MO_RELAXED
326 #include "rseq/arch/aarch64/bits.h"
327 #undef RSEQ_TEMPLATE_MO_RELAXED
328 #undef RSEQ_TEMPLATE_INDEX_NONE
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